1/*
2 * Aic7xxx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-2000 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.reg 63457 2000-07-18 20:12:14Z gibbs $
32 */
33
34/*
35 * This file is processed by the aic7xxx_asm utility for use in assembling
36 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
37 * a C header file for use in the kernel portion of the Aic7xxx driver.
38 *
39 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
40 * Adaptec's Technical Documents Department 1-800-934-2766
41 */
42
43/*
44 * SCSI Sequence Control (p. 3-11).
45 * Each bit, when set starts a specific SCSI sequence on the bus
46 */
47register SCSISEQ {
48 address 0x000
49 access_mode RW
50 bit TEMODE 0x80
51 bit ENSELO 0x40
52 bit ENSELI 0x20
53 bit ENRSELI 0x10
54 bit ENAUTOATNO 0x08
55 bit ENAUTOATNI 0x04
56 bit ENAUTOATNP 0x02
57 bit SCSIRSTO 0x01
58}
59
60/*
61 * SCSI Transfer Control 0 Register (pp. 3-13).
62 * Controls the SCSI module data path.
63 */
64register SXFRCTL0 {
65 address 0x001
66 access_mode RW
67 bit DFON 0x80
68 bit DFPEXP 0x40
69 bit FAST20 0x20
70 bit CLRSTCNT 0x10
71 bit SPIOEN 0x08
72 bit SCAMEN 0x04
73 bit CLRCHN 0x02
74}
75
76/*
77 * SCSI Transfer Control 1 Register (pp. 3-14,15).
78 * Controls the SCSI module data path.
79 */
80register SXFRCTL1 {
81 address 0x002
82 access_mode RW
83 bit BITBUCKET 0x80
84 bit SWRAPEN 0x40
85 bit ENSPCHK 0x20
86 mask STIMESEL 0x18
87 bit ENSTIMER 0x04
88 bit ACTNEGEN 0x02
89 bit STPWEN 0x01 /* Powered Termination */
90}
91
92/*
93 * SCSI Control Signal Read Register (p. 3-15).
94 * Reads the actual state of the SCSI bus pins
95 */
96register SCSISIGI {
97 address 0x003
98 access_mode RO
99 bit CDI 0x80
100 bit IOI 0x40
101 bit MSGI 0x20
102 bit ATNI 0x10
103 bit SELI 0x08
104 bit BSYI 0x04
105 bit REQI 0x02
106 bit ACKI 0x01
107/*
108 * Possible phases in SCSISIGI
109 */
110 mask PHASE_MASK CDI|IOI|MSGI
111 mask P_DATAOUT 0x00
112 mask P_DATAIN IOI
113 mask P_COMMAND CDI
114 mask P_MESGOUT CDI|MSGI
115 mask P_STATUS CDI|IOI
116 mask P_MESGIN CDI|IOI|MSGI
117}
118
119/*
120 * SCSI Control Signal Write Register (p. 3-16).
121 * Writing to this register modifies the control signals on the bus. Only
122 * those signals that are allowed in the current mode (Initiator/Target) are
123 * asserted.
124 */
125register SCSISIGO {
126 address 0x003
127 access_mode WO
128 bit CDO 0x80
129 bit IOO 0x40
130 bit MSGO 0x20
131 bit ATNO 0x10
132 bit SELO 0x08
133 bit BSYO 0x04
134 bit REQO 0x02
135 bit ACKO 0x01
136/*
137 * Possible phases to write into SCSISIG0
138 */
139 mask PHASE_MASK CDI|IOI|MSGI
140 mask P_DATAOUT 0x00
141 mask P_DATAIN IOI
142 mask P_COMMAND CDI
143 mask P_MESGOUT CDI|MSGI
144 mask P_STATUS CDI|IOI
145 mask P_MESGIN CDI|IOI|MSGI
146}
147
148/*
149 * SCSI Rate Control (p. 3-17).
150 * Contents of this register determine the Synchronous SCSI data transfer
151 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
152 * SOFS (3:0) bits disables synchronous data transfers. Any offset value
153 * greater than 0 enables synchronous transfers.
154 */
155register SCSIRATE {
156 address 0x004
157 access_mode RW
158 bit WIDEXFER 0x80 /* Wide transfer control */
159 bit ENABLE_CRC 0x40 /* CRC for D-Phases */
160 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */
161 mask SXFR 0x70 /* Sync transfer rate */
162 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */
163 mask SOFS 0x0f /* Sync offset */
164}
165
166/*
167 * SCSI ID (p. 3-18).
168 * Contains the ID of the board and the current target on the
169 * selected channel.
170 */
171register SCSIID {
172 address 0x005
173 access_mode RW
174 mask TID 0xf0 /* Target ID mask */
175 mask TWIN_TID 0x70
176 bit TWIN_CHNLB 0x80
177 mask OID 0x0f /* Our ID mask */
178 /*
179 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
180 * The aic7890/91 allow an offset of up to 127 transfers in both wide
181 * and narrow mode.
182 */
183 alias SCSIOFFSET
184 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
185}
186
187/*
188 * SCSI Latched Data (p. 3-19).
189 * Read/Write latches used to transfer data on the SCSI bus during
190 * Automatic or Manual PIO mode. SCSIDATH can be used for the
191 * upper byte of a 16bit wide asynchronouse data phase transfer.
192 */
193register SCSIDATL {
194 address 0x006
195 access_mode RW
196}
197
198register SCSIDATH {
199 address 0x007
200 access_mode RW
201}
202
203/*
204 * SCSI Transfer Count (pp. 3-19,20)
205 * These registers count down the number of bytes transferred
206 * across the SCSI bus. The counter is decremented only once
207 * the data has been safely transferred. SDONE in SSTAT0 is
208 * set when STCNT goes to 0
209 */
210register STCNT {
211 address 0x008
212 size 3
213 access_mode RW
214}
215
216/* ALT_MODE register on Ultra160 chips */
217register OPTIONMODE {
218 address 0x008
219 access_mode RW
220 bit AUTORATEEN 0x80
221 bit AUTOACKEN 0x40
222 bit ATNMGMNTEN 0x20
223 bit BUSFREEREV 0x10
224 bit EXPPHASEDIS 0x08
225 bit SCSIDATL_IMGEN 0x04
226 bit AUTO_MSGOUT_DE 0x02
227 bit DIS_MSGIN_DUALEDGE 0x01
228 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
229}
230
231/* ALT_MODE register on Ultra160 chips */
232register TARGCRCCNT {
233 address 0x00a
234 size 2
235 access_mode RW
236}
237
238/*
239 * Clear SCSI Interrupt 0 (p. 3-20)
240 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
241 */
242register CLRSINT0 {
243 address 0x00b
244 access_mode WO
245 bit CLRSELDO 0x40
246 bit CLRSELDI 0x20
247 bit CLRSELINGO 0x10
248 bit CLRSWRAP 0x08
249 bit CLRSPIORDY 0x02
250}
251
252/*
253 * SCSI Status 0 (p. 3-21)
254 * Contains one set of SCSI Interrupt codes
255 * These are most likely of interest to the sequencer
256 */
257register SSTAT0 {
258 address 0x00b
259 access_mode RO
260 bit TARGET 0x80 /* Board acting as target */
261 bit SELDO 0x40 /* Selection Done */
262 bit SELDI 0x20 /* Board has been selected */
263 bit SELINGO 0x10 /* Selection In Progress */
264 bit SWRAP 0x08 /* 24bit counter wrap */
265 bit IOERR 0x08 /* LVD Tranceiver mode changed */
266 bit SDONE 0x04 /* STCNT = 0x000000 */
267 bit SPIORDY 0x02 /* SCSI PIO Ready */
268 bit DMADONE 0x01 /* DMA transfer completed */
269}
270
271/*
272 * Clear SCSI Interrupt 1 (p. 3-23)
273 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
274 */
275register CLRSINT1 {
276 address 0x00c
277 access_mode WO
278 bit CLRSELTIMEO 0x80
279 bit CLRATNO 0x40
280 bit CLRSCSIRSTI 0x20
281 bit CLRBUSFREE 0x08
282 bit CLRSCSIPERR 0x04
283 bit CLRPHASECHG 0x02
284 bit CLRREQINIT 0x01
285}
286
287/*
288 * SCSI Status 1 (p. 3-24)
289 */
290register SSTAT1 {
291 address 0x00c
292 access_mode RO
293 bit SELTO 0x80
294 bit ATNTARG 0x40
295 bit SCSIRSTI 0x20
296 bit PHASEMIS 0x10
297 bit BUSFREE 0x08
298 bit SCSIPERR 0x04
299 bit PHASECHG 0x02
300 bit REQINIT 0x01
301}
302
303/*
304 * SCSI Status 2 (pp. 3-25,26)
305 */
306register SSTAT2 {
307 address 0x00d
308 access_mode RO
309 bit OVERRUN 0x80
310 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */
311 mask SFCNT 0x1f
312}
313
314/*
315 * SCSI Status 3 (p. 3-26)
316 */
317register SSTAT3 {
318 address 0x00e
319 access_mode RO
320 mask SCSICNT 0xf0
321 mask OFFCNT 0x0f
322}
323
324/*
325 * SCSI ID for the aic7890/91 chips
326 */
327register SCSIID_ULTRA2 {
328 address 0x00f
329 access_mode RW
330 mask TID 0xf0 /* Target ID mask */
331 mask OID 0x0f /* Our ID mask */
332}
333
334/*
335 * SCSI Interrupt Mode 1 (p. 3-28)
336 * Setting any bit will enable the corresponding function
337 * in SIMODE0 to interrupt via the IRQ pin.
338 */
339register SIMODE0 {
340 address 0x010
341 access_mode RW
342 bit ENSELDO 0x40
343 bit ENSELDI 0x20
344 bit ENSELINGO 0x10
345 bit ENSWRAP 0x08
346 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */
347 bit ENSDONE 0x04
348 bit ENSPIORDY 0x02
349 bit ENDMADONE 0x01
350}
351
352/*
353 * SCSI Interrupt Mode 1 (pp. 3-28,29)
354 * Setting any bit will enable the corresponding function
355 * in SIMODE1 to interrupt via the IRQ pin.
356 */
357register SIMODE1 {
358 address 0x011
359 access_mode RW
360 bit ENSELTIMO 0x80
361 bit ENATNTARG 0x40
362 bit ENSCSIRST 0x20
363 bit ENPHASEMIS 0x10
364 bit ENBUSFREE 0x08
365 bit ENSCSIPERR 0x04
366 bit ENPHASECHG 0x02
367 bit ENREQINIT 0x01
368}
369
370/*
371 * SCSI Data Bus (High) (p. 3-29)
372 * This register reads data on the SCSI Data bus directly.
373 */
374register SCSIBUSL {
375 address 0x012
376 access_mode RO
377}
378
379register SCSIBUSH {
380 address 0x013
381 access_mode RO
382}
383
384/*
385 * SCSI/Host Address (p. 3-30)
386 * These registers hold the host address for the byte about to be
387 * transferred on the SCSI bus. They are counted up in the same
388 * manner as STCNT is counted down. SHADDR should always be used
389 * to determine the address of the last byte transferred since HADDR
390 * can be skewed by write ahead.
391 */
392register SHADDR {
393 address 0x014
394 size 4
395 access_mode RO
396}
397
398/*
399 * Selection Timeout Timer (p. 3-30)
400 */
401register SELTIMER {
402 address 0x018
403 access_mode RW
404 bit STAGE6 0x20
405 bit STAGE5 0x10
406 bit STAGE4 0x08
407 bit STAGE3 0x04
408 bit STAGE2 0x02
409 bit STAGE1 0x01
410 alias TARGIDIN
411}
412
413/*
414 * Selection/Reselection ID (p. 3-31)
415 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
416 * device did not set its own ID.
417 */
418register SELID {
419 address 0x019
420 access_mode RW
421 mask SELID_MASK 0xf0
422 bit ONEBIT 0x08
423}
424
425register SCAMCTL {
426 address 0x01a
427 access_mode RW
428 bit ENSCAMSELO 0x80
429 bit CLRSCAMSELID 0x40
430 bit ALTSTIM 0x20
431 bit DFLTTID 0x10
432 mask SCAMLVL 0x03
433}
434
435/*
436 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
437 */
438register TARGID {
439 address 0x01b
440 size 2
441 access_mode RW
442}
443
444/*
445 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
446 * Indicates if external logic has been attached to the chip to
447 * perform the tasks of accessing a serial eeprom, testing termination
448 * strength, and performing cable detection. On the aic7860, most of
449 * these features are handled on chip, but on the aic7855 an attached
450 * aic3800 does the grunt work.
451 */
452register SPIOCAP {
453 address 0x01b
454 access_mode RW
455 bit SOFT1 0x80
456 bit SOFT0 0x40
457 bit SOFTCMDEN 0x20
458 bit HAS_BRDCTL 0x10 /* External Board control */
459 bit SEEPROM 0x08 /* External serial eeprom logic */
460 bit EEPROM 0x04 /* Writable external BIOS ROM */
461 bit ROM 0x02 /* Logic for accessing external ROM */
462 bit SSPIOCPS 0x01 /* Termination and cable detection */
463}
464
465register BRDCTL {
466 address 0x01d
467 bit BRDDAT7 0x80
468 bit BRDDAT6 0x40
469 bit BRDDAT5 0x20
470 bit BRDSTB 0x10
471 bit BRDCS 0x08
472 bit BRDRW 0x04
473 bit BRDCTL1 0x02
474 bit BRDCTL0 0x01
475 /* 7890 Definitions */
476 bit BRDDAT4 0x10
477 bit BRDDAT3 0x08
478 bit BRDDAT2 0x04
479 bit BRDRW_ULTRA2 0x02
480 bit BRDSTB_ULTRA2 0x01
481}
482
483/*
484 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
485 * Controls the reading and writing of an external serial 1-bit
486 * EEPROM Device. In order to access the serial EEPROM, you must
487 * first set the SEEMS bit that generates a request to the memory
488 * port for access to the serial EEPROM device. When the memory
489 * port is not busy servicing another request, it reconfigures
490 * to allow access to the serial EEPROM. When this happens, SEERDY
491 * gets set high to verify that the memory port access has been
492 * granted.
493 *
494 * After successful arbitration for the memory port, the SEECS bit of
495 * the SEECTL register is connected to the chip select. The SEECK,
496 * SEEDO, and SEEDI are connected to the clock, data out, and data in
497 * lines respectively. The SEERDY bit of SEECTL is useful in that it
498 * gives us an 800 nsec timer. After a write to the SEECTL register,
499 * the SEERDY goes high 800 nsec later. The one exception to this is
500 * when we first request access to the memory port. The SEERDY goes
501 * high to signify that access has been granted and, for this case, has
502 * no implied timing.
503 *
504 * See 93cx6.c for detailed information on the protocol necessary to
505 * read the serial EEPROM.
506 */
507register SEECTL {
508 address 0x01e
509 bit EXTARBACK 0x80
510 bit EXTARBREQ 0x40
511 bit SEEMS 0x20
512 bit SEERDY 0x10
513 bit SEECS 0x08
514 bit SEECK 0x04
515 bit SEEDO 0x02
516 bit SEEDI 0x01
517}
518/*
519 * SCSI Block Control (p. 3-32)
520 * Controls Bus type and channel selection. In a twin channel configuration
521 * addresses 0x00-0x1e are gated to the appropriate channel based on this
522 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
523 * on a wide bus.
524 */
525register SBLKCTL {
526 address 0x01f
527 access_mode RW
528 bit DIAGLEDEN 0x80 /* Aic78X0 only */
529 bit DIAGLEDON 0x40 /* Aic78X0 only */
530 bit AUTOFLUSHDIS 0x20
531 bit SELBUSB 0x08
532 bit ENAB40 0x08 /* LVD transceiver active */
533 bit ENAB20 0x04 /* SE/HVD transceiver active */
534 bit SELWIDE 0x02
535 bit XCVR 0x01 /* External transceiver active */
536}
537
538/*
539 * Sequencer Control (p. 3-33)
540 * Error detection mode and speed configuration
541 */
542register SEQCTL {
543 address 0x060
544 access_mode RW
545 bit PERRORDIS 0x80
546 bit PAUSEDIS 0x40
547 bit FAILDIS 0x20
548 bit FASTMODE 0x10
549 bit BRKADRINTEN 0x08
550 bit STEP 0x04
551 bit SEQRESET 0x02
552 bit LOADRAM 0x01
553}
554
555/*
556 * Sequencer RAM Data (p. 3-34)
557 * Single byte window into the Scratch Ram area starting at the address
558 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
559 * four bytes in succession. The SEQADDRs will increment after the most
560 * significant byte is written
561 */
562register SEQRAM {
563 address 0x061
564 access_mode RW
565}
566
567/*
568 * Sequencer Address Registers (p. 3-35)
569 * Only the first bit of SEQADDR1 holds addressing information
570 */
571register SEQADDR0 {
572 address 0x062
573 access_mode RW
574}
575
576register SEQADDR1 {
577 address 0x063
578 access_mode RW
579 mask SEQADDR1_MASK 0x01
580}
581
582/*
583 * Accumulator
584 * We cheat by passing arguments in the Accumulator up to the kernel driver
585 */
586register ACCUM {
587 address 0x064
588 access_mode RW
589 accumulator
590}
591
592register SINDEX {
593 address 0x065
594 access_mode RW
595 sindex
596}
597
598register DINDEX {
599 address 0x066
600 access_mode RW
601}
602
603register ALLONES {
604 address 0x069
605 access_mode RO
606 allones
607}
608
609register ALLZEROS {
610 address 0x06a
611 access_mode RO
612 allzeros
613}
614
615register NONE {
616 address 0x06a
617 access_mode WO
618 none
619}
620
621register FLAGS {
622 address 0x06b
623 access_mode RO
624 bit ZERO 0x02
625 bit CARRY 0x01
626}
627
628register SINDIR {
629 address 0x06c
630 access_mode RO
631}
632
633register DINDIR {
634 address 0x06d
635 access_mode WO
636}
637
638register FUNCTION1 {
639 address 0x06e
640 access_mode RW
641}
642
643register STACK {
644 address 0x06f
645 access_mode RO
646}
647
648/*
649 * Board Control (p. 3-43)
650 */
651register BCTL {
652 address 0x084
653 access_mode RW
654 bit ACE 0x08
655 bit ENABLE 0x01
656}
657
658/*
659 * On the aic78X0 chips, Board Control is replaced by the DSCommand
660 * register (p. 4-64)
661 */
662register DSCOMMAND0 {
663 address 0x084
664 access_mode RW
665 bit CACHETHEN 0x80 /* Cache Threshold enable */
666 bit DPARCKEN 0x40 /* Data Parity Check Enable */
667 bit MPARCKEN 0x20 /* Memory Parity Check Enable */
668 bit EXTREQLCK 0x10 /* External Request Lock */
669 /* aic7890/91/96/97 only */
670 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */
671 bit RAMPS 0x04 /* External SCB RAM Present */
672 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
673 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */
674}
675
676/*
677 * Bus On/Off Time (p. 3-44)
678 */
679register BUSTIME {
680 address 0x085
681 access_mode RW
682 mask BOFF 0xf0
683 mask BON 0x0f
684}
685
686/*
687 * Bus Speed (p. 3-45) aic7770 only
688 */
689register BUSSPD {
690 address 0x086
691 access_mode RW
692 mask DFTHRSH 0xc0
693 mask STBOFF 0x38
694 mask STBON 0x07
695 mask DFTHRSH_100 0xc0
696}
697
698/* aic7850/55/60/70/80/95 only */
699register DSPCISTATUS {
700 address 0x086
701 mask DFTHRSH_100 0xc0
702}
703
704/* aic7890/91/96/97 only */
705register HS_MAILBOX {
706 address 0x086
707 mask HOST_MAILBOX 0xF0
708 mask SEQ_MAILBOX 0x0F
709 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
710}
711
712const HOST_MAILBOX_SHIFT 4
713const SEQ_MAILBOX_SHIFT 0
714
715/*
716 * Host Control (p. 3-47) R/W
717 * Overall host control of the device.
718 */
719register HCNTRL {
720 address 0x087
721 access_mode RW
722 bit POWRDN 0x40
723 bit SWINT 0x10
724 bit IRQMS 0x08
725 bit PAUSE 0x04
726 bit INTEN 0x02
727 bit CHIPRST 0x01
728 bit CHIPRSTACK 0x01
729}
730
731/*
732 * Host Address (p. 3-48)
733 * This register contains the address of the byte about
734 * to be transferred across the host bus.
735 */
736register HADDR {
737 address 0x088
738 size 4
739 access_mode RW
740}
741
742register HCNT {
743 address 0x08c
744 size 3
745 access_mode RW
746}
747
748/*
749 * SCB Pointer (p. 3-49)
750 * Gate one of the SCBs into the SCBARRAY window.
751 */
752register SCBPTR {
753 address 0x090
754 access_mode RW
755}
756
757/*
758 * Interrupt Status (p. 3-50)
759 * Status for system interrupts
760 */
761register INTSTAT {
762 address 0x091
763 access_mode RW
764 bit BRKADRINT 0x08
765 bit SCSIINT 0x04
766 bit CMDCMPLT 0x02
767 bit SEQINT 0x01
768 mask BAD_PHASE SEQINT /* unknown scsi bus phase */
769 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
770 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/
771 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
772 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
773 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
774 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */
775 mask TRACEPOINT2 0x90|SEQINT
776 mask HOST_MSG_LOOP 0xa0|SEQINT /*
777 * The bus is ready for the
778 * host to perform another
779 * message transaction. This
780 * mechanism is used for things
781 * like sync/wide negotiation
782 * that require a kernel based
783 * message state engine.
784 */
785 mask PERR_DETECTED 0xb0|SEQINT /*
786 * Either the phase_lock
787 * or inb_next routine has
788 * noticed a parity error.
789 */
790 mask TRACEPOINT 0xd0|SEQINT
791 mask DATA_OVERRUN 0xf0|SEQINT /*
792 * Target attempted to write
793 * beyond the bounds of its
794 * command.
795 */
796
797 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
798 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
799}
800
801/*
802 * Hard Error (p. 3-53)
803 * Reporting of catastrophic errors. You usually cannot recover from
804 * these without a full board reset.
805 */
806register ERROR {
807 address 0x092
808 access_mode RO
809 bit CIOPARERR 0x80 /* Ultra2 only */
810 bit PCIERRSTAT 0x40 /* PCI only */
811 bit MPARERR 0x20 /* PCI only */
812 bit DPARERR 0x10 /* PCI only */
813 bit SQPARERR 0x08
814 bit ILLOPCODE 0x04
815 bit ILLSADDR 0x02
816 bit ILLHADDR 0x01
817}
818
819/*
820 * Clear Interrupt Status (p. 3-52)
821 */
822register CLRINT {
823 address 0x092
824 access_mode WO
825 bit CLRPARERR 0x10 /* PCI only */
826 bit CLRBRKADRINT 0x08
827 bit CLRSCSIINT 0x04
828 bit CLRCMDINT 0x02
829 bit CLRSEQINT 0x01
830}
831
832register DFCNTRL {
833 address 0x093
834 access_mode RW
835 bit PRELOADEN 0x80 /* aic7890 only */
836 bit WIDEODD 0x40
837 bit SCSIEN 0x20
838 bit SDMAEN 0x10
839 bit SDMAENACK 0x10
840 bit HDMAEN 0x08
841 bit HDMAENACK 0x08
842 bit DIRECTION 0x04
843 bit FIFOFLUSH 0x02
844 bit FIFORESET 0x01
845}
846
847register DFSTATUS {
848 address 0x094
849 access_mode RO
850 bit PRELOAD_AVAIL 0x80
851 bit DWORDEMP 0x20
852 bit MREQPEND 0x10
853 bit HDONE 0x08
854 bit DFTHRESH 0x04
855 bit FIFOFULL 0x02
856 bit FIFOEMP 0x01
857}
858
859register DFWADDR {
860 address 0x95
861 access_mode RW
862}
863
864register DFRADDR {
865 address 0x97
866 access_mode RW
867}
868
869register DFDAT {
870 address 0x099
871 access_mode RW
872}
873
874/*
875 * SCB Auto Increment (p. 3-59)
876 * Byte offset into the SCB Array and an optional bit to allow auto
877 * incrementing of the address during download and upload operations
878 */
879register SCBCNT {
880 address 0x09a
881 access_mode RW
882 bit SCBAUTO 0x80
883 mask SCBCNT_MASK 0x1f
884}
885
886/*
887 * Queue In FIFO (p. 3-60)
888 * Input queue for queued SCBs (commands that the seqencer has yet to start)
889 */
890register QINFIFO {
891 address 0x09b
892 access_mode RW
893}
894
895/*
896 * Queue In Count (p. 3-60)
897 * Number of queued SCBs
898 */
899register QINCNT {
900 address 0x09c
901 access_mode RO
902}
903
904/*
905 * Queue Out FIFO (p. 3-61)
906 * Queue of SCBs that have completed and await the host
907 */
908register QOUTFIFO {
909 address 0x09d
910 access_mode WO
911}
912
913register CRCCONTROL1 {
914 address 0x09d
915 access_mode RW
916 bit CRCONSEEN 0x80
917 bit CRCVALCHKEN 0x40
918 bit CRCENDCHKEN 0x20
919 bit CRCREQCHKEN 0x10
920 bit TARGCRCENDEN 0x08
921 bit TARGCRCCNTEN 0x04
922}
923
924
925/*
926 * Queue Out Count (p. 3-61)
927 * Number of queued SCBs in the Out FIFO
928 */
929register QOUTCNT {
930 address 0x09e
931 access_mode RO
932}
933
934register SCSIPHASE {
935 address 0x09e
936 access_mode RO
937 bit STATUS_PHASE 0x20
938 bit COMMAND_PHASE 0x10
939 bit MSG_IN_PHASE 0x08
940 bit MSG_OUT_PHASE 0x04
941 bit DATA_IN_PHASE 0x02
942 bit DATA_OUT_PHASE 0x01
943}
944
945/*
946 * Special Function
947 */
948register SFUNCT {
949 address 0x09f
950 access_mode RW
951 bit ALT_MODE 0x80
952}
953
954/*
955 * SCB Definition (p. 5-4)
956 */
957scb {
958 address 0x0a0
959 SCB_CONTROL {
960 size 1
961 bit TARGET_SCB 0x80
962 bit DISCENB 0x40
963 bit TAG_ENB 0x20
964 bit MK_MESSAGE 0x10
965 bit ULTRAENB 0x08
966 bit DISCONNECTED 0x04
967 mask SCB_TAG_TYPE 0x03
968 }
969 SCB_SCSIID {
970 size 1
971 bit TWIN_CHNLB 0x80
972 mask TWIN_TID 0x70
973 mask TID 0xf0
974 mask OID 0x0f
975 }
976 SCB_LUN {
977 mask LID 0xff
978 size 1
979 }
980 SCB_CDB_LEN {
981 size 1
982 }
983 SCB_CDB_PTR {
984 size 4
985 alias SCB_RESIDUAL_DATACNT
986 alias SCB_CDB_STORE
987 alias SCB_TARGET_INFO
988 }
989 SCB_RESIDUAL_SGPTR {
990 size 4
991 }
992 SCB_SCSI_STATUS {
993 size 1
994 }
995 SCB_CDB_STORE_PAD {
996 size 3
997 }
998 SCB_DATAPTR {
999 size 4
1000 }
1001 SCB_DATACNT {
1002 /*
1003 * The last byte is really the high address bits for
1004 * the data address.
1005 */
1006 size 4
1007 bit SG_LAST_SEG 0x80 /* In the fourth byte */
1008 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
1009 }
1010 SCB_SGPTR {
1011 size 4
1012 bit SG_RESID_VALID 0x04 /* In the first byte */
1013 bit SG_FULL_RESID 0x02 /* In the first byte */
1014 bit SG_LIST_NULL 0x01 /* In the first byte */
1015 }
1016 SCB_TAG {
1017 size 1
1018 }
1019 SCB_SCSIRATE {
1020 size 1
1021 }
1022 SCB_SCSIOFFSET {
1023 size 1
1024 }
1025 SCB_NEXT {
1026 size 1
1027 }
1028 SCB_64_BTT {
1029 size 16
1030 }
1031 SCB_64_SPARE {
1032 size 16
1033 }
1034}
1035
1036const SCB_32BYTE_SIZE 30 /* Cards supporting 32byte scbs */
1037const SCB_64BYTE_SIZE 32 /* Cards supporting 64byte scbs */
1038
1039const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
1040
1041/* --------------------- AHA-2840-only definitions -------------------- */
1042
1043register SEECTL_2840 {
1044 address 0x0c0
1045 access_mode RW
1046 bit CS_2840 0x04
1047 bit CK_2840 0x02
1048 bit DO_2840 0x01
1049}
1050
1051register STATUS_2840 {
1052 address 0x0c1
1053 access_mode RW
1054 bit EEPROM_TF 0x80
1055 mask BIOS_SEL 0x60
1056 mask ADSEL 0x1e
1057 bit DI_2840 0x01
1058}
1059
1060/* --------------------- AIC-7870-only definitions -------------------- */
1061
1062register CCHADDR {
1063 address 0x0E0
1064 size 8
1065}
1066
1067register CCHCNT {
1068 address 0x0E8
1069}
1070
1071register CCSGRAM {
1072 address 0x0E9
1073}
1074
1075register CCSGADDR {
1076 address 0x0EA
1077}
1078
1079register CCSGCTL {
1080 address 0x0EB
1081 bit CCSGDONE 0x80
1082 bit CCSGEN 0x08
1083 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */
1084 bit CCSGRESET 0x01
1085}
1086
1087register CCSCBCNT {
1088 address 0xEF
1089}
1090
1091register CCSCBCTL {
1092 address 0x0EE
1093 bit CCSCBDONE 0x80
1094 bit ARRDONE 0x40 /* SCB Array prefetch done */
1095 bit CCARREN 0x10
1096 bit CCSCBEN 0x08
1097 bit CCSCBDIR 0x04
1098 bit CCSCBRESET 0x01
1099}
1100
1101register CCSCBADDR {
1102 address 0x0ED
1103}
1104
1105register CCSCBRAM {
1106 address 0xEC
1107}
1108
1109/*
1110 * SCB bank address (7895/7896/97 only)
1111 */
1112register SCBBADDR {
1113 address 0x0F0
1114 access_mode RW
1115}
1116
1117register CCSCBPTR {
1118 address 0x0F1
1119}
1120
1121register HNSCB_QOFF {
1122 address 0x0F4
1123}
1124
1125register SNSCB_QOFF {
1126 address 0x0F6
1127}
1128
1129register SDSCB_QOFF {
1130 address 0x0F8
1131}
1132
1133register QOFF_CTLSTA {
1134 address 0x0FA
1135 bit SCB_AVAIL 0x40
1136 bit SNSCB_ROLLOVER 0x20
1137 bit SDSCB_ROLLOVER 0x10
1138 mask SCB_QSIZE 0x07
1139 mask SCB_QSIZE_256 0x06
1140}
1141
1142register DFF_THRSH {
1143 address 0x0FB
1144 mask WR_DFTHRSH 0x70
1145 mask RD_DFTHRSH 0x07
1146 mask RD_DFTHRSH_MIN 0x00
1147 mask RD_DFTHRSH_25 0x01
1148 mask RD_DFTHRSH_50 0x02
1149 mask RD_DFTHRSH_63 0x03
1150 mask RD_DFTHRSH_75 0x04
1151 mask RD_DFTHRSH_85 0x05
1152 mask RD_DFTHRSH_90 0x06
1153 mask RD_DFTHRSH_MAX 0x07
1154 mask WR_DFTHRSH_MIN 0x00
1155 mask WR_DFTHRSH_25 0x10
1156 mask WR_DFTHRSH_50 0x20
1157 mask WR_DFTHRSH_63 0x30
1158 mask WR_DFTHRSH_75 0x40
1159 mask WR_DFTHRSH_85 0x50
1160 mask WR_DFTHRSH_90 0x60
1161 mask WR_DFTHRSH_MAX 0x70
1162}
1163
1164register SG_CACHE_PRE {
1165 access_mode WO
1166 address 0x0fc
1167 mask SG_ADDR_MASK 0xf8
1168 bit ODD_SEG 0x04
1169 bit LAST_SEG 0x02
1170 bit LAST_SEG_DONE 0x01
1171}
1172
1173register SG_CACHE_SHADOW {
1174 access_mode RO
1175 address 0x0fc
1176 mask SG_ADDR_MASK 0xf8
1177 bit ODD_SEG 0x04
1178 bit LAST_SEG 0x02
1179 bit LAST_SEG_DONE 0x01
1180}
1181/* ---------------------- Scratch RAM Offsets ------------------------- */
1182/* These offsets are either to values that are initialized by the board's
1183 * BIOS or are specified by the sequencer code.
1184 *
1185 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1186 * device information, 32-33 and 5a-5f as well. As it turns out, the
1187 * BIOS trashes 20-2f, writing the synchronous negotiation results
1188 * on top of the BIOS values, so we re-use those for our per-target
1189 * scratchspace (actually a value that can be copied directly into
1190 * SCSIRATE). The kernel driver will enable synchronous negotiation
1191 * for all targets that have a value other than 0 in the lower four
1192 * bits of the target scratch space. This should work regardless of
1193 * whether the bios has been installed.
1194 */
1195
1196scratch_ram {
1197 address 0x020
1198
1199 /*
1200 * 1 byte per target starting at this address for configuration values
1201 */
1202 CMDSIZE_TABLE {
1203 alias TARG_SCSIRATE
1204 size 8
1205 }
1206 BUSY_TARGETS {
1207 size 16
1208 }
1209 /*
1210 * Bit vector of targets that have ULTRA enabled.
1211 */
1212 ULTRA_ENB {
1213 size 2
1214 }
1215 /*
1216 * Bit vector of targets that have disconnection disabled.
1217 */
1218 DISC_DSB {
1219 size 2
1220 }
1221 /*
1222 * Single byte buffer used to designate the type or message
1223 * to send to a target.
1224 */
1225 MSG_OUT {
1226 size 1
1227 }
1228 /* Parameters for DMA Logic */
1229 DMAPARAMS {
1230 size 1
1231 bit PRELOADEN 0x80
1232 bit WIDEODD 0x40
1233 bit SCSIEN 0x20
1234 bit SDMAEN 0x10
1235 bit SDMAENACK 0x10
1236 bit HDMAEN 0x08
1237 bit HDMAENACK 0x08
1238 bit DIRECTION 0x04
1239 bit FIFOFLUSH 0x02
1240 bit FIFORESET 0x01
1241 }
1242 SEQ_FLAGS {
1243 size 1
1244 bit IDENTIFY_SEEN 0x80
1245 bit SCBPTR_VALID 0x40
1246 bit TARGET_CMD_IS_TAGGED 0x40
1247 bit DPHASE 0x20
1248 /* Target flags */
1249 bit TARG_CMD_PENDING 0x10
1250 bit CMDPHASE_PENDING 0x08
1251 bit DPHASE_PENDING 0x04
1252 bit SPHASE_PENDING 0x02
1253 bit NO_DISCONNECT 0x01
1254 }
1255 /*
1256 * Temporary storage for the
1257 * target/channel/lun of a
1258 * reconnecting target
1259 */
1260 SAVED_SCSIID {
1261 size 1
1262 }
1263 SAVED_LUN {
1264 size 1
1265 }
1266 /*
1267 * The last bus phase as seen by the sequencer.
1268 */
1269 LASTPHASE {
1270 size 1
1271 bit CDI 0x80
1272 bit IOI 0x40
1273 bit MSGI 0x20
1274 mask PHASE_MASK CDI|IOI|MSGI
1275 mask P_DATAOUT 0x00
1276 mask P_DATAIN IOI
1277 mask P_COMMAND CDI
1278 mask P_MESGOUT CDI|MSGI
1279 mask P_STATUS CDI|IOI
1280 mask P_MESGIN CDI|IOI|MSGI
1281 mask P_BUSFREE 0x01
1282 }
1283 /*
1284 * head of list of SCBs awaiting
1285 * selection
1286 */
1287 WAITING_SCBH {
1288 size 1
1289 }
1290 /*
1291 * head of list of SCBs that are
1292 * disconnected. Used for SCB
1293 * paging.
1294 */
1295 DISCONNECTED_SCBH {
1296 size 1
1297 }
1298 /*
1299 * head of list of SCBs that are
1300 * not in use. Used for SCB paging.
1301 */
1302 FREE_SCBH {
1303 size 1
1304 }
1305 /*
1306 * Address of the hardware scb array in the host.
1307 */
1308 HSCB_ADDR {
1309 size 4
1310 }
1311 /*
1312 * Base address of our shared data with the kernel driver in host
1313 * memory. This includes the qinfifo, qoutfifo, and target mode
1314 * incoming command queue.
1315 */
1316 SHARED_DATA_ADDR {
1317 size 4
1318 }
1319 KERNEL_QINPOS {
1320 size 1
1321 }
1322 QINPOS {
1323 size 1
1324 }
1325 QOUTPOS {
1326 size 1
1327 }
1328 /*
1329 * Kernel and sequencer offsets into the queue of
1330 * incoming target mode command descriptors. The
1331 * queue is full when the KERNEL_TQINPOS == TQINPOS.
1332 */
1333 KERNEL_TQINPOS {
1334 size 1
1335 }
1336 TQINPOS {
1337 size 1
1338 }
1339 ARG_1 {
1340 size 1
1341 mask SEND_MSG 0x80
1342 mask SEND_SENSE 0x40
1343 mask SEND_REJ 0x20
1344 mask MSGOUT_PHASEMIS 0x10
1345 mask EXIT_MSG_LOOP 0x08
1346 mask CONT_MSG_LOOP 0x04
1347 mask CONT_TARG_SESSION 0x02
1348 alias RETURN_1
1349 }
1350 ARG_2 {
1351 size 1
1352 alias RETURN_2
1353 }
1354
1355 /*
1356 * Snapshot of MSG_OUT taken after each message is sent.
1357 */
1358 LAST_MSG {
1359 size 1
1360 }
1361
1362 /*
1363 * Interrupt kernel for a message to this target on
1364 * the next transaction. This is usually used for
1365 * negotiation requests.
1366 */
1367 TARGET_MSG_REQUEST {
1368 size 2
1369 }
1370
1371 /*
1372 * Sequences the kernel driver has okayed for us. This allows
1373 * the driver to do things like prevent initiator or target
1374 * operations.
1375 */
1376 SCSISEQ_TEMPLATE {
1377 size 1
1378 bit ENSELO 0x40
1379 bit ENSELI 0x20
1380 bit ENRSELI 0x10
1381 bit ENAUTOATNO 0x08
1382 bit ENAUTOATNI 0x04
1383 bit ENAUTOATNP 0x02
1384 }
1385
1386 /*
1387 * Track whether the transfer byte count for
1388 * the current data phase is odd.
1389 */
1390 DATA_COUNT_ODD {
1391 size 1
1392 }
1393
1394 /*
1395 * The initiator specified tag for this target mode transaction.
1396 */
1397 INITIATOR_TAG {
1398 size 1
1399 }
1400
1401 /*
1402 * These are reserved registers in the card's scratch ram. Some of
1403 * the values are specified in the AHA2742 technical reference manual
1404 * and are initialized by the BIOS at boot time.
1405 */
1406 SCSICONF {
1407 address 0x05a
1408 size 1
1409 bit TERM_ENB 0x80
1410 bit RESET_SCSI 0x40
1411 bit ENSPCHK 0x20
1412 mask HSCSIID 0x07 /* our SCSI ID */
1413 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
1414 }
1415 HOSTCONF {
1416 address 0x05d
1417 size 1
1418 }
1419 HA_274_BIOSCTRL {
1420 address 0x05f
1421 size 1
1422 mask BIOSMODE 0x30
1423 mask BIOSDISABLED 0x30
1424 bit CHANNEL_B_PRIMARY 0x08
1425 }
1426 /*
1427 * Per target SCSI offset values for Ultra2 controllers.
1428 */
1429 TARG_OFFSET {
1430 address 0x070
1431 size 16
1432 }
1433}
1434
1435const TID_SHIFT 4
1436const SCB_LIST_NULL 0xff
1437const TARGET_CMD_CMPLT 0xfe
1438
1439const CCSGADDR_MAX 0x80
1440const CCSGRAM_MAXSEGS 16
1441
1442/* WDTR Message values */
1443const BUS_8_BIT 0x00
1444const BUS_16_BIT 0x01
1445const BUS_32_BIT 0x02
1446
1447/* Offset maximums */
1448const MAX_OFFSET_8BIT 0x0f
1449const MAX_OFFSET_16BIT 0x08
1450const MAX_OFFSET_ULTRA2 0x7f
1451const HOST_MSG 0xff
1452
1453/* Target mode command processing constants */
1454const CMD_GROUP_CODE_SHIFT 0x05
1455
1456const STATUS_BUSY 0x08
1457const STATUS_QUEUE_FULL 0x28
1458const SCB_TARGET_PHASES 0
1459const SCB_TARGET_DATA_DIR 1
1460const SCB_TARGET_STATUS 2
1461const SCB_INITIATOR_TAG 3
1462const TARGET_DATA_IN 1
1463
1464/*
1465 * Downloaded (kernel inserted) constants
1466 */
1467/* Offsets into the SCBID array where different data is stored */
1468const QOUTFIFO_OFFSET download
1469const QINFIFO_OFFSET download
2 * Aic7xxx register and scratch ram definitions.
3 *
4 * Copyright (c) 1994-2000 Justin Gibbs.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU Public License ("GPL").
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.reg 63457 2000-07-18 20:12:14Z gibbs $
32 */
33
34/*
35 * This file is processed by the aic7xxx_asm utility for use in assembling
36 * firmware for the aic7xxx family of SCSI host adapters as well as to generate
37 * a C header file for use in the kernel portion of the Aic7xxx driver.
38 *
39 * All page numbers refer to the Adaptec AIC-7770 Data Book available from
40 * Adaptec's Technical Documents Department 1-800-934-2766
41 */
42
43/*
44 * SCSI Sequence Control (p. 3-11).
45 * Each bit, when set starts a specific SCSI sequence on the bus
46 */
47register SCSISEQ {
48 address 0x000
49 access_mode RW
50 bit TEMODE 0x80
51 bit ENSELO 0x40
52 bit ENSELI 0x20
53 bit ENRSELI 0x10
54 bit ENAUTOATNO 0x08
55 bit ENAUTOATNI 0x04
56 bit ENAUTOATNP 0x02
57 bit SCSIRSTO 0x01
58}
59
60/*
61 * SCSI Transfer Control 0 Register (pp. 3-13).
62 * Controls the SCSI module data path.
63 */
64register SXFRCTL0 {
65 address 0x001
66 access_mode RW
67 bit DFON 0x80
68 bit DFPEXP 0x40
69 bit FAST20 0x20
70 bit CLRSTCNT 0x10
71 bit SPIOEN 0x08
72 bit SCAMEN 0x04
73 bit CLRCHN 0x02
74}
75
76/*
77 * SCSI Transfer Control 1 Register (pp. 3-14,15).
78 * Controls the SCSI module data path.
79 */
80register SXFRCTL1 {
81 address 0x002
82 access_mode RW
83 bit BITBUCKET 0x80
84 bit SWRAPEN 0x40
85 bit ENSPCHK 0x20
86 mask STIMESEL 0x18
87 bit ENSTIMER 0x04
88 bit ACTNEGEN 0x02
89 bit STPWEN 0x01 /* Powered Termination */
90}
91
92/*
93 * SCSI Control Signal Read Register (p. 3-15).
94 * Reads the actual state of the SCSI bus pins
95 */
96register SCSISIGI {
97 address 0x003
98 access_mode RO
99 bit CDI 0x80
100 bit IOI 0x40
101 bit MSGI 0x20
102 bit ATNI 0x10
103 bit SELI 0x08
104 bit BSYI 0x04
105 bit REQI 0x02
106 bit ACKI 0x01
107/*
108 * Possible phases in SCSISIGI
109 */
110 mask PHASE_MASK CDI|IOI|MSGI
111 mask P_DATAOUT 0x00
112 mask P_DATAIN IOI
113 mask P_COMMAND CDI
114 mask P_MESGOUT CDI|MSGI
115 mask P_STATUS CDI|IOI
116 mask P_MESGIN CDI|IOI|MSGI
117}
118
119/*
120 * SCSI Control Signal Write Register (p. 3-16).
121 * Writing to this register modifies the control signals on the bus. Only
122 * those signals that are allowed in the current mode (Initiator/Target) are
123 * asserted.
124 */
125register SCSISIGO {
126 address 0x003
127 access_mode WO
128 bit CDO 0x80
129 bit IOO 0x40
130 bit MSGO 0x20
131 bit ATNO 0x10
132 bit SELO 0x08
133 bit BSYO 0x04
134 bit REQO 0x02
135 bit ACKO 0x01
136/*
137 * Possible phases to write into SCSISIG0
138 */
139 mask PHASE_MASK CDI|IOI|MSGI
140 mask P_DATAOUT 0x00
141 mask P_DATAIN IOI
142 mask P_COMMAND CDI
143 mask P_MESGOUT CDI|MSGI
144 mask P_STATUS CDI|IOI
145 mask P_MESGIN CDI|IOI|MSGI
146}
147
148/*
149 * SCSI Rate Control (p. 3-17).
150 * Contents of this register determine the Synchronous SCSI data transfer
151 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
152 * SOFS (3:0) bits disables synchronous data transfers. Any offset value
153 * greater than 0 enables synchronous transfers.
154 */
155register SCSIRATE {
156 address 0x004
157 access_mode RW
158 bit WIDEXFER 0x80 /* Wide transfer control */
159 bit ENABLE_CRC 0x40 /* CRC for D-Phases */
160 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */
161 mask SXFR 0x70 /* Sync transfer rate */
162 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */
163 mask SOFS 0x0f /* Sync offset */
164}
165
166/*
167 * SCSI ID (p. 3-18).
168 * Contains the ID of the board and the current target on the
169 * selected channel.
170 */
171register SCSIID {
172 address 0x005
173 access_mode RW
174 mask TID 0xf0 /* Target ID mask */
175 mask TWIN_TID 0x70
176 bit TWIN_CHNLB 0x80
177 mask OID 0x0f /* Our ID mask */
178 /*
179 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
180 * The aic7890/91 allow an offset of up to 127 transfers in both wide
181 * and narrow mode.
182 */
183 alias SCSIOFFSET
184 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
185}
186
187/*
188 * SCSI Latched Data (p. 3-19).
189 * Read/Write latches used to transfer data on the SCSI bus during
190 * Automatic or Manual PIO mode. SCSIDATH can be used for the
191 * upper byte of a 16bit wide asynchronouse data phase transfer.
192 */
193register SCSIDATL {
194 address 0x006
195 access_mode RW
196}
197
198register SCSIDATH {
199 address 0x007
200 access_mode RW
201}
202
203/*
204 * SCSI Transfer Count (pp. 3-19,20)
205 * These registers count down the number of bytes transferred
206 * across the SCSI bus. The counter is decremented only once
207 * the data has been safely transferred. SDONE in SSTAT0 is
208 * set when STCNT goes to 0
209 */
210register STCNT {
211 address 0x008
212 size 3
213 access_mode RW
214}
215
216/* ALT_MODE register on Ultra160 chips */
217register OPTIONMODE {
218 address 0x008
219 access_mode RW
220 bit AUTORATEEN 0x80
221 bit AUTOACKEN 0x40
222 bit ATNMGMNTEN 0x20
223 bit BUSFREEREV 0x10
224 bit EXPPHASEDIS 0x08
225 bit SCSIDATL_IMGEN 0x04
226 bit AUTO_MSGOUT_DE 0x02
227 bit DIS_MSGIN_DUALEDGE 0x01
228 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
229}
230
231/* ALT_MODE register on Ultra160 chips */
232register TARGCRCCNT {
233 address 0x00a
234 size 2
235 access_mode RW
236}
237
238/*
239 * Clear SCSI Interrupt 0 (p. 3-20)
240 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
241 */
242register CLRSINT0 {
243 address 0x00b
244 access_mode WO
245 bit CLRSELDO 0x40
246 bit CLRSELDI 0x20
247 bit CLRSELINGO 0x10
248 bit CLRSWRAP 0x08
249 bit CLRSPIORDY 0x02
250}
251
252/*
253 * SCSI Status 0 (p. 3-21)
254 * Contains one set of SCSI Interrupt codes
255 * These are most likely of interest to the sequencer
256 */
257register SSTAT0 {
258 address 0x00b
259 access_mode RO
260 bit TARGET 0x80 /* Board acting as target */
261 bit SELDO 0x40 /* Selection Done */
262 bit SELDI 0x20 /* Board has been selected */
263 bit SELINGO 0x10 /* Selection In Progress */
264 bit SWRAP 0x08 /* 24bit counter wrap */
265 bit IOERR 0x08 /* LVD Tranceiver mode changed */
266 bit SDONE 0x04 /* STCNT = 0x000000 */
267 bit SPIORDY 0x02 /* SCSI PIO Ready */
268 bit DMADONE 0x01 /* DMA transfer completed */
269}
270
271/*
272 * Clear SCSI Interrupt 1 (p. 3-23)
273 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
274 */
275register CLRSINT1 {
276 address 0x00c
277 access_mode WO
278 bit CLRSELTIMEO 0x80
279 bit CLRATNO 0x40
280 bit CLRSCSIRSTI 0x20
281 bit CLRBUSFREE 0x08
282 bit CLRSCSIPERR 0x04
283 bit CLRPHASECHG 0x02
284 bit CLRREQINIT 0x01
285}
286
287/*
288 * SCSI Status 1 (p. 3-24)
289 */
290register SSTAT1 {
291 address 0x00c
292 access_mode RO
293 bit SELTO 0x80
294 bit ATNTARG 0x40
295 bit SCSIRSTI 0x20
296 bit PHASEMIS 0x10
297 bit BUSFREE 0x08
298 bit SCSIPERR 0x04
299 bit PHASECHG 0x02
300 bit REQINIT 0x01
301}
302
303/*
304 * SCSI Status 2 (pp. 3-25,26)
305 */
306register SSTAT2 {
307 address 0x00d
308 access_mode RO
309 bit OVERRUN 0x80
310 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */
311 mask SFCNT 0x1f
312}
313
314/*
315 * SCSI Status 3 (p. 3-26)
316 */
317register SSTAT3 {
318 address 0x00e
319 access_mode RO
320 mask SCSICNT 0xf0
321 mask OFFCNT 0x0f
322}
323
324/*
325 * SCSI ID for the aic7890/91 chips
326 */
327register SCSIID_ULTRA2 {
328 address 0x00f
329 access_mode RW
330 mask TID 0xf0 /* Target ID mask */
331 mask OID 0x0f /* Our ID mask */
332}
333
334/*
335 * SCSI Interrupt Mode 1 (p. 3-28)
336 * Setting any bit will enable the corresponding function
337 * in SIMODE0 to interrupt via the IRQ pin.
338 */
339register SIMODE0 {
340 address 0x010
341 access_mode RW
342 bit ENSELDO 0x40
343 bit ENSELDI 0x20
344 bit ENSELINGO 0x10
345 bit ENSWRAP 0x08
346 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */
347 bit ENSDONE 0x04
348 bit ENSPIORDY 0x02
349 bit ENDMADONE 0x01
350}
351
352/*
353 * SCSI Interrupt Mode 1 (pp. 3-28,29)
354 * Setting any bit will enable the corresponding function
355 * in SIMODE1 to interrupt via the IRQ pin.
356 */
357register SIMODE1 {
358 address 0x011
359 access_mode RW
360 bit ENSELTIMO 0x80
361 bit ENATNTARG 0x40
362 bit ENSCSIRST 0x20
363 bit ENPHASEMIS 0x10
364 bit ENBUSFREE 0x08
365 bit ENSCSIPERR 0x04
366 bit ENPHASECHG 0x02
367 bit ENREQINIT 0x01
368}
369
370/*
371 * SCSI Data Bus (High) (p. 3-29)
372 * This register reads data on the SCSI Data bus directly.
373 */
374register SCSIBUSL {
375 address 0x012
376 access_mode RO
377}
378
379register SCSIBUSH {
380 address 0x013
381 access_mode RO
382}
383
384/*
385 * SCSI/Host Address (p. 3-30)
386 * These registers hold the host address for the byte about to be
387 * transferred on the SCSI bus. They are counted up in the same
388 * manner as STCNT is counted down. SHADDR should always be used
389 * to determine the address of the last byte transferred since HADDR
390 * can be skewed by write ahead.
391 */
392register SHADDR {
393 address 0x014
394 size 4
395 access_mode RO
396}
397
398/*
399 * Selection Timeout Timer (p. 3-30)
400 */
401register SELTIMER {
402 address 0x018
403 access_mode RW
404 bit STAGE6 0x20
405 bit STAGE5 0x10
406 bit STAGE4 0x08
407 bit STAGE3 0x04
408 bit STAGE2 0x02
409 bit STAGE1 0x01
410 alias TARGIDIN
411}
412
413/*
414 * Selection/Reselection ID (p. 3-31)
415 * Upper four bits are the device id. The ONEBIT is set when the re/selecting
416 * device did not set its own ID.
417 */
418register SELID {
419 address 0x019
420 access_mode RW
421 mask SELID_MASK 0xf0
422 bit ONEBIT 0x08
423}
424
425register SCAMCTL {
426 address 0x01a
427 access_mode RW
428 bit ENSCAMSELO 0x80
429 bit CLRSCAMSELID 0x40
430 bit ALTSTIM 0x20
431 bit DFLTTID 0x10
432 mask SCAMLVL 0x03
433}
434
435/*
436 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
437 */
438register TARGID {
439 address 0x01b
440 size 2
441 access_mode RW
442}
443
444/*
445 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
446 * Indicates if external logic has been attached to the chip to
447 * perform the tasks of accessing a serial eeprom, testing termination
448 * strength, and performing cable detection. On the aic7860, most of
449 * these features are handled on chip, but on the aic7855 an attached
450 * aic3800 does the grunt work.
451 */
452register SPIOCAP {
453 address 0x01b
454 access_mode RW
455 bit SOFT1 0x80
456 bit SOFT0 0x40
457 bit SOFTCMDEN 0x20
458 bit HAS_BRDCTL 0x10 /* External Board control */
459 bit SEEPROM 0x08 /* External serial eeprom logic */
460 bit EEPROM 0x04 /* Writable external BIOS ROM */
461 bit ROM 0x02 /* Logic for accessing external ROM */
462 bit SSPIOCPS 0x01 /* Termination and cable detection */
463}
464
465register BRDCTL {
466 address 0x01d
467 bit BRDDAT7 0x80
468 bit BRDDAT6 0x40
469 bit BRDDAT5 0x20
470 bit BRDSTB 0x10
471 bit BRDCS 0x08
472 bit BRDRW 0x04
473 bit BRDCTL1 0x02
474 bit BRDCTL0 0x01
475 /* 7890 Definitions */
476 bit BRDDAT4 0x10
477 bit BRDDAT3 0x08
478 bit BRDDAT2 0x04
479 bit BRDRW_ULTRA2 0x02
480 bit BRDSTB_ULTRA2 0x01
481}
482
483/*
484 * Serial EEPROM Control (p. 4-92 in 7870 Databook)
485 * Controls the reading and writing of an external serial 1-bit
486 * EEPROM Device. In order to access the serial EEPROM, you must
487 * first set the SEEMS bit that generates a request to the memory
488 * port for access to the serial EEPROM device. When the memory
489 * port is not busy servicing another request, it reconfigures
490 * to allow access to the serial EEPROM. When this happens, SEERDY
491 * gets set high to verify that the memory port access has been
492 * granted.
493 *
494 * After successful arbitration for the memory port, the SEECS bit of
495 * the SEECTL register is connected to the chip select. The SEECK,
496 * SEEDO, and SEEDI are connected to the clock, data out, and data in
497 * lines respectively. The SEERDY bit of SEECTL is useful in that it
498 * gives us an 800 nsec timer. After a write to the SEECTL register,
499 * the SEERDY goes high 800 nsec later. The one exception to this is
500 * when we first request access to the memory port. The SEERDY goes
501 * high to signify that access has been granted and, for this case, has
502 * no implied timing.
503 *
504 * See 93cx6.c for detailed information on the protocol necessary to
505 * read the serial EEPROM.
506 */
507register SEECTL {
508 address 0x01e
509 bit EXTARBACK 0x80
510 bit EXTARBREQ 0x40
511 bit SEEMS 0x20
512 bit SEERDY 0x10
513 bit SEECS 0x08
514 bit SEECK 0x04
515 bit SEEDO 0x02
516 bit SEEDI 0x01
517}
518/*
519 * SCSI Block Control (p. 3-32)
520 * Controls Bus type and channel selection. In a twin channel configuration
521 * addresses 0x00-0x1e are gated to the appropriate channel based on this
522 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
523 * on a wide bus.
524 */
525register SBLKCTL {
526 address 0x01f
527 access_mode RW
528 bit DIAGLEDEN 0x80 /* Aic78X0 only */
529 bit DIAGLEDON 0x40 /* Aic78X0 only */
530 bit AUTOFLUSHDIS 0x20
531 bit SELBUSB 0x08
532 bit ENAB40 0x08 /* LVD transceiver active */
533 bit ENAB20 0x04 /* SE/HVD transceiver active */
534 bit SELWIDE 0x02
535 bit XCVR 0x01 /* External transceiver active */
536}
537
538/*
539 * Sequencer Control (p. 3-33)
540 * Error detection mode and speed configuration
541 */
542register SEQCTL {
543 address 0x060
544 access_mode RW
545 bit PERRORDIS 0x80
546 bit PAUSEDIS 0x40
547 bit FAILDIS 0x20
548 bit FASTMODE 0x10
549 bit BRKADRINTEN 0x08
550 bit STEP 0x04
551 bit SEQRESET 0x02
552 bit LOADRAM 0x01
553}
554
555/*
556 * Sequencer RAM Data (p. 3-34)
557 * Single byte window into the Scratch Ram area starting at the address
558 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
559 * four bytes in succession. The SEQADDRs will increment after the most
560 * significant byte is written
561 */
562register SEQRAM {
563 address 0x061
564 access_mode RW
565}
566
567/*
568 * Sequencer Address Registers (p. 3-35)
569 * Only the first bit of SEQADDR1 holds addressing information
570 */
571register SEQADDR0 {
572 address 0x062
573 access_mode RW
574}
575
576register SEQADDR1 {
577 address 0x063
578 access_mode RW
579 mask SEQADDR1_MASK 0x01
580}
581
582/*
583 * Accumulator
584 * We cheat by passing arguments in the Accumulator up to the kernel driver
585 */
586register ACCUM {
587 address 0x064
588 access_mode RW
589 accumulator
590}
591
592register SINDEX {
593 address 0x065
594 access_mode RW
595 sindex
596}
597
598register DINDEX {
599 address 0x066
600 access_mode RW
601}
602
603register ALLONES {
604 address 0x069
605 access_mode RO
606 allones
607}
608
609register ALLZEROS {
610 address 0x06a
611 access_mode RO
612 allzeros
613}
614
615register NONE {
616 address 0x06a
617 access_mode WO
618 none
619}
620
621register FLAGS {
622 address 0x06b
623 access_mode RO
624 bit ZERO 0x02
625 bit CARRY 0x01
626}
627
628register SINDIR {
629 address 0x06c
630 access_mode RO
631}
632
633register DINDIR {
634 address 0x06d
635 access_mode WO
636}
637
638register FUNCTION1 {
639 address 0x06e
640 access_mode RW
641}
642
643register STACK {
644 address 0x06f
645 access_mode RO
646}
647
648/*
649 * Board Control (p. 3-43)
650 */
651register BCTL {
652 address 0x084
653 access_mode RW
654 bit ACE 0x08
655 bit ENABLE 0x01
656}
657
658/*
659 * On the aic78X0 chips, Board Control is replaced by the DSCommand
660 * register (p. 4-64)
661 */
662register DSCOMMAND0 {
663 address 0x084
664 access_mode RW
665 bit CACHETHEN 0x80 /* Cache Threshold enable */
666 bit DPARCKEN 0x40 /* Data Parity Check Enable */
667 bit MPARCKEN 0x20 /* Memory Parity Check Enable */
668 bit EXTREQLCK 0x10 /* External Request Lock */
669 /* aic7890/91/96/97 only */
670 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */
671 bit RAMPS 0x04 /* External SCB RAM Present */
672 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
673 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */
674}
675
676/*
677 * Bus On/Off Time (p. 3-44)
678 */
679register BUSTIME {
680 address 0x085
681 access_mode RW
682 mask BOFF 0xf0
683 mask BON 0x0f
684}
685
686/*
687 * Bus Speed (p. 3-45) aic7770 only
688 */
689register BUSSPD {
690 address 0x086
691 access_mode RW
692 mask DFTHRSH 0xc0
693 mask STBOFF 0x38
694 mask STBON 0x07
695 mask DFTHRSH_100 0xc0
696}
697
698/* aic7850/55/60/70/80/95 only */
699register DSPCISTATUS {
700 address 0x086
701 mask DFTHRSH_100 0xc0
702}
703
704/* aic7890/91/96/97 only */
705register HS_MAILBOX {
706 address 0x086
707 mask HOST_MAILBOX 0xF0
708 mask SEQ_MAILBOX 0x0F
709 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
710}
711
712const HOST_MAILBOX_SHIFT 4
713const SEQ_MAILBOX_SHIFT 0
714
715/*
716 * Host Control (p. 3-47) R/W
717 * Overall host control of the device.
718 */
719register HCNTRL {
720 address 0x087
721 access_mode RW
722 bit POWRDN 0x40
723 bit SWINT 0x10
724 bit IRQMS 0x08
725 bit PAUSE 0x04
726 bit INTEN 0x02
727 bit CHIPRST 0x01
728 bit CHIPRSTACK 0x01
729}
730
731/*
732 * Host Address (p. 3-48)
733 * This register contains the address of the byte about
734 * to be transferred across the host bus.
735 */
736register HADDR {
737 address 0x088
738 size 4
739 access_mode RW
740}
741
742register HCNT {
743 address 0x08c
744 size 3
745 access_mode RW
746}
747
748/*
749 * SCB Pointer (p. 3-49)
750 * Gate one of the SCBs into the SCBARRAY window.
751 */
752register SCBPTR {
753 address 0x090
754 access_mode RW
755}
756
757/*
758 * Interrupt Status (p. 3-50)
759 * Status for system interrupts
760 */
761register INTSTAT {
762 address 0x091
763 access_mode RW
764 bit BRKADRINT 0x08
765 bit SCSIINT 0x04
766 bit CMDCMPLT 0x02
767 bit SEQINT 0x01
768 mask BAD_PHASE SEQINT /* unknown scsi bus phase */
769 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
770 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/
771 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
772 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
773 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
774 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */
775 mask TRACEPOINT2 0x90|SEQINT
776 mask HOST_MSG_LOOP 0xa0|SEQINT /*
777 * The bus is ready for the
778 * host to perform another
779 * message transaction. This
780 * mechanism is used for things
781 * like sync/wide negotiation
782 * that require a kernel based
783 * message state engine.
784 */
785 mask PERR_DETECTED 0xb0|SEQINT /*
786 * Either the phase_lock
787 * or inb_next routine has
788 * noticed a parity error.
789 */
790 mask TRACEPOINT 0xd0|SEQINT
791 mask DATA_OVERRUN 0xf0|SEQINT /*
792 * Target attempted to write
793 * beyond the bounds of its
794 * command.
795 */
796
797 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
798 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
799}
800
801/*
802 * Hard Error (p. 3-53)
803 * Reporting of catastrophic errors. You usually cannot recover from
804 * these without a full board reset.
805 */
806register ERROR {
807 address 0x092
808 access_mode RO
809 bit CIOPARERR 0x80 /* Ultra2 only */
810 bit PCIERRSTAT 0x40 /* PCI only */
811 bit MPARERR 0x20 /* PCI only */
812 bit DPARERR 0x10 /* PCI only */
813 bit SQPARERR 0x08
814 bit ILLOPCODE 0x04
815 bit ILLSADDR 0x02
816 bit ILLHADDR 0x01
817}
818
819/*
820 * Clear Interrupt Status (p. 3-52)
821 */
822register CLRINT {
823 address 0x092
824 access_mode WO
825 bit CLRPARERR 0x10 /* PCI only */
826 bit CLRBRKADRINT 0x08
827 bit CLRSCSIINT 0x04
828 bit CLRCMDINT 0x02
829 bit CLRSEQINT 0x01
830}
831
832register DFCNTRL {
833 address 0x093
834 access_mode RW
835 bit PRELOADEN 0x80 /* aic7890 only */
836 bit WIDEODD 0x40
837 bit SCSIEN 0x20
838 bit SDMAEN 0x10
839 bit SDMAENACK 0x10
840 bit HDMAEN 0x08
841 bit HDMAENACK 0x08
842 bit DIRECTION 0x04
843 bit FIFOFLUSH 0x02
844 bit FIFORESET 0x01
845}
846
847register DFSTATUS {
848 address 0x094
849 access_mode RO
850 bit PRELOAD_AVAIL 0x80
851 bit DWORDEMP 0x20
852 bit MREQPEND 0x10
853 bit HDONE 0x08
854 bit DFTHRESH 0x04
855 bit FIFOFULL 0x02
856 bit FIFOEMP 0x01
857}
858
859register DFWADDR {
860 address 0x95
861 access_mode RW
862}
863
864register DFRADDR {
865 address 0x97
866 access_mode RW
867}
868
869register DFDAT {
870 address 0x099
871 access_mode RW
872}
873
874/*
875 * SCB Auto Increment (p. 3-59)
876 * Byte offset into the SCB Array and an optional bit to allow auto
877 * incrementing of the address during download and upload operations
878 */
879register SCBCNT {
880 address 0x09a
881 access_mode RW
882 bit SCBAUTO 0x80
883 mask SCBCNT_MASK 0x1f
884}
885
886/*
887 * Queue In FIFO (p. 3-60)
888 * Input queue for queued SCBs (commands that the seqencer has yet to start)
889 */
890register QINFIFO {
891 address 0x09b
892 access_mode RW
893}
894
895/*
896 * Queue In Count (p. 3-60)
897 * Number of queued SCBs
898 */
899register QINCNT {
900 address 0x09c
901 access_mode RO
902}
903
904/*
905 * Queue Out FIFO (p. 3-61)
906 * Queue of SCBs that have completed and await the host
907 */
908register QOUTFIFO {
909 address 0x09d
910 access_mode WO
911}
912
913register CRCCONTROL1 {
914 address 0x09d
915 access_mode RW
916 bit CRCONSEEN 0x80
917 bit CRCVALCHKEN 0x40
918 bit CRCENDCHKEN 0x20
919 bit CRCREQCHKEN 0x10
920 bit TARGCRCENDEN 0x08
921 bit TARGCRCCNTEN 0x04
922}
923
924
925/*
926 * Queue Out Count (p. 3-61)
927 * Number of queued SCBs in the Out FIFO
928 */
929register QOUTCNT {
930 address 0x09e
931 access_mode RO
932}
933
934register SCSIPHASE {
935 address 0x09e
936 access_mode RO
937 bit STATUS_PHASE 0x20
938 bit COMMAND_PHASE 0x10
939 bit MSG_IN_PHASE 0x08
940 bit MSG_OUT_PHASE 0x04
941 bit DATA_IN_PHASE 0x02
942 bit DATA_OUT_PHASE 0x01
943}
944
945/*
946 * Special Function
947 */
948register SFUNCT {
949 address 0x09f
950 access_mode RW
951 bit ALT_MODE 0x80
952}
953
954/*
955 * SCB Definition (p. 5-4)
956 */
957scb {
958 address 0x0a0
959 SCB_CONTROL {
960 size 1
961 bit TARGET_SCB 0x80
962 bit DISCENB 0x40
963 bit TAG_ENB 0x20
964 bit MK_MESSAGE 0x10
965 bit ULTRAENB 0x08
966 bit DISCONNECTED 0x04
967 mask SCB_TAG_TYPE 0x03
968 }
969 SCB_SCSIID {
970 size 1
971 bit TWIN_CHNLB 0x80
972 mask TWIN_TID 0x70
973 mask TID 0xf0
974 mask OID 0x0f
975 }
976 SCB_LUN {
977 mask LID 0xff
978 size 1
979 }
980 SCB_CDB_LEN {
981 size 1
982 }
983 SCB_CDB_PTR {
984 size 4
985 alias SCB_RESIDUAL_DATACNT
986 alias SCB_CDB_STORE
987 alias SCB_TARGET_INFO
988 }
989 SCB_RESIDUAL_SGPTR {
990 size 4
991 }
992 SCB_SCSI_STATUS {
993 size 1
994 }
995 SCB_CDB_STORE_PAD {
996 size 3
997 }
998 SCB_DATAPTR {
999 size 4
1000 }
1001 SCB_DATACNT {
1002 /*
1003 * The last byte is really the high address bits for
1004 * the data address.
1005 */
1006 size 4
1007 bit SG_LAST_SEG 0x80 /* In the fourth byte */
1008 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
1009 }
1010 SCB_SGPTR {
1011 size 4
1012 bit SG_RESID_VALID 0x04 /* In the first byte */
1013 bit SG_FULL_RESID 0x02 /* In the first byte */
1014 bit SG_LIST_NULL 0x01 /* In the first byte */
1015 }
1016 SCB_TAG {
1017 size 1
1018 }
1019 SCB_SCSIRATE {
1020 size 1
1021 }
1022 SCB_SCSIOFFSET {
1023 size 1
1024 }
1025 SCB_NEXT {
1026 size 1
1027 }
1028 SCB_64_BTT {
1029 size 16
1030 }
1031 SCB_64_SPARE {
1032 size 16
1033 }
1034}
1035
1036const SCB_32BYTE_SIZE 30 /* Cards supporting 32byte scbs */
1037const SCB_64BYTE_SIZE 32 /* Cards supporting 64byte scbs */
1038
1039const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
1040
1041/* --------------------- AHA-2840-only definitions -------------------- */
1042
1043register SEECTL_2840 {
1044 address 0x0c0
1045 access_mode RW
1046 bit CS_2840 0x04
1047 bit CK_2840 0x02
1048 bit DO_2840 0x01
1049}
1050
1051register STATUS_2840 {
1052 address 0x0c1
1053 access_mode RW
1054 bit EEPROM_TF 0x80
1055 mask BIOS_SEL 0x60
1056 mask ADSEL 0x1e
1057 bit DI_2840 0x01
1058}
1059
1060/* --------------------- AIC-7870-only definitions -------------------- */
1061
1062register CCHADDR {
1063 address 0x0E0
1064 size 8
1065}
1066
1067register CCHCNT {
1068 address 0x0E8
1069}
1070
1071register CCSGRAM {
1072 address 0x0E9
1073}
1074
1075register CCSGADDR {
1076 address 0x0EA
1077}
1078
1079register CCSGCTL {
1080 address 0x0EB
1081 bit CCSGDONE 0x80
1082 bit CCSGEN 0x08
1083 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */
1084 bit CCSGRESET 0x01
1085}
1086
1087register CCSCBCNT {
1088 address 0xEF
1089}
1090
1091register CCSCBCTL {
1092 address 0x0EE
1093 bit CCSCBDONE 0x80
1094 bit ARRDONE 0x40 /* SCB Array prefetch done */
1095 bit CCARREN 0x10
1096 bit CCSCBEN 0x08
1097 bit CCSCBDIR 0x04
1098 bit CCSCBRESET 0x01
1099}
1100
1101register CCSCBADDR {
1102 address 0x0ED
1103}
1104
1105register CCSCBRAM {
1106 address 0xEC
1107}
1108
1109/*
1110 * SCB bank address (7895/7896/97 only)
1111 */
1112register SCBBADDR {
1113 address 0x0F0
1114 access_mode RW
1115}
1116
1117register CCSCBPTR {
1118 address 0x0F1
1119}
1120
1121register HNSCB_QOFF {
1122 address 0x0F4
1123}
1124
1125register SNSCB_QOFF {
1126 address 0x0F6
1127}
1128
1129register SDSCB_QOFF {
1130 address 0x0F8
1131}
1132
1133register QOFF_CTLSTA {
1134 address 0x0FA
1135 bit SCB_AVAIL 0x40
1136 bit SNSCB_ROLLOVER 0x20
1137 bit SDSCB_ROLLOVER 0x10
1138 mask SCB_QSIZE 0x07
1139 mask SCB_QSIZE_256 0x06
1140}
1141
1142register DFF_THRSH {
1143 address 0x0FB
1144 mask WR_DFTHRSH 0x70
1145 mask RD_DFTHRSH 0x07
1146 mask RD_DFTHRSH_MIN 0x00
1147 mask RD_DFTHRSH_25 0x01
1148 mask RD_DFTHRSH_50 0x02
1149 mask RD_DFTHRSH_63 0x03
1150 mask RD_DFTHRSH_75 0x04
1151 mask RD_DFTHRSH_85 0x05
1152 mask RD_DFTHRSH_90 0x06
1153 mask RD_DFTHRSH_MAX 0x07
1154 mask WR_DFTHRSH_MIN 0x00
1155 mask WR_DFTHRSH_25 0x10
1156 mask WR_DFTHRSH_50 0x20
1157 mask WR_DFTHRSH_63 0x30
1158 mask WR_DFTHRSH_75 0x40
1159 mask WR_DFTHRSH_85 0x50
1160 mask WR_DFTHRSH_90 0x60
1161 mask WR_DFTHRSH_MAX 0x70
1162}
1163
1164register SG_CACHE_PRE {
1165 access_mode WO
1166 address 0x0fc
1167 mask SG_ADDR_MASK 0xf8
1168 bit ODD_SEG 0x04
1169 bit LAST_SEG 0x02
1170 bit LAST_SEG_DONE 0x01
1171}
1172
1173register SG_CACHE_SHADOW {
1174 access_mode RO
1175 address 0x0fc
1176 mask SG_ADDR_MASK 0xf8
1177 bit ODD_SEG 0x04
1178 bit LAST_SEG 0x02
1179 bit LAST_SEG_DONE 0x01
1180}
1181/* ---------------------- Scratch RAM Offsets ------------------------- */
1182/* These offsets are either to values that are initialized by the board's
1183 * BIOS or are specified by the sequencer code.
1184 *
1185 * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1186 * device information, 32-33 and 5a-5f as well. As it turns out, the
1187 * BIOS trashes 20-2f, writing the synchronous negotiation results
1188 * on top of the BIOS values, so we re-use those for our per-target
1189 * scratchspace (actually a value that can be copied directly into
1190 * SCSIRATE). The kernel driver will enable synchronous negotiation
1191 * for all targets that have a value other than 0 in the lower four
1192 * bits of the target scratch space. This should work regardless of
1193 * whether the bios has been installed.
1194 */
1195
1196scratch_ram {
1197 address 0x020
1198
1199 /*
1200 * 1 byte per target starting at this address for configuration values
1201 */
1202 CMDSIZE_TABLE {
1203 alias TARG_SCSIRATE
1204 size 8
1205 }
1206 BUSY_TARGETS {
1207 size 16
1208 }
1209 /*
1210 * Bit vector of targets that have ULTRA enabled.
1211 */
1212 ULTRA_ENB {
1213 size 2
1214 }
1215 /*
1216 * Bit vector of targets that have disconnection disabled.
1217 */
1218 DISC_DSB {
1219 size 2
1220 }
1221 /*
1222 * Single byte buffer used to designate the type or message
1223 * to send to a target.
1224 */
1225 MSG_OUT {
1226 size 1
1227 }
1228 /* Parameters for DMA Logic */
1229 DMAPARAMS {
1230 size 1
1231 bit PRELOADEN 0x80
1232 bit WIDEODD 0x40
1233 bit SCSIEN 0x20
1234 bit SDMAEN 0x10
1235 bit SDMAENACK 0x10
1236 bit HDMAEN 0x08
1237 bit HDMAENACK 0x08
1238 bit DIRECTION 0x04
1239 bit FIFOFLUSH 0x02
1240 bit FIFORESET 0x01
1241 }
1242 SEQ_FLAGS {
1243 size 1
1244 bit IDENTIFY_SEEN 0x80
1245 bit SCBPTR_VALID 0x40
1246 bit TARGET_CMD_IS_TAGGED 0x40
1247 bit DPHASE 0x20
1248 /* Target flags */
1249 bit TARG_CMD_PENDING 0x10
1250 bit CMDPHASE_PENDING 0x08
1251 bit DPHASE_PENDING 0x04
1252 bit SPHASE_PENDING 0x02
1253 bit NO_DISCONNECT 0x01
1254 }
1255 /*
1256 * Temporary storage for the
1257 * target/channel/lun of a
1258 * reconnecting target
1259 */
1260 SAVED_SCSIID {
1261 size 1
1262 }
1263 SAVED_LUN {
1264 size 1
1265 }
1266 /*
1267 * The last bus phase as seen by the sequencer.
1268 */
1269 LASTPHASE {
1270 size 1
1271 bit CDI 0x80
1272 bit IOI 0x40
1273 bit MSGI 0x20
1274 mask PHASE_MASK CDI|IOI|MSGI
1275 mask P_DATAOUT 0x00
1276 mask P_DATAIN IOI
1277 mask P_COMMAND CDI
1278 mask P_MESGOUT CDI|MSGI
1279 mask P_STATUS CDI|IOI
1280 mask P_MESGIN CDI|IOI|MSGI
1281 mask P_BUSFREE 0x01
1282 }
1283 /*
1284 * head of list of SCBs awaiting
1285 * selection
1286 */
1287 WAITING_SCBH {
1288 size 1
1289 }
1290 /*
1291 * head of list of SCBs that are
1292 * disconnected. Used for SCB
1293 * paging.
1294 */
1295 DISCONNECTED_SCBH {
1296 size 1
1297 }
1298 /*
1299 * head of list of SCBs that are
1300 * not in use. Used for SCB paging.
1301 */
1302 FREE_SCBH {
1303 size 1
1304 }
1305 /*
1306 * Address of the hardware scb array in the host.
1307 */
1308 HSCB_ADDR {
1309 size 4
1310 }
1311 /*
1312 * Base address of our shared data with the kernel driver in host
1313 * memory. This includes the qinfifo, qoutfifo, and target mode
1314 * incoming command queue.
1315 */
1316 SHARED_DATA_ADDR {
1317 size 4
1318 }
1319 KERNEL_QINPOS {
1320 size 1
1321 }
1322 QINPOS {
1323 size 1
1324 }
1325 QOUTPOS {
1326 size 1
1327 }
1328 /*
1329 * Kernel and sequencer offsets into the queue of
1330 * incoming target mode command descriptors. The
1331 * queue is full when the KERNEL_TQINPOS == TQINPOS.
1332 */
1333 KERNEL_TQINPOS {
1334 size 1
1335 }
1336 TQINPOS {
1337 size 1
1338 }
1339 ARG_1 {
1340 size 1
1341 mask SEND_MSG 0x80
1342 mask SEND_SENSE 0x40
1343 mask SEND_REJ 0x20
1344 mask MSGOUT_PHASEMIS 0x10
1345 mask EXIT_MSG_LOOP 0x08
1346 mask CONT_MSG_LOOP 0x04
1347 mask CONT_TARG_SESSION 0x02
1348 alias RETURN_1
1349 }
1350 ARG_2 {
1351 size 1
1352 alias RETURN_2
1353 }
1354
1355 /*
1356 * Snapshot of MSG_OUT taken after each message is sent.
1357 */
1358 LAST_MSG {
1359 size 1
1360 }
1361
1362 /*
1363 * Interrupt kernel for a message to this target on
1364 * the next transaction. This is usually used for
1365 * negotiation requests.
1366 */
1367 TARGET_MSG_REQUEST {
1368 size 2
1369 }
1370
1371 /*
1372 * Sequences the kernel driver has okayed for us. This allows
1373 * the driver to do things like prevent initiator or target
1374 * operations.
1375 */
1376 SCSISEQ_TEMPLATE {
1377 size 1
1378 bit ENSELO 0x40
1379 bit ENSELI 0x20
1380 bit ENRSELI 0x10
1381 bit ENAUTOATNO 0x08
1382 bit ENAUTOATNI 0x04
1383 bit ENAUTOATNP 0x02
1384 }
1385
1386 /*
1387 * Track whether the transfer byte count for
1388 * the current data phase is odd.
1389 */
1390 DATA_COUNT_ODD {
1391 size 1
1392 }
1393
1394 /*
1395 * The initiator specified tag for this target mode transaction.
1396 */
1397 INITIATOR_TAG {
1398 size 1
1399 }
1400
1401 /*
1402 * These are reserved registers in the card's scratch ram. Some of
1403 * the values are specified in the AHA2742 technical reference manual
1404 * and are initialized by the BIOS at boot time.
1405 */
1406 SCSICONF {
1407 address 0x05a
1408 size 1
1409 bit TERM_ENB 0x80
1410 bit RESET_SCSI 0x40
1411 bit ENSPCHK 0x20
1412 mask HSCSIID 0x07 /* our SCSI ID */
1413 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
1414 }
1415 HOSTCONF {
1416 address 0x05d
1417 size 1
1418 }
1419 HA_274_BIOSCTRL {
1420 address 0x05f
1421 size 1
1422 mask BIOSMODE 0x30
1423 mask BIOSDISABLED 0x30
1424 bit CHANNEL_B_PRIMARY 0x08
1425 }
1426 /*
1427 * Per target SCSI offset values for Ultra2 controllers.
1428 */
1429 TARG_OFFSET {
1430 address 0x070
1431 size 16
1432 }
1433}
1434
1435const TID_SHIFT 4
1436const SCB_LIST_NULL 0xff
1437const TARGET_CMD_CMPLT 0xfe
1438
1439const CCSGADDR_MAX 0x80
1440const CCSGRAM_MAXSEGS 16
1441
1442/* WDTR Message values */
1443const BUS_8_BIT 0x00
1444const BUS_16_BIT 0x01
1445const BUS_32_BIT 0x02
1446
1447/* Offset maximums */
1448const MAX_OFFSET_8BIT 0x0f
1449const MAX_OFFSET_16BIT 0x08
1450const MAX_OFFSET_ULTRA2 0x7f
1451const HOST_MSG 0xff
1452
1453/* Target mode command processing constants */
1454const CMD_GROUP_CODE_SHIFT 0x05
1455
1456const STATUS_BUSY 0x08
1457const STATUS_QUEUE_FULL 0x28
1458const SCB_TARGET_PHASES 0
1459const SCB_TARGET_DATA_DIR 1
1460const SCB_TARGET_STATUS 2
1461const SCB_INITIATOR_TAG 3
1462const TARGET_DATA_IN 1
1463
1464/*
1465 * Downloaded (kernel inserted) constants
1466 */
1467/* Offsets into the SCBID array where different data is stored */
1468const QOUTFIFO_OFFSET download
1469const QINFIFO_OFFSET download