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cvmx-core.h (210286) cvmx-core.h (215990)
1/***********************license start***************
1/***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
3 * reserved.
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
3 * reserved.
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10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
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18 * * Neither the name of Cavium Networks nor the names of
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13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
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19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
21 * permission.
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23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
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27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
37 ***********************license end**************************************/
38
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40
41
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43
38 ***********************license end**************************************/
39
40
41
42
43
44
45
44/**
45 * @file
46 *
47 * Module to support operations on core such as TLB config, etc.
48 *
46/**
47 * @file
48 *
49 * Module to support operations on core such as TLB config, etc.
50 *
49 * <hr>$Revision: 41586 $<hr>
51 * <hr>$Revision: 49448 $<hr>
50 *
51 */
52
53
54#ifndef __CVMX_CORE_H__
55#define __CVMX_CORE_H__
56
57#ifdef __cplusplus

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112 CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */
113 CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */
114 CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */
115 CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */
116 CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */
117 CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
118 CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
119 CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */
52 *
53 */
54
55
56#ifndef __CVMX_CORE_H__
57#define __CVMX_CORE_H__
58
59#ifdef __cplusplus

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114 CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */
115 CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */
116 CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */
117 CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */
118 CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */
119 CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
120 CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */
121 CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */
122 /* Added in CN63XX */
123 CVMX_CORE_PERF_ERETMIS = 64, /**< D/eret mispredicts */
124 CVMX_CORE_PERF_LIKMIS = 65, /**< Branch likely mispredicts */
125 CVMX_CORE_PERF_HAZTR = 66, /**< Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers */
120 CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */
121} cvmx_core_perf_t;
122
123/**
124 * Bit description of the COP0 counter control register
125 */
126typedef union
127{
128 uint32_t u32;
129 struct
130 {
126 CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */
127} cvmx_core_perf_t;
128
129/**
130 * Bit description of the COP0 counter control register
131 */
132typedef union
133{
134 uint32_t u32;
135 struct
136 {
137#if __BYTE_ORDER == __BIG_ENDIAN
131 uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
132 uint32_t w : 1; /**< Set to 1 indicating coutners are 64 bit */
138 uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */
139 uint32_t w : 1; /**< Set to 1 indicating coutners are 64 bit */
133 uint32_t reserved_11_29 :19;
134 cvmx_core_perf_t event : 6; /**< Selects the event to be counted by the corresponding Counter Register */
140 uint32_t reserved_11_29 :15;
141 cvmx_core_perf_t event :10; /**< Selects the event to be counted by the corresponding Counter Register */
135 uint32_t ie : 1; /**< Count in interrupt context */
136 uint32_t u : 1; /**< Count in user mode */
137 uint32_t s : 1; /**< Count in supervisor mode */
138 uint32_t k : 1; /**< Count in kernel mode */
139 uint32_t ex : 1; /**< Count in exception context */
142 uint32_t ie : 1; /**< Count in interrupt context */
143 uint32_t u : 1; /**< Count in user mode */
144 uint32_t s : 1; /**< Count in supervisor mode */
145 uint32_t k : 1; /**< Count in kernel mode */
146 uint32_t ex : 1; /**< Count in exception context */
147#else
148 uint32_t ex : 1;
149 uint32_t k : 1;
150 uint32_t s : 1;
151 uint32_t u : 1;
152 uint32_t ie : 1;
153 uint32_t event :10;
154 uint32_t reserved_11_29 :15;
155 uint32_t w : 1;
156 uint32_t m : 1;
157#endif
140 } s;
141} cvmx_core_perf_control_t;
142
143typedef enum {
144 CVMX_TLB_PAGEMASK_4K = 0x3 << 11,
145 CVMX_TLB_PAGEMASK_16K = 0xF << 11,
146 CVMX_TLB_PAGEMASK_64K = 0x3F << 11,
147 CVMX_TLB_PAGEMASK_256K = 0xFF << 11,

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154
155
156int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask);
157
158
159int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
160int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
161
158 } s;
159} cvmx_core_perf_control_t;
160
161typedef enum {
162 CVMX_TLB_PAGEMASK_4K = 0x3 << 11,
163 CVMX_TLB_PAGEMASK_16K = 0xF << 11,
164 CVMX_TLB_PAGEMASK_64K = 0x3F << 11,
165 CVMX_TLB_PAGEMASK_256K = 0xFF << 11,

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172
173
174int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask);
175
176
177int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
178int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask);
179
180/**
181 * Return number of TLB entries.
182 */
183int cvmx_core_get_tlb_entries(void);
162#ifdef __cplusplus
163}
164#endif
165
166#endif /* __CVMX_CORE_H__ */
184#ifdef __cplusplus
185}
186#endif
187
188#endif /* __CVMX_CORE_H__ */