cvmx-core.c (210286) | cvmx-core.c (215990) |
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1/***********************license start*************** | 1/***********************license start*************** |
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. | 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. |
4 * 5 * | 4 * 5 * |
6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: | 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: |
9 * | 9 * |
10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. | 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. |
12 * | 12 * |
13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * | 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. |
37 ***********************license end**************************************/ 38 39 40 41 42 43 | 38 ***********************license end**************************************/ 39 40 41 42 43 44 |
45 |
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44/** 45 * @file 46 * 47 * Module to support operations on core such as TLB config, etc. 48 * | 46/** 47 * @file 48 * 49 * Module to support operations on core such as TLB config, etc. 50 * |
49 * <hr>$Revision: 41586 $<hr> | 51 * <hr>$Revision: 49862 $<hr> |
50 * 51 */ 52 | 52 * 53 */ 54 |
55#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 56#include <linux/module.h> 57#include <asm/octeon/cvmx.h> 58#include <asm/octeon/cvmx-core.h> 59#else |
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53#include "cvmx-config.h" 54#include "cvmx.h" 55#include "cvmx-core.h" | 60#include "cvmx-config.h" 61#include "cvmx.h" 62#include "cvmx-core.h" |
63#endif |
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56 57 58/** 59 * Adds a wired TLB entry, and returns the index of the entry added. 60 * Parameters are written to TLB registers without further processing. 61 * 62 * @param hi HI register value 63 * @param lo0 lo0 register value 64 * @param lo1 lo1 register value 65 * @param page_mask pagemask register value 66 * | 64 65 66/** 67 * Adds a wired TLB entry, and returns the index of the entry added. 68 * Parameters are written to TLB registers without further processing. 69 * 70 * @param hi HI register value 71 * @param lo0 lo0 register value 72 * @param lo1 lo1 register value 73 * @param page_mask pagemask register value 74 * |
67 * @return Success: TLB index used (0-31) or (0-63) for OCTEON Plus 68 * Failure: -1 | 75 * @return Success: TLB index used (0-31 Octeon, 0-63 Octeon+, or 0-127 76 * Octeon2). Failure: -1 |
69 */ 70int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask) 71{ 72 uint32_t index; | 77 */ 78int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask) 79{ 80 uint32_t index; |
73 uint32_t index_limit = 31; | |
74 | 81 |
75 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) 76 { 77 index_limit=63; 78 } 79 | |
80 CVMX_MF_TLB_WIRED(index); | 82 CVMX_MF_TLB_WIRED(index); |
81 if (index >= index_limit) | 83 if (index >= (unsigned int)cvmx_core_get_tlb_entries()) |
82 { 83 return(-1); 84 } 85 CVMX_MT_ENTRY_HIGH(hi); 86 CVMX_MT_ENTRY_LO_0(lo0); 87 CVMX_MT_ENTRY_LO_1(lo1); 88 CVMX_MT_PAGEMASK(page_mask); 89 CVMX_MT_TLB_INDEX(index); --- 50 unchanged lines hidden (view full) --- 140 * Failure: -1 141 */ 142int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask) 143{ 144 145 return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask)); 146 147} | 84 { 85 return(-1); 86 } 87 CVMX_MT_ENTRY_HIGH(hi); 88 CVMX_MT_ENTRY_LO_0(lo0); 89 CVMX_MT_ENTRY_LO_1(lo1); 90 CVMX_MT_PAGEMASK(page_mask); 91 CVMX_MT_TLB_INDEX(index); --- 50 unchanged lines hidden (view full) --- 142 * Failure: -1 143 */ 144int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask) 145{ 146 147 return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask)); 148 149} |
150 151/** 152 * Return number of TLB entries. 153 */ 154int cvmx_core_get_tlb_entries(void) 155{ 156 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) 157 return 32; 158 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) 159 return 64; 160 else 161 return 128; 162} |
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