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cvmx-address.h (210286) cvmx-address.h (215990)
1/***********************license start***************
1/***********************license start***************
2 * Copyright (c) 2003-2009 Cavium Networks (support@cavium.com). All rights
3 * reserved.
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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14 * copyright notice, this list of conditions and the following
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16 * with the distribution.
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19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
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27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
37 ***********************license end**************************************/
38
38 ***********************license end**************************************/
39
40
39/**
40 * @file
41 * Typedefs and defines for working with Octeon physical addresses.
42 *
43 * <hr>$Revision: 38306 $<hr>
44*/
45#ifndef __CVMX_ADDRESS_H__
46#define __CVMX_ADDRESS_H__

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58
59typedef enum {
60 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
61 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
62 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
63 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
64} cvmx_mips_xkseg_space_t;
65
41/**
42 * @file
43 * Typedefs and defines for working with Octeon physical addresses.
44 *
45 * <hr>$Revision: 38306 $<hr>
46*/
47#ifndef __CVMX_ADDRESS_H__
48#define __CVMX_ADDRESS_H__

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60
61typedef enum {
62 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
63 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
64 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
65 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
66} cvmx_mips_xkseg_space_t;
67
66// decodes <14:13> of a kseg3 window address
68 /* decodes <14:13> of a kseg3 window address */
67typedef enum {
68 CVMX_ADD_WIN_SCR = 0L,
69typedef enum {
70 CVMX_ADD_WIN_SCR = 0L,
69 CVMX_ADD_WIN_DMA = 1L, // see cvmx_add_win_dma_dec_t for further decode
71 CVMX_ADD_WIN_DMA = 1L, /* see cvmx_add_win_dma_dec_t for further decode */
70 CVMX_ADD_WIN_UNUSED = 2L,
71 CVMX_ADD_WIN_UNUSED2 = 3L
72} cvmx_add_win_dec_t;
73
72 CVMX_ADD_WIN_UNUSED = 2L,
73 CVMX_ADD_WIN_UNUSED2 = 3L
74} cvmx_add_win_dec_t;
75
74// decode within DMA space
76 /* decode within DMA space */
75typedef enum {
77typedef enum {
76 CVMX_ADD_WIN_DMA_ADD = 0L, // add store data to the write buffer entry, allocating it if necessary
77 CVMX_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM
78 // store data must be normal DRAM memory space address in this case
79 CVMX_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command
80 // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents
81 CVMX_ADD_WIN_DMA_SENDIO = 3L, // send out the write buffer entry as an IO write
82 // store data must be normal IO space address in this case
83 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus
84 // no write buffer data needed/used
78 CVMX_ADD_WIN_DMA_ADD = 0L, /* add store data to the write buffer entry, allocating it if necessary */
79 CVMX_ADD_WIN_DMA_SENDMEM = 1L, /* send out the write buffer entry to DRAM */
80 /* store data must be normal DRAM memory space address in this case */
81 CVMX_ADD_WIN_DMA_SENDDMA = 2L, /* send out the write buffer entry as an IOBDMA command */
82 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
83 CVMX_ADD_WIN_DMA_SENDIO = 3L, /* send out the write buffer entry as an IO write */
84 /* store data must be normal IO space address in this case */
85 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, /* send out a single-tick command on the NCB bus */
86 /* no write buffer data needed/used */
85} cvmx_add_win_dma_dec_t;
86
87} cvmx_add_win_dma_dec_t;
88
87
88
89/**
90 * Physical Address Decode
91 *
92 * Octeon-I HW never interprets this X (<39:36> reserved
93 * for future expansion), software should set to 0.
94 *
95 * - 0x0 XXX0 0000 0000 to DRAM Cached
96 * - 0x0 XXX0 0FFF FFFF

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111 */
112typedef union {
113
114 uint64_t u64;
115
116 struct {
117 cvmx_mips_space_t R : 2;
118 uint64_t offset :62;
89/**
90 * Physical Address Decode
91 *
92 * Octeon-I HW never interprets this X (<39:36> reserved
93 * for future expansion), software should set to 0.
94 *
95 * - 0x0 XXX0 0000 0000 to DRAM Cached
96 * - 0x0 XXX0 0FFF FFFF

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111 */
112typedef union {
113
114 uint64_t u64;
115
116 struct {
117 cvmx_mips_space_t R : 2;
118 uint64_t offset :62;
119 } sva; // mapped or unmapped virtual address
119 } sva; /* mapped or unmapped virtual address */
120
121 struct {
122 uint64_t zeroes :33;
123 uint64_t offset :31;
120
121 struct {
122 uint64_t zeroes :33;
123 uint64_t offset :31;
124 } suseg; // mapped USEG virtual addresses (typically)
124 } suseg; /* mapped USEG virtual addresses (typically) */
125
126 struct {
127 uint64_t ones :33;
128 cvmx_mips_xkseg_space_t sp : 2;
129 uint64_t offset :29;
125
126 struct {
127 uint64_t ones :33;
128 cvmx_mips_xkseg_space_t sp : 2;
129 uint64_t offset :29;
130 } sxkseg; // mapped or unmapped virtual address
130 } sxkseg; /* mapped or unmapped virtual address */
131
132 struct {
131
132 struct {
133 cvmx_mips_space_t R : 2; // CVMX_MIPS_SPACE_XKPHYS in this case
134 uint64_t cca : 3; // ignored by octeon
133 cvmx_mips_space_t R : 2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
134 uint64_t cca : 3; /* ignored by octeon */
135 uint64_t mbz :10;
135 uint64_t mbz :10;
136 uint64_t pa :49; // physical address
137 } sxkphys; // physical address accessed through xkphys unmapped virtual address
136 uint64_t pa :49; /* physical address */
137 } sxkphys; /* physical address accessed through xkphys unmapped virtual address */
138
139 struct {
140 uint64_t mbz :15;
138
139 struct {
140 uint64_t mbz :15;
141 uint64_t is_io : 1; // if set, the address is uncached and resides on MCB bus
142 uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID
143 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I
141 uint64_t is_io : 1; /* if set, the address is uncached and resides on MCB bus */
142 uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */
143 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
144 uint64_t offset :36;
144 uint64_t offset :36;
145 } sphys; // physical address
145 } sphys; /* physical address */
146
147 struct {
146
147 struct {
148 uint64_t zeroes :24; // techically, <47:40> are dont-cares
149 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I
148 uint64_t zeroes :24; /* techically, <47:40> are dont-cares */
149 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
150 uint64_t offset :36;
150 uint64_t offset :36;
151 } smem; // physical mem address
151 } smem; /* physical mem address */
152
153 struct {
154 uint64_t mem_region :2;
155 uint64_t mbz :13;
152
153 struct {
154 uint64_t mem_region :2;
155 uint64_t mbz :13;
156 uint64_t is_io : 1; // 1 in this case
157 uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID
158 uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I
156 uint64_t is_io : 1; /* 1 in this case */
157 uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */
158 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
159 uint64_t offset :36;
159 uint64_t offset :36;
160 } sio; // physical IO address
160 } sio; /* physical IO address */
161
162 struct {
163 uint64_t ones : 49;
161
162 struct {
163 uint64_t ones : 49;
164 cvmx_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_SCR (0) in this case
164 cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_SCR (0) in this case */
165 uint64_t addr : 13;
165 uint64_t addr : 13;
166 } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3
166 } sscr; /* scratchpad virtual address - accessed through a window at the end of kseg3 */
167
167
168 // there should only be stores to IOBDMA space, no loads
168 /* there should only be stores to IOBDMA space, no loads */
169 struct {
170 uint64_t ones : 49;
169 struct {
170 uint64_t ones : 49;
171 cvmx_add_win_dec_t csrdec : 2; // CVMX_ADD_WIN_DMA (1) in this case
171 cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_DMA (1) in this case */
172 uint64_t unused2: 3;
173 cvmx_add_win_dma_dec_t type : 3;
174 uint64_t addr : 7;
172 uint64_t unused2: 3;
173 cvmx_add_win_dma_dec_t type : 3;
174 uint64_t addr : 7;
175 } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3
175 } sdma; /* IOBDMA virtual address - accessed through a window at the end of kseg3 */
176
177 struct {
178 uint64_t didspace : 24;
179 uint64_t unused : 40;
180 } sfilldidspace;
181
182} cvmx_addr_t;
183

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198#ifndef CVMX_ADD_IO_SEG
199#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
200#endif
201#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
202#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
203#define CVMX_FULL_DID(did,subdid) (((did) << 3) | (subdid))
204
205
176
177 struct {
178 uint64_t didspace : 24;
179 uint64_t unused : 40;
180 } sfilldidspace;
181
182} cvmx_addr_t;
183

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198#ifndef CVMX_ADD_IO_SEG
199#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
200#endif
201#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
202#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
203#define CVMX_FULL_DID(did,subdid) (((did) << 3) | (subdid))
204
205
206// from include/ncb_rsl_id.v
207#define CVMX_OCT_DID_MIS 0ULL // misc stuff
206 /* from include/ncb_rsl_id.v */
207#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
208#define CVMX_OCT_DID_GMX0 1ULL
209#define CVMX_OCT_DID_GMX1 2ULL
210#define CVMX_OCT_DID_PCI 3ULL
211#define CVMX_OCT_DID_KEY 4ULL
212#define CVMX_OCT_DID_FPA 5ULL
213#define CVMX_OCT_DID_DFA 6ULL
214#define CVMX_OCT_DID_ZIP 7ULL
215#define CVMX_OCT_DID_RNG 8ULL
216#define CVMX_OCT_DID_IPD 9ULL
217#define CVMX_OCT_DID_PKT 10ULL
218#define CVMX_OCT_DID_TIM 11ULL
219#define CVMX_OCT_DID_TAG 12ULL
208#define CVMX_OCT_DID_GMX0 1ULL
209#define CVMX_OCT_DID_GMX1 2ULL
210#define CVMX_OCT_DID_PCI 3ULL
211#define CVMX_OCT_DID_KEY 4ULL
212#define CVMX_OCT_DID_FPA 5ULL
213#define CVMX_OCT_DID_DFA 6ULL
214#define CVMX_OCT_DID_ZIP 7ULL
215#define CVMX_OCT_DID_RNG 8ULL
216#define CVMX_OCT_DID_IPD 9ULL
217#define CVMX_OCT_DID_PKT 10ULL
218#define CVMX_OCT_DID_TIM 11ULL
219#define CVMX_OCT_DID_TAG 12ULL
220// the rest are not on the IO bus
220 /* the rest are not on the IO bus */
221#define CVMX_OCT_DID_L2C 16ULL
222#define CVMX_OCT_DID_LMC 17ULL
223#define CVMX_OCT_DID_SPX0 18ULL
224#define CVMX_OCT_DID_SPX1 19ULL
225#define CVMX_OCT_DID_PIP 20ULL
226#define CVMX_OCT_DID_ASX0 22ULL
227#define CVMX_OCT_DID_ASX1 23ULL
228#define CVMX_OCT_DID_IOB 30ULL

--- 25 unchanged lines hidden --- 		221#define CVMX_OCT_DID_L2C 16ULL
222#define CVMX_OCT_DID_LMC 17ULL
223#define CVMX_OCT_DID_SPX0 18ULL
224#define CVMX_OCT_DID_SPX1 19ULL
225#define CVMX_OCT_DID_PIP 20ULL
226#define CVMX_OCT_DID_ASX0 22ULL
227#define CVMX_OCT_DID_ASX1 23ULL
228#define CVMX_OCT_DID_IOB 30ULL

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