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cvmx-access-native.h (210311) cvmx-access-native.h (215990)
1/***********************license start***************
1/***********************license start***************
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29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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38 ***********************license end**************************************/
39
40
39/**
40 * @file
41 * Functions for accessing memory and CSRs on Octeon when we are compiling
42 * natively.
43 *
44 * <hr>$Revision: 38306 $<hr>
45*/
46#ifndef __CVMX_ACCESS_NATIVE_H__

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76 * @return Hardware physical address
77 */
78static inline uint64_t cvmx_ptr_to_phys(void *ptr)
79{
80 if (CVMX_ENABLE_PARAMETER_CHECKING)
81 cvmx_warn_if(ptr==NULL, "cvmx_ptr_to_phys() passed a NULL pointer\n");
82
83#ifdef CVMX_BUILD_FOR_UBOOT
41/**
42 * @file
43 * Functions for accessing memory and CSRs on Octeon when we are compiling
44 * natively.
45 *
46 * <hr>$Revision: 38306 $<hr>
47*/
48#ifndef __CVMX_ACCESS_NATIVE_H__

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78 * @return Hardware physical address
79 */
80static inline uint64_t cvmx_ptr_to_phys(void *ptr)
81{
82 if (CVMX_ENABLE_PARAMETER_CHECKING)
83 cvmx_warn_if(ptr==NULL, "cvmx_ptr_to_phys() passed a NULL pointer\n");
84
85#ifdef CVMX_BUILD_FOR_UBOOT
84 /* U-boot is a special case, as it is running in error level, which disables the TLB completely.
85 ** U-boot may use kseg0 addresses, or may directly use physical addresses already */
86 return(CAST64(ptr) & 0x7FFFFFFF);
86 uint64_t uboot_tlb_ptr_to_phys(void *ptr);
87
88 if (((uint32_t)ptr) < 0x80000000)
89 {
90 /* Handle useg (unmapped due to ERL) here*/
91 return(CAST64(ptr) & 0x7FFFFFFF);
92 }
93 else if (((uint32_t)ptr) < 0xC0000000)
94 {
95 /* Here we handle KSEG0/KSEG1 _pointers_. We know we are dealing
96 ** with 32 bit only values, so we treat them that way. Note that
97 ** a cvmx_phys_to_ptr(cvmx_ptr_to_phys(X)) will not return X in this case,
98 ** but the physical address of the KSEG0/KSEG1 address. */
99 return(CAST64(ptr) & 0x1FFFFFFF);
100 }
101 else
102 return(uboot_tlb_ptr_to_phys(ptr)); /* Should not get get here in !TLB case */
103
87#endif
88
89#ifdef __linux__
90 if (sizeof(void*) == 8)
91 {
92 /* We're running in 64 bit mode. Normally this means that we can use
93 40 bits of address space (the hardware limit). Unfortunately there
94 is one case were we need to limit this to 30 bits, sign extended

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161 * @return Pointer to memory
162 */
163static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
164{
165 if (CVMX_ENABLE_PARAMETER_CHECKING)
166 cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
167
168#ifdef CVMX_BUILD_FOR_UBOOT
104#endif
105
106#ifdef __linux__
107 if (sizeof(void*) == 8)
108 {
109 /* We're running in 64 bit mode. Normally this means that we can use
110 40 bits of address space (the hardware limit). Unfortunately there
111 is one case were we need to limit this to 30 bits, sign extended

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178 * @return Pointer to memory
179 */
180static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
181{
182 if (CVMX_ENABLE_PARAMETER_CHECKING)
183 cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
184
185#ifdef CVMX_BUILD_FOR_UBOOT
169 /* U-boot is a special case, as it is running in error level, which disables the TLB completely.
170 ** U-boot may use kseg0 addresses, or may directly use physical addresses already */
186#if !CONFIG_OCTEON_UBOOT_TLB
171 if (physical_address >= 0x80000000)
172 return NULL;
173 else
174 return CASTPTR(void, (physical_address & 0x7FFFFFFF));
175#endif
176
187 if (physical_address >= 0x80000000)
188 return NULL;
189 else
190 return CASTPTR(void, (physical_address & 0x7FFFFFFF));
191#endif
192
193 /* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
194 ** which can have a physical address above the 32 bit address space. 1-1 mappings are used
195 ** to allow the low 2 GBytes to be accessed as in error level.
196 **
197 ** NOTE: This conversion can cause problems in u-boot, as users may want to enter addresses
198 ** like 0xBFC00000 (kseg1 boot bus address), which is a valid 64 bit physical address,
199 ** but is likely intended to be a boot bus address. */
200
201 if (physical_address < 0x80000000)
202 {
203 /* Handle useg here. ERL is set, so useg is unmapped. This is the only physical
204 ** address range that is directly addressable by u-boot. */
205 return CASTPTR(void, physical_address);
206 }
207 else
208 {
209 DECLARE_GLOBAL_DATA_PTR;
210 extern char uboot_start;
211 /* Above 0x80000000 we can only support one case - a physical address
212 ** that is mapped for u-boot code/data. We check against the u-boot mem range,
213 ** and return NULL if it is out of this range.
214 */
215 if (physical_address >= gd->bd->bi_uboot_ram_addr
216 && physical_address < gd->bd->bi_uboot_ram_addr + gd->bd->bi_uboot_ram_used_size)
217 {
218 return ((char *)&uboot_start + (physical_address - gd->bd->bi_uboot_ram_addr));
219 }
220 else
221 return(NULL);
222 }
223
224 if (physical_address >= 0x80000000)
225 return NULL;
226 else
227#endif
228
177#ifdef __linux__
178 if (sizeof(void*) == 8)
179 {
180 /* Just set the top bit, avoiding any TLB uglyness */
181 return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
182 }
183 else
184 {

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194 }
195#elif defined(_WRS_KERNEL)
196 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
197#elif defined(VXWORKS_USER_MAPPINGS)
198 /* This mapping mode is used in vxWorks 5.5 to support 2GB of ram. The
199 2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
200 if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
201 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
229#ifdef __linux__
230 if (sizeof(void*) == 8)
231 {
232 /* Just set the top bit, avoiding any TLB uglyness */
233 return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
234 }
235 else
236 {

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246 }
247#elif defined(_WRS_KERNEL)
248 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
249#elif defined(VXWORKS_USER_MAPPINGS)
250 /* This mapping mode is used in vxWorks 5.5 to support 2GB of ram. The
251 2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
252 if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
253 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
202 else if ((physical_address >= 0x410000000ull) && (physical_address < 0x420000000ull))
254 else if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && (physical_address >= 0x410000000ull) &&
255 (physical_address < 0x420000000ull))
203 return CASTPTR(void, physical_address - 0x400000000ull);
204 else
205 return CASTPTR(void, physical_address);
206#elif defined(__FreeBSD__) && defined(_KERNEL)
207#if defined(__mips_n64)
208 return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
209#else
210 if (physical_address < 0x20000000)

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459
460static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
461{
462 cvmx_write64_uint64(csr_addr, val);
463
464 /* Perform an immediate read after every write to an RSL register to force
465 the write to complete. It doesn't matter what RSL read we do, so we
466 choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
256 return CASTPTR(void, physical_address - 0x400000000ull);
257 else
258 return CASTPTR(void, physical_address);
259#elif defined(__FreeBSD__) && defined(_KERNEL)
260#if defined(__mips_n64)
261 return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
262#else
263 if (physical_address < 0x20000000)

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512
513static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
514{
515 cvmx_write64_uint64(csr_addr, val);
516
517 /* Perform an immediate read after every write to an RSL register to force
518 the write to complete. It doesn't matter what RSL read we do, so we
519 choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
467 if ((csr_addr >> 40) == (0x800118))
520 if (((csr_addr >> 40) & 0x7ffff) == (0x118))
468 cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT);
469}
470
471static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
472{
473 cvmx_write64_uint64(io_addr, val);
474}
475

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498 addr.u64 = csr_addr;
499 addr.s.scraddr = scraddr >> 3;
500 addr.s.len = 1;
501 cvmx_send_single(addr.u64);
502}
503
504
505/**
521 cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT);
522}
523
524static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
525{
526 cvmx_write64_uint64(io_addr, val);
527}
528

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551 addr.u64 = csr_addr;
552 addr.s.scraddr = scraddr >> 3;
553 addr.s.len = 1;
554 cvmx_send_single(addr.u64);
555}
556
557
558/**
506 * Number of the Core on which the program is currently running.
559 * Number of the Core on which the program is currently running.
507 *
508 * @return Number of cores
509 */
510static inline unsigned int cvmx_get_core_num(void)
511{
512 unsigned int core_num;
513 CVMX_RDHWRNV(core_num, 0);
514 return core_num;

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543{
544 int pop;
545 CVMX_DPOP(pop, val);
546 return pop;
547}
548
549
550/**
560 *
561 * @return Number of cores
562 */
563static inline unsigned int cvmx_get_core_num(void)
564{
565 unsigned int core_num;
566 CVMX_RDHWRNV(core_num, 0);
567 return core_num;

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596{
597 int pop;
598 CVMX_DPOP(pop, val);
599 return pop;
600}
601
602
603/**
551 * Provide current cycle counter as a return value
604 * @deprecated
605 * Provide current cycle counter as a return value. Deprecated, use
606 * cvmx_clock_get_count(CVMX_CLOCK_CORE) to get cycle counter.
552 *
553 * @return current cycle counter
554 */
555static inline uint64_t cvmx_get_cycle(void)
556{
607 *
608 * @return current cycle counter
609 */
610static inline uint64_t cvmx_get_cycle(void)
611{
557#if defined(CVMX_ABI_O32)
558 uint32_t tmp_low, tmp_hi;
559
560 asm volatile (
561 " .set push \n"
562 " .set mips64r2 \n"
563 " .set noreorder \n"
564 " rdhwr %[tmpl], $31 \n"
565 " dsrl %[tmph], %[tmpl], 32 \n"
566 " sll %[tmpl], 0 \n"
567 " sll %[tmph], 0 \n"
568 " .set pop \n"
569 : [tmpl] "=&r" (tmp_low), [tmph] "=&r" (tmp_hi) : );
570
571 return(((uint64_t)tmp_hi << 32) + tmp_low);
572#else
573 uint64_t cycle;
574 CVMX_RDHWR(cycle, 31);
575 return(cycle);
576#endif
612 return cvmx_clock_get_count(CVMX_CLOCK_CORE);
577}
578
579
580/**
613}
614
615
616/**
581 * Reads a chip global cycle counter. This counts CPU cycles since
582 * chip reset. The counter is 64 bit.
583 * This register does not exist on CN38XX pass 1 silicion
617 * @deprecated
618 * Reads a chip global cycle counter. This counts SCLK cycles since
619 * chip reset. The counter is 64 bit. This function is deprecated as the rate
620 * of the global cycle counter is different between Octeon+ and Octeon2, use
621 * cvmx_clock_get_count(CVMX_CLOCK_SCLK) instead. For Octeon2, the clock rate
622 * of SCLK may be differnet than the core clock.
584 *
585 * @return Global chip cycle count since chip reset.
586 */
587static inline uint64_t cvmx_get_cycle_global(void)
588{
623 *
624 * @return Global chip cycle count since chip reset.
625 */
626static inline uint64_t cvmx_get_cycle_global(void)
627{
589 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
590 return 0;
591 else
592 return cvmx_read64_uint64(CVMX_IPD_CLK_COUNT);
628 return cvmx_clock_get_count(CVMX_CLOCK_IPD);
593}
594
595
596/**
629}
630
631
632/**
597 * Wait for the specified number of cycle
633 * Wait for the specified number of core clock cycles
598 *
599 * @param cycles
600 */
601static inline void cvmx_wait(uint64_t cycles)
602{
603 uint64_t done = cvmx_get_cycle() + cycles;
604
605 while (cvmx_get_cycle() < done)

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611
612/**
613 * Wait for the specified number of micro seconds
614 *
615 * @param usec micro seconds to wait
616 */
617static inline void cvmx_wait_usec(uint64_t usec)
618{
634 *
635 * @param cycles
636 */
637static inline void cvmx_wait(uint64_t cycles)
638{
639 uint64_t done = cvmx_get_cycle() + cycles;
640
641 while (cvmx_get_cycle() < done)

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647
648/**
649 * Wait for the specified number of micro seconds
650 *
651 * @param usec micro seconds to wait
652 */
653static inline void cvmx_wait_usec(uint64_t usec)
654{
619 uint64_t done = cvmx_get_cycle() + usec * cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
655 uint64_t done = cvmx_get_cycle() + usec * cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;
620 while (cvmx_get_cycle() < done)
621 {
622 /* Spin */
623 }
624}
625
626
627/**
656 while (cvmx_get_cycle() < done)
657 {
658 /* Spin */
659 }
660}
661
662
663/**
664 * Wait for the specified number of io clock cycles
665 *
666 * @param cycles
667 */
668static inline void cvmx_wait_io(uint64_t cycles)
669{
670 uint64_t done = cvmx_clock_get_count(CVMX_CLOCK_SCLK) + cycles;
671
672 while (cvmx_clock_get_count(CVMX_CLOCK_SCLK) < done)
673 {
674 /* Spin */
675 }
676}
677
678
679/**
628 * Perform a soft reset of Octeon
629 *
630 * @return
631 */
632static inline void cvmx_reset_octeon(void)
633{
634 cvmx_ciu_soft_rst_t ciu_soft_rst;
635 ciu_soft_rst.u64 = 0;

--- 43 unchanged lines hidden --- 		680 * Perform a soft reset of Octeon
681 *
682 * @return
683 */
684static inline void cvmx_reset_octeon(void)
685{
686 cvmx_ciu_soft_rst_t ciu_soft_rst;
687 ciu_soft_rst.u64 = 0;

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