| ixp425_qmgr.c (193096) | ixp425_qmgr.c (215034) |
|---|---|
| 1/*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 43 unchanged lines hidden (view full) --- 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58*/ 59#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 43 unchanged lines hidden (view full) --- 52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 57 * SUCH DAMAGE. 58*/ 59#include <sys/cdefs.h> |
| 60__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/ixp425_qmgr.c 193096 2009-05-30 15:14:44Z attilio $"); | 60__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/ixp425_qmgr.c 215034 2010-11-09 10:59:09Z brucec $"); |
| 61 62/* 63 * Intel XScale Queue Manager support. 64 * 65 * Each IXP4XXX device has a hardware block that implements a priority 66 * queue manager that is shared between the XScale cpu and the backend 67 * devices (such as the NPE). Queues are accessed by reading/writing 68 * special memory locations. The queue contents are mapped into a shared --- 243 unchanged lines hidden (view full) --- 312 313 /* AQM Q upper-group (32-63) Full status register bitmasks */ 314 qi->qStat1BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); 315 } 316 } 317 318 sc->aqmFreeSramAddress = 0x100; /* Q buffer space starts at 0x2100 */ 319 | 61 62/* 63 * Intel XScale Queue Manager support. 64 * 65 * Each IXP4XXX device has a hardware block that implements a priority 66 * queue manager that is shared between the XScale cpu and the backend 67 * devices (such as the NPE). Queues are accessed by reading/writing 68 * special memory locations. The queue contents are mapped into a shared --- 243 unchanged lines hidden (view full) --- 312 313 /* AQM Q upper-group (32-63) Full status register bitmasks */ 314 qi->qStat1BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); 315 } 316 } 317 318 sc->aqmFreeSramAddress = 0x100; /* Q buffer space starts at 0x2100 */ 319 |
| 320 ixpqmgr_rebuild(sc); /* build inital priority table */ | 320 ixpqmgr_rebuild(sc); /* build initial priority table */ |
| 321 aqm_reset(sc); /* reset h/w */ 322 return (0); 323} 324 325static int 326ixpqmgr_detach(device_t dev) 327{ 328 struct ixpqmgr_softc *sc = device_get_softc(dev); --- 441 unchanged lines hidden (view full) --- 770 } else { 771 /* 772 * The event is triggered by more than 1 queue, 773 * the queue search will start from the beginning 774 * or the middle of the priority table. 775 * 776 * The search will end when all the bits of the interrupt 777 * register are cleared. There is no need to maintain | 321 aqm_reset(sc); /* reset h/w */ 322 return (0); 323} 324 325static int 326ixpqmgr_detach(device_t dev) 327{ 328 struct ixpqmgr_softc *sc = device_get_softc(dev); --- 441 unchanged lines hidden (view full) --- 770 } else { 771 /* 772 * The event is triggered by more than 1 queue, 773 * the queue search will start from the beginning 774 * or the middle of the priority table. 775 * 776 * The search will end when all the bits of the interrupt 777 * register are cleared. There is no need to maintain |
| 778 * a seperate value and test it at each iteration. | 778 * a separate value and test it at each iteration. |
| 779 */ 780 if (intRegVal & sc->lowPriorityTableFirstHalfMask) { 781 priorityTableIndex = 0; 782 } else { 783 priorityTableIndex = 16; 784 } 785 /* 786 * Iterate over the priority table until all the bits --- 319 unchanged lines hidden --- | 779 */ 780 if (intRegVal & sc->lowPriorityTableFirstHalfMask) { 781 priorityTableIndex = 0; 782 } else { 783 priorityTableIndex = 16; 784 } 785 /* 786 * Iterate over the priority table until all the bits --- 319 unchanged lines hidden --- |