| kirkwood.c (186899) | kirkwood.c (186909) |
|---|---|
| 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> | 1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 16 unchanged lines hidden (view full) --- 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> |
| 33__FBSDID("$FreeBSD: head/sys/arm/mv/kirkwood/kirkwood.c 186899 2009-01-08 13:20:28Z raj $"); | 33__FBSDID("$FreeBSD: head/sys/arm/mv/kirkwood/kirkwood.c 186909 2009-01-08 18:31:43Z raj $"); |
| 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38 39#include <machine/bus.h> 40 41#include <arm/mv/mvreg.h> --- 65 unchanged lines hidden (view full) --- 107 MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE, 4, 0xE0, 108 MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE, 4, 0xE8, 109 NULL, MV_INT_PEX0 110 }, 111 112 { 0, 0, 0 } 113}; 114 | 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38 39#include <machine/bus.h> 40 41#include <arm/mv/mvreg.h> --- 65 unchanged lines hidden (view full) --- 107 MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE, 4, 0xE0, 108 MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE, 4, 0xE8, 109 NULL, MV_INT_PEX0 110 }, 111 112 { 0, 0, 0 } 113}; 114 |
| 115struct resource_spec mv_gpio_spec[] = { | 115struct resource_spec mv_gpio_res[] = { |
| 116 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 117 { SYS_RES_IRQ, 0, RF_ACTIVE }, 118 { SYS_RES_IRQ, 1, RF_ACTIVE }, 119 { SYS_RES_IRQ, 2, RF_ACTIVE }, 120 { SYS_RES_IRQ, 3, RF_ACTIVE }, 121 { SYS_RES_IRQ, 4, RF_ACTIVE }, 122 { SYS_RES_IRQ, 5, RF_ACTIVE }, 123 { SYS_RES_IRQ, 6, RF_ACTIVE }, 124 { -1, 0 } 125}; 126 | 116 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 117 { SYS_RES_IRQ, 0, RF_ACTIVE }, 118 { SYS_RES_IRQ, 1, RF_ACTIVE }, 119 { SYS_RES_IRQ, 2, RF_ACTIVE }, 120 { SYS_RES_IRQ, 3, RF_ACTIVE }, 121 { SYS_RES_IRQ, 4, RF_ACTIVE }, 122 { SYS_RES_IRQ, 5, RF_ACTIVE }, 123 { SYS_RES_IRQ, 6, RF_ACTIVE }, 124 { -1, 0 } 125}; 126 |
| 127struct resource_spec mv_xor_spec[] = { | 127struct resource_spec mv_xor_res[] = { |
| 128 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 129 { SYS_RES_IRQ, 0, RF_ACTIVE }, 130 { SYS_RES_IRQ, 1, RF_ACTIVE }, 131 { SYS_RES_IRQ, 2, RF_ACTIVE }, 132 { SYS_RES_IRQ, 3, RF_ACTIVE }, 133 { SYS_RES_IRQ, 4, RF_ACTIVE }, 134 { SYS_RES_IRQ, 5, RF_ACTIVE }, 135 { -1, 0 } --- 6 unchanged lines hidden (view full) --- 142 /* Device bus CS0 */ 143 { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 144 145 /* Device bus CS1 */ 146 { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 147 148 /* Device bus CS2 */ 149 { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, | 128 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 129 { SYS_RES_IRQ, 0, RF_ACTIVE }, 130 { SYS_RES_IRQ, 1, RF_ACTIVE }, 131 { SYS_RES_IRQ, 2, RF_ACTIVE }, 132 { SYS_RES_IRQ, 3, RF_ACTIVE }, 133 { SYS_RES_IRQ, 4, RF_ACTIVE }, 134 { SYS_RES_IRQ, 5, RF_ACTIVE }, 135 { -1, 0 } --- 6 unchanged lines hidden (view full) --- 142 /* Device bus CS0 */ 143 { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 144 145 /* Device bus CS1 */ 146 { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 147 148 /* Device bus CS2 */ 149 { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, |
| 150 151 /* CESA */ 152 { 3, 0x00, MV_CESA_SRAM_PHYS_BASE, MV_CESA_SRAM_SIZE, -1 }, 153 |
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| 150}; 151const struct decode_win *cpu_wins = cpu_win_tbl; 152int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 153 | 154}; 155const struct decode_win *cpu_wins = cpu_win_tbl; 156int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 157 |
| 158const struct decode_win xor_win_tbl[] = { 159 /* PCIE MEM */ 160 { 4, 0xE8, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 }, 161}; 162const struct decode_win *xor_wins = xor_win_tbl; 163int xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win); 164 |
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| 154uint32_t 155get_tclk(void) 156{ 157 uint32_t dev, rev; 158 159 /* 160 * On Kirkwood TCLK is not configurable and depends on silicon 161 * revision: 162 * - A0 has TCLK hardcoded to 200 MHz. 163 * - Z0 and others have TCLK hardcoded to 166 MHz. 164 */ 165 soc_id(&dev, &rev); 166 if (dev == MV_DEV_88F6281 && rev == 2) 167 return (TCLK_200MHZ); 168 169 return (TCLK_166MHZ); 170} | 165uint32_t 166get_tclk(void) 167{ 168 uint32_t dev, rev; 169 170 /* 171 * On Kirkwood TCLK is not configurable and depends on silicon 172 * revision: 173 * - A0 has TCLK hardcoded to 200 MHz. 174 * - Z0 and others have TCLK hardcoded to 166 MHz. 175 */ 176 soc_id(&dev, &rev); 177 if (dev == MV_DEV_88F6281 && rev == 2) 178 return (TCLK_200MHZ); 179 180 return (TCLK_166MHZ); 181} |