1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
| 1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
|
33__FBSDID("$FreeBSD: head/sys/arm/mv/kirkwood/kirkwood.c 186899 2009-01-08 13:20:28Z raj $");
| 33__FBSDID("$FreeBSD: head/sys/arm/mv/kirkwood/kirkwood.c 186909 2009-01-08 18:31:43Z raj $");
|
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38
39#include <machine/bus.h>
40
41#include <arm/mv/mvreg.h>
42#include <arm/mv/mvvar.h>
43
44struct obio_device obio_devices[] = {
45 { "ic", MV_IC_BASE, MV_IC_SIZE,
46 { -1 },
47 { -1 },
48 CPU_PM_CTRL_NONE
49 },
50 { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
51 { MV_INT_BRIDGE, -1 },
52 { -1 },
53 CPU_PM_CTRL_NONE
54 },
55 { "rtc", MV_RTC_BASE, MV_RTC_SIZE,
56 { -1 },
57 { -1 },
58 CPU_PM_CTRL_NONE
59 },
60 { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
61 { MV_INT_GPIO7_0, MV_INT_GPIO15_8,
62 MV_INT_GPIO23_16, MV_INT_GPIO31_24,
63 MV_INT_GPIOHI7_0, MV_INT_GPIOHI15_8,
64 MV_INT_GPIOHI23_16, -1 },
65 { -1 },
66 CPU_PM_CTRL_NONE
67 },
68 { "uart", MV_UART0_BASE, MV_UART_SIZE,
69 { MV_INT_UART0, -1 },
70 { -1 },
71 CPU_PM_CTRL_NONE
72 },
73 { "uart", MV_UART1_BASE, MV_UART_SIZE,
74 { MV_INT_UART1, -1 },
75 { -1 },
76 CPU_PM_CTRL_NONE
77 },
78 { "xor", MV_XOR_BASE, MV_XOR_SIZE,
79 { MV_INT_XOR0_CHAN0, MV_INT_XOR0_CHAN1,
80 MV_INT_XOR1_CHAN0, MV_INT_XOR1_CHAN1,
81 MV_INT_XOR0_ERR, MV_INT_XOR1_ERR,
82 -1 },
83 { -1 },
84 CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1
85 },
86 { "ehci", MV_USB0_BASE, MV_USB_SIZE,
87 { MV_INT_USB_BERR, MV_INT_USB_CI, -1 },
88 { -1 },
89 CPU_PM_CTRL_USB0
90 },
91 { "mge", MV_ETH0_BASE, MV_ETH_SIZE,
92 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
93 MV_INT_GBESUM, MV_INT_GBEERR, -1 },
94 { -1 },
95 CPU_PM_CTRL_GE0
96 },
97 { "twsi", MV_TWSI_BASE, MV_TWSI_SIZE,
98 { -1 }, { -1 },
99 CPU_PM_CTRL_NONE
100 },
101 { NULL, 0, 0, { 0 }, { 0 }, 0 }
102};
103
104const struct obio_pci mv_pci_info[] = {
105 { MV_TYPE_PCIE,
106 MV_PCIE_BASE, MV_PCIE_SIZE,
107 MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE, 4, 0xE0,
108 MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE, 4, 0xE8,
109 NULL, MV_INT_PEX0
110 },
111
112 { 0, 0, 0 }
113};
114
| 34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38
39#include <machine/bus.h>
40
41#include <arm/mv/mvreg.h>
42#include <arm/mv/mvvar.h>
43
44struct obio_device obio_devices[] = {
45 { "ic", MV_IC_BASE, MV_IC_SIZE,
46 { -1 },
47 { -1 },
48 CPU_PM_CTRL_NONE
49 },
50 { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
51 { MV_INT_BRIDGE, -1 },
52 { -1 },
53 CPU_PM_CTRL_NONE
54 },
55 { "rtc", MV_RTC_BASE, MV_RTC_SIZE,
56 { -1 },
57 { -1 },
58 CPU_PM_CTRL_NONE
59 },
60 { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
61 { MV_INT_GPIO7_0, MV_INT_GPIO15_8,
62 MV_INT_GPIO23_16, MV_INT_GPIO31_24,
63 MV_INT_GPIOHI7_0, MV_INT_GPIOHI15_8,
64 MV_INT_GPIOHI23_16, -1 },
65 { -1 },
66 CPU_PM_CTRL_NONE
67 },
68 { "uart", MV_UART0_BASE, MV_UART_SIZE,
69 { MV_INT_UART0, -1 },
70 { -1 },
71 CPU_PM_CTRL_NONE
72 },
73 { "uart", MV_UART1_BASE, MV_UART_SIZE,
74 { MV_INT_UART1, -1 },
75 { -1 },
76 CPU_PM_CTRL_NONE
77 },
78 { "xor", MV_XOR_BASE, MV_XOR_SIZE,
79 { MV_INT_XOR0_CHAN0, MV_INT_XOR0_CHAN1,
80 MV_INT_XOR1_CHAN0, MV_INT_XOR1_CHAN1,
81 MV_INT_XOR0_ERR, MV_INT_XOR1_ERR,
82 -1 },
83 { -1 },
84 CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1
85 },
86 { "ehci", MV_USB0_BASE, MV_USB_SIZE,
87 { MV_INT_USB_BERR, MV_INT_USB_CI, -1 },
88 { -1 },
89 CPU_PM_CTRL_USB0
90 },
91 { "mge", MV_ETH0_BASE, MV_ETH_SIZE,
92 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
93 MV_INT_GBESUM, MV_INT_GBEERR, -1 },
94 { -1 },
95 CPU_PM_CTRL_GE0
96 },
97 { "twsi", MV_TWSI_BASE, MV_TWSI_SIZE,
98 { -1 }, { -1 },
99 CPU_PM_CTRL_NONE
100 },
101 { NULL, 0, 0, { 0 }, { 0 }, 0 }
102};
103
104const struct obio_pci mv_pci_info[] = {
105 { MV_TYPE_PCIE,
106 MV_PCIE_BASE, MV_PCIE_SIZE,
107 MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE, 4, 0xE0,
108 MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE, 4, 0xE8,
109 NULL, MV_INT_PEX0
110 },
111
112 { 0, 0, 0 }
113};
114
|
115struct resource_spec mv_gpio_spec[] = {
| 115struct resource_spec mv_gpio_res[] = {
|
116 { SYS_RES_MEMORY, 0, RF_ACTIVE },
117 { SYS_RES_IRQ, 0, RF_ACTIVE },
118 { SYS_RES_IRQ, 1, RF_ACTIVE },
119 { SYS_RES_IRQ, 2, RF_ACTIVE },
120 { SYS_RES_IRQ, 3, RF_ACTIVE },
121 { SYS_RES_IRQ, 4, RF_ACTIVE },
122 { SYS_RES_IRQ, 5, RF_ACTIVE },
123 { SYS_RES_IRQ, 6, RF_ACTIVE },
124 { -1, 0 }
125};
126
| 116 { SYS_RES_MEMORY, 0, RF_ACTIVE },
117 { SYS_RES_IRQ, 0, RF_ACTIVE },
118 { SYS_RES_IRQ, 1, RF_ACTIVE },
119 { SYS_RES_IRQ, 2, RF_ACTIVE },
120 { SYS_RES_IRQ, 3, RF_ACTIVE },
121 { SYS_RES_IRQ, 4, RF_ACTIVE },
122 { SYS_RES_IRQ, 5, RF_ACTIVE },
123 { SYS_RES_IRQ, 6, RF_ACTIVE },
124 { -1, 0 }
125};
126
|
127struct resource_spec mv_xor_spec[] = {
| 127struct resource_spec mv_xor_res[] = {
|
128 { SYS_RES_MEMORY, 0, RF_ACTIVE },
129 { SYS_RES_IRQ, 0, RF_ACTIVE },
130 { SYS_RES_IRQ, 1, RF_ACTIVE },
131 { SYS_RES_IRQ, 2, RF_ACTIVE },
132 { SYS_RES_IRQ, 3, RF_ACTIVE },
133 { SYS_RES_IRQ, 4, RF_ACTIVE },
134 { SYS_RES_IRQ, 5, RF_ACTIVE },
135 { -1, 0 }
136};
137
138const struct decode_win cpu_win_tbl[] = {
139 /* Device bus BOOT */
140 { 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
141
142 /* Device bus CS0 */
143 { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
144
145 /* Device bus CS1 */
146 { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
147
148 /* Device bus CS2 */
149 { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
| 128 { SYS_RES_MEMORY, 0, RF_ACTIVE },
129 { SYS_RES_IRQ, 0, RF_ACTIVE },
130 { SYS_RES_IRQ, 1, RF_ACTIVE },
131 { SYS_RES_IRQ, 2, RF_ACTIVE },
132 { SYS_RES_IRQ, 3, RF_ACTIVE },
133 { SYS_RES_IRQ, 4, RF_ACTIVE },
134 { SYS_RES_IRQ, 5, RF_ACTIVE },
135 { -1, 0 }
136};
137
138const struct decode_win cpu_win_tbl[] = {
139 /* Device bus BOOT */
140 { 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
141
142 /* Device bus CS0 */
143 { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
144
145 /* Device bus CS1 */
146 { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
147
148 /* Device bus CS2 */
149 { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
|
| 150
151 /* CESA */
152 { 3, 0x00, MV_CESA_SRAM_PHYS_BASE, MV_CESA_SRAM_SIZE, -1 },
153
|
150};
151const struct decode_win *cpu_wins = cpu_win_tbl;
152int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
153
| 154};
155const struct decode_win *cpu_wins = cpu_win_tbl;
156int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
157
|
| 158const struct decode_win xor_win_tbl[] = {
159 /* PCIE MEM */
160 { 4, 0xE8, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
161};
162const struct decode_win *xor_wins = xor_win_tbl;
163int xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win);
164
|
154uint32_t
155get_tclk(void)
156{
157 uint32_t dev, rev;
158
159 /*
160 * On Kirkwood TCLK is not configurable and depends on silicon
161 * revision:
162 * - A0 has TCLK hardcoded to 200 MHz.
163 * - Z0 and others have TCLK hardcoded to 166 MHz.
164 */
165 soc_id(&dev, &rev);
166 if (dev == MV_DEV_88F6281 && rev == 2)
167 return (TCLK_200MHZ);
168
169 return (TCLK_166MHZ);
170}
| 165uint32_t
166get_tclk(void)
167{
168 uint32_t dev, rev;
169
170 /*
171 * On Kirkwood TCLK is not configurable and depends on silicon
172 * revision:
173 * - A0 has TCLK hardcoded to 200 MHz.
174 * - Z0 and others have TCLK hardcoded to 166 MHz.
175 */
176 soc_id(&dev, &rev);
177 if (dev == MV_DEV_88F6281 && rev == 2)
178 return (TCLK_200MHZ);
179
180 return (TCLK_166MHZ);
181}
|