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gpio.c (186901) gpio.c (186909)
1/*-
2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
4 * All rights reserved.
5 *
6 * Adapted and extended for Marvell SoCs by Semihalf.
7 *
8 * Redistribution and use in source and binary forms, with or without

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
4 * All rights reserved.
5 *
6 * Adapted and extended for Marvell SoCs by Semihalf.
7 *
8 * Redistribution and use in source and binary forms, with or without

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/arm/mv/gpio.c 186901 2009-01-08 13:25:22Z raj $");
32__FBSDID("$FreeBSD: head/sys/arm/mv/gpio.c 186909 2009-01-08 18:31:43Z raj $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/lock.h>
39#include <sys/interrupt.h>
40#include <sys/module.h>

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57 void *ih_cookie[GPIO_MAX_INTR_COUNT];
58 bus_space_tag_t bst;
59 bus_space_handle_t bsh;
60 uint8_t pin_num; /* number of GPIO pins */
61 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
62 uint8_t use_high;
63};
64
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/lock.h>
39#include <sys/interrupt.h>
40#include <sys/module.h>

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57 void *ih_cookie[GPIO_MAX_INTR_COUNT];
58 bus_space_tag_t bst;
59 bus_space_handle_t bsh;
60 uint8_t pin_num; /* number of GPIO pins */
61 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
62 uint8_t use_high;
63};
64
65extern struct resource_spec mv_gpio_spec[];
65extern struct resource_spec mv_gpio_res[];
66
67static struct mv_gpio_softc *mv_gpio_softc = NULL;
68static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
69
70static int mv_gpio_probe(device_t);
71static int mv_gpio_attach(device_t);
72static void mv_gpio_intr(void *);
73

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138 sc->irq_num = 7;
139 sc->use_high = 1;
140
141 } else {
142 device_printf(dev, "unknown board id=0x%x\n", dev_id);
143 return (ENXIO);
144 }
145
66
67static struct mv_gpio_softc *mv_gpio_softc = NULL;
68static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
69
70static int mv_gpio_probe(device_t);
71static int mv_gpio_attach(device_t);
72static void mv_gpio_intr(void *);
73

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138 sc->irq_num = 7;
139 sc->use_high = 1;
140
141 } else {
142 device_printf(dev, "unknown board id=0x%x\n", dev_id);
143 return (ENXIO);
144 }
145
146 error = bus_alloc_resources(dev, mv_gpio_spec, sc->res);
146 error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
147 if (error) {
148 device_printf(dev, "could not allocate resources\n");
149 return (ENXIO);
150 }
151
152 sc->bst = rman_get_bustag(sc->res[0]);
153 sc->bsh = rman_get_bushandle(sc->res[0]);
154

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166 GPIO_HI_INT_CAUSE, 0);
167 }
168
169 for (i = 0; i < sc->irq_num; i++) {
170 if (bus_setup_intr(dev, sc->res[1 + i],
171 INTR_TYPE_MISC | INTR_FAST,
172 (driver_filter_t *)mv_gpio_intr, NULL,
173 sc, &sc->ih_cookie[i]) != 0) {
147 if (error) {
148 device_printf(dev, "could not allocate resources\n");
149 return (ENXIO);
150 }
151
152 sc->bst = rman_get_bustag(sc->res[0]);
153 sc->bsh = rman_get_bushandle(sc->res[0]);
154

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166 GPIO_HI_INT_CAUSE, 0);
167 }
168
169 for (i = 0; i < sc->irq_num; i++) {
170 if (bus_setup_intr(dev, sc->res[1 + i],
171 INTR_TYPE_MISC | INTR_FAST,
172 (driver_filter_t *)mv_gpio_intr, NULL,
173 sc, &sc->ih_cookie[i]) != 0) {
174 bus_release_resources(dev, mv_gpio_spec, sc->res);
174 bus_release_resources(dev, mv_gpio_res, sc->res);
175 device_printf(dev, "could not set up intr %d\n", i);
176 return (ENXIO);
177 }
178 }
179
175 device_printf(dev, "could not set up intr %d\n", i);
176 return (ENXIO);
177 }
178 }
179
180 /* Setup GPIO lines */
181 for (i = 0; mv_gpio_config[i].gc_gpio >= 0; i++) {
182 mv_gpio_configure(mv_gpio_config[i].gc_gpio,
183 mv_gpio_config[i].gc_flags, ~0u);
184
185 if (mv_gpio_config[i].gc_output < 0)
186 mv_gpio_out_en(mv_gpio_config[i].gc_gpio, 0);
187 else
188 mv_gpio_out(mv_gpio_config[i].gc_gpio,
189 mv_gpio_config[i].gc_output, 1);
190 }
191
180 return (0);
181}
182
183static void
184mv_gpio_intr(void *arg)
185{
192 return (0);
193}
194
195static void
196mv_gpio_intr(void *arg)
197{
186 uint32_t int_cause, gpio_val;
187 uint32_t int_cause_hi, gpio_val_hi = 0;
188 int i;
198 uint32_t int_cause, gpio_val;
199 uint32_t int_cause_hi, gpio_val_hi = 0;
200 int i;
189
190 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
191 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
192 gpio_val &= int_cause;
193 if (mv_gpio_softc->use_high) {
194 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
195 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
196 gpio_val_hi &= int_cause_hi;

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290mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask)
291{
292
293 if (pin >= mv_gpio_softc->pin_num)
294 return (EINVAL);
295
296 if (mask & MV_GPIO_BLINK)
297 mv_gpio_blink(pin, flags & MV_GPIO_BLINK);
201
202 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
203 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
204 gpio_val &= int_cause;
205 if (mv_gpio_softc->use_high) {
206 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
207 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
208 gpio_val_hi &= int_cause_hi;

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302mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask)
303{
304
305 if (pin >= mv_gpio_softc->pin_num)
306 return (EINVAL);
307
308 if (mask & MV_GPIO_BLINK)
309 mv_gpio_blink(pin, flags & MV_GPIO_BLINK);
298 if (mask & MV_GPIO_POLARITY)
299 mv_gpio_polarity(pin, flags & MV_GPIO_POLARITY);
310 if (mask & MV_GPIO_POLAR_LOW)
311 mv_gpio_polarity(pin, flags & MV_GPIO_POLAR_LOW);
300 if (mask & MV_GPIO_EDGE)
301 mv_gpio_edge(pin, flags & MV_GPIO_EDGE);
302 if (mask & MV_GPIO_LEVEL)
303 mv_gpio_level(pin, flags & MV_GPIO_LEVEL);
304
305 gpio_setup[pin] &= ~(mask);
306 gpio_setup[pin] |= (flags & mask);
307

--- 209 unchanged lines hidden --- 		312 if (mask & MV_GPIO_EDGE)
313 mv_gpio_edge(pin, flags & MV_GPIO_EDGE);
314 if (mask & MV_GPIO_LEVEL)
315 mv_gpio_level(pin, flags & MV_GPIO_LEVEL);
316
317 gpio_setup[pin] &= ~(mask);
318 gpio_setup[pin] |= (flags & mask);
319

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