| specialreg.h (165918) | specialreg.h (167493) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 13 unchanged lines hidden (view full) --- 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
| 30 * $FreeBSD: head/sys/amd64/include/specialreg.h 165918 2007-01-09 19:23:22Z jkim $ | 30 * $FreeBSD: head/sys/amd64/include/specialreg.h 167493 2007-03-12 20:27:21Z jkim $ |
| 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ --- 68 unchanged lines hidden (view full) --- 107#define CPUID_XMM 0x02000000 108#define CPUID_SSE2 0x04000000 109#define CPUID_SS 0x08000000 110#define CPUID_HTT 0x10000000 111#define CPUID_TM 0x20000000 112#define CPUID_IA64 0x40000000 113#define CPUID_PBE 0x80000000 114 | 31 */ 32 33#ifndef _MACHINE_SPECIALREG_H_ 34#define _MACHINE_SPECIALREG_H_ 35 36/* 37 * Bits in 386 special registers: 38 */ --- 68 unchanged lines hidden (view full) --- 107#define CPUID_XMM 0x02000000 108#define CPUID_SSE2 0x04000000 109#define CPUID_SS 0x08000000 110#define CPUID_HTT 0x10000000 111#define CPUID_TM 0x20000000 112#define CPUID_IA64 0x40000000 113#define CPUID_PBE 0x80000000 114 |
| 115#define CPUID2_SSE3 0x00000001 116#define CPUID2_MON 0x00000008 117#define CPUID2_DS_CPL 0x00000010 118#define CPUID2_VMX 0x00000020 119#define CPUID2_EST 0x00000080 120#define CPUID2_TM2 0x00000100 121#define CPUID2_SSSE3 0x00000200 122#define CPUID2_CNXTID 0x00000400 123#define CPUID2_CX16 0x00002000 124#define CPUID2_XTPR 0x00004000 | 115#define CPUID2_SSE3 0x00000001 116#define CPUID2_MON 0x00000008 117#define CPUID2_DS_CPL 0x00000010 118#define CPUID2_VMX 0x00000020 119#define CPUID2_EST 0x00000080 120#define CPUID2_TM2 0x00000100 121#define CPUID2_SSSE3 0x00000200 122#define CPUID2_CNXTID 0x00000400 123#define CPUID2_CX16 0x00002000 124#define CPUID2_XTPR 0x00004000 |
| 125 126/* 127 * Important bits in the AMD extended cpuid flags 128 */ | 125 126/* 127 * Important bits in the AMD extended cpuid flags 128 */ |
| 129#define AMDID_SYSCALL 0x00000800 130#define AMDID_MP 0x00080000 131#define AMDID_NX 0x00100000 132#define AMDID_EXT_MMX 0x00400000 133#define AMDID_FFXSR 0x01000000 134#define AMDID_RDTSCP 0x08000000 135#define AMDID_LM 0x20000000 136#define AMDID_EXT_3DNOW 0x40000000 137#define AMDID_3DNOW 0x80000000 | 129#define AMDID_SYSCALL 0x00000800 130#define AMDID_MP 0x00080000 131#define AMDID_NX 0x00100000 132#define AMDID_EXT_MMX 0x00400000 133#define AMDID_FFXSR 0x01000000 134#define AMDID_RDTSCP 0x08000000 135#define AMDID_LM 0x20000000 136#define AMDID_EXT_3DNOW 0x40000000 137#define AMDID_3DNOW 0x80000000 |
| 138 | 138 |
| 139#define AMDID2_LAHF 0x00000001 140#define AMDID2_CMP 0x00000002 141#define AMDID2_SVM 0x00000004 142#define AMDID2_EXT_APIC 0x00000008 143#define AMDID2_CR8 0x00000010 | 139#define AMDID2_LAHF 0x00000001 140#define AMDID2_CMP 0x00000002 141#define AMDID2_SVM 0x00000004 142#define AMDID2_EXT_APIC 0x00000008 143#define AMDID2_CR8 0x00000010 144#define AMDID2_PREFETCH 0x00000100 |
| 144 145/* 146 * CPUID instruction 1 ebx info 147 */ 148#define CPUID_BRAND_INDEX 0x000000ff 149#define CPUID_CLFUSH_SIZE 0x0000ff00 150#define CPUID_HTT_CORES 0x00ff0000 151#define CPUID_LOCAL_APIC_ID 0xff000000 152 153/* 154 * AMD extended function 8000_0008h ecx info 155 */ | 145 146/* 147 * CPUID instruction 1 ebx info 148 */ 149#define CPUID_BRAND_INDEX 0x000000ff 150#define CPUID_CLFUSH_SIZE 0x0000ff00 151#define CPUID_HTT_CORES 0x00ff0000 152#define CPUID_LOCAL_APIC_ID 0xff000000 153 154/* 155 * AMD extended function 8000_0008h ecx info 156 */ |
| 156#define AMDID_CMP_CORES 0x000000ff | 157#define AMDID_CMP_CORES 0x000000ff |
| 157 158/* 159 * Model-specific registers for the i386 family 160 */ | 158 159/* 160 * Model-specific registers for the i386 family 161 */ |
| 161#define MSR_P5_MC_ADDR 0x000 162#define MSR_P5_MC_TYPE 0x001 163#define MSR_TSC 0x010 | 162#define MSR_P5_MC_ADDR 0x000 163#define MSR_P5_MC_TYPE 0x001 164#define MSR_TSC 0x010 |
| 164#define MSR_P5_CESR 0x011 165#define MSR_P5_CTR0 0x012 166#define MSR_P5_CTR1 0x013 167#define MSR_IA32_PLATFORM_ID 0x017 | 165#define MSR_P5_CESR 0x011 166#define MSR_P5_CTR0 0x012 167#define MSR_P5_CTR1 0x013 168#define MSR_IA32_PLATFORM_ID 0x017 |
| 168#define MSR_APICBASE 0x01b 169#define MSR_EBL_CR_POWERON 0x02a | 169#define MSR_APICBASE 0x01b 170#define MSR_EBL_CR_POWERON 0x02a |
| 170#define MSR_TEST_CTL 0x033 | 171#define MSR_TEST_CTL 0x033 |
| 171#define MSR_BIOS_UPDT_TRIG 0x079 | 172#define MSR_BIOS_UPDT_TRIG 0x079 |
| 172#define MSR_BBL_CR_D0 0x088 173#define MSR_BBL_CR_D1 0x089 174#define MSR_BBL_CR_D2 0x08a | 173#define MSR_BBL_CR_D0 0x088 174#define MSR_BBL_CR_D1 0x089 175#define MSR_BBL_CR_D2 0x08a |
| 175#define MSR_BIOS_SIGN 0x08b 176#define MSR_PERFCTR0 0x0c1 177#define MSR_PERFCTR1 0x0c2 178#define MSR_MTRRcap 0x0fe | 176#define MSR_BIOS_SIGN 0x08b 177#define MSR_PERFCTR0 0x0c1 178#define MSR_PERFCTR1 0x0c2 179#define MSR_MTRRcap 0x0fe |
| 179#define MSR_BBL_CR_ADDR 0x116 180#define MSR_BBL_CR_DECC 0x118 181#define MSR_BBL_CR_CTL 0x119 182#define MSR_BBL_CR_TRIG 0x11a 183#define MSR_BBL_CR_BUSY 0x11b 184#define MSR_BBL_CR_CTL3 0x11e 185#define MSR_SYSENTER_CS_MSR 0x174 186#define MSR_SYSENTER_ESP_MSR 0x175 187#define MSR_SYSENTER_EIP_MSR 0x176 | 180#define MSR_BBL_CR_ADDR 0x116 181#define MSR_BBL_CR_DECC 0x118 182#define MSR_BBL_CR_CTL 0x119 183#define MSR_BBL_CR_TRIG 0x11a 184#define MSR_BBL_CR_BUSY 0x11b 185#define MSR_BBL_CR_CTL3 0x11e 186#define MSR_SYSENTER_CS_MSR 0x174 187#define MSR_SYSENTER_ESP_MSR 0x175 188#define MSR_SYSENTER_EIP_MSR 0x176 |
| 188#define MSR_MCG_CAP 0x179 189#define MSR_MCG_STATUS 0x17a 190#define MSR_MCG_CTL 0x17b 191#define MSR_EVNTSEL0 0x186 192#define MSR_EVNTSEL1 0x187 193#define MSR_THERM_CONTROL 0x19a 194#define MSR_THERM_INTERRUPT 0x19b 195#define MSR_THERM_STATUS 0x19c | 189#define MSR_MCG_CAP 0x179 190#define MSR_MCG_STATUS 0x17a 191#define MSR_MCG_CTL 0x17b 192#define MSR_EVNTSEL0 0x186 193#define MSR_EVNTSEL1 0x187 194#define MSR_THERM_CONTROL 0x19a 195#define MSR_THERM_INTERRUPT 0x19b 196#define MSR_THERM_STATUS 0x19c |
| 196#define MSR_IA32_MISC_ENABLE 0x1a0 | 197#define MSR_IA32_MISC_ENABLE 0x1a0 |
| 197#define MSR_DEBUGCTLMSR 0x1d9 198#define MSR_LASTBRANCHFROMIP 0x1db 199#define MSR_LASTBRANCHTOIP 0x1dc 200#define MSR_LASTINTFROMIP 0x1dd 201#define MSR_LASTINTTOIP 0x1de 202#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 203#define MSR_MTRRVarBase 0x200 204#define MSR_MTRR64kBase 0x250 205#define MSR_MTRR16kBase 0x258 206#define MSR_MTRR4kBase 0x268 207#define MSR_PAT 0x277 208#define MSR_MTRRdefType 0x2ff 209#define MSR_MC0_CTL 0x400 210#define MSR_MC0_STATUS 0x401 211#define MSR_MC0_ADDR 0x402 212#define MSR_MC0_MISC 0x403 213#define MSR_MC1_CTL 0x404 214#define MSR_MC1_STATUS 0x405 215#define MSR_MC1_ADDR 0x406 216#define MSR_MC1_MISC 0x407 217#define MSR_MC2_CTL 0x408 218#define MSR_MC2_STATUS 0x409 219#define MSR_MC2_ADDR 0x40a 220#define MSR_MC2_MISC 0x40b 221#define MSR_MC3_CTL 0x40c 222#define MSR_MC3_STATUS 0x40d 223#define MSR_MC3_ADDR 0x40e 224#define MSR_MC3_MISC 0x40f 225#define MSR_MC4_CTL 0x410 226#define MSR_MC4_STATUS 0x411 227#define MSR_MC4_ADDR 0x412 228#define MSR_MC4_MISC 0x413 | 198#define MSR_DEBUGCTLMSR 0x1d9 199#define MSR_LASTBRANCHFROMIP 0x1db 200#define MSR_LASTBRANCHTOIP 0x1dc 201#define MSR_LASTINTFROMIP 0x1dd 202#define MSR_LASTINTTOIP 0x1de 203#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 204#define MSR_MTRRVarBase 0x200 205#define MSR_MTRR64kBase 0x250 206#define MSR_MTRR16kBase 0x258 207#define MSR_MTRR4kBase 0x268 208#define MSR_PAT 0x277 209#define MSR_MTRRdefType 0x2ff 210#define MSR_MC0_CTL 0x400 211#define MSR_MC0_STATUS 0x401 212#define MSR_MC0_ADDR 0x402 213#define MSR_MC0_MISC 0x403 214#define MSR_MC1_CTL 0x404 215#define MSR_MC1_STATUS 0x405 216#define MSR_MC1_ADDR 0x406 217#define MSR_MC1_MISC 0x407 218#define MSR_MC2_CTL 0x408 219#define MSR_MC2_STATUS 0x409 220#define MSR_MC2_ADDR 0x40a 221#define MSR_MC2_MISC 0x40b 222#define MSR_MC3_CTL 0x40c 223#define MSR_MC3_STATUS 0x40d 224#define MSR_MC3_ADDR 0x40e 225#define MSR_MC3_MISC 0x40f 226#define MSR_MC4_CTL 0x410 227#define MSR_MC4_STATUS 0x411 228#define MSR_MC4_ADDR 0x412 229#define MSR_MC4_MISC 0x413 |
| 229 230/* 231 * Constants related to MSR's. 232 */ 233#define APICBASE_RESERVED 0x000006ff 234#define APICBASE_BSP 0x00000100 235#define APICBASE_ENABLED 0x00000800 236#define APICBASE_ADDRESS 0xfffff000 --- 8 unchanged lines hidden (view full) --- 245#define PAT_WRITE_BACK 0x06 246#define PAT_UNCACHED 0x07 247#define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 248#define PAT_MASK(i) PAT_VALUE(i, 0xff) 249 250/* 251 * Constants related to MTRRs 252 */ | 230 231/* 232 * Constants related to MSR's. 233 */ 234#define APICBASE_RESERVED 0x000006ff 235#define APICBASE_BSP 0x00000100 236#define APICBASE_ENABLED 0x00000800 237#define APICBASE_ADDRESS 0xfffff000 --- 8 unchanged lines hidden (view full) --- 246#define PAT_WRITE_BACK 0x06 247#define PAT_UNCACHED 0x07 248#define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) 249#define PAT_MASK(i) PAT_VALUE(i, 0xff) 250 251/* 252 * Constants related to MTRRs 253 */ |
| 253#define MTRR_N64K 8 /* numbers of fixed-size entries */ 254#define MTRR_N16K 16 255#define MTRR_N4K 64 | 254#define MTRR_N64K 8 /* numbers of fixed-size entries */ 255#define MTRR_N16K 16 256#define MTRR_N4K 64 |
| 256 257/* Performance Control Register (5x86 only). */ 258#define PCR0 0x20 259#define PCR0_RSTK 0x01 /* Enables return stack */ 260#define PCR0_BTB 0x02 /* Enables branch target buffer */ 261#define PCR0_LOOP 0x04 /* Enables loop */ 262#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 263 serialize pipe. */ --- 80 unchanged lines hidden (view full) --- 344#define RCR1 0xdd 345#define RCR2 0xde 346#define RCR3 0xdf 347#define RCR4 0xe0 348#define RCR5 0xe1 349#define RCR6 0xe2 350#define RCR7 0xe3 351 | 257 258/* Performance Control Register (5x86 only). */ 259#define PCR0 0x20 260#define PCR0_RSTK 0x01 /* Enables return stack */ 261#define PCR0_BTB 0x02 /* Enables branch target buffer */ 262#define PCR0_LOOP 0x04 /* Enables loop */ 263#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 264 serialize pipe. */ --- 80 unchanged lines hidden (view full) --- 345#define RCR1 0xdd 346#define RCR2 0xde 347#define RCR3 0xdf 348#define RCR4 0xe0 349#define RCR5 0xe1 350#define RCR6 0xe2 351#define RCR7 0xe3 352 |
| 352#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 353#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 354#define RCR_WWO 0x02 /* Weak write ordering. */ | 353#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 354#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 355#define RCR_WWO 0x02 /* Weak write ordering. */ |
| 355#define RCR_WL 0x04 /* Weak locking. */ | 356#define RCR_WL 0x04 /* Weak locking. */ |
| 356#define RCR_WG 0x08 /* Write gathering. */ | 357#define RCR_WG 0x08 /* Write gathering. */ |
| 357#define RCR_WT 0x10 /* Write-through. */ 358#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 359 360/* AMD Write Allocate Top-Of-Memory and Control Register */ 361#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 362#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 363#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 364 --- 28 unchanged lines hidden --- | 358#define RCR_WT 0x10 /* Write-through. */ 359#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 360 361/* AMD Write Allocate Top-Of-Memory and Control Register */ 362#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 363#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 364#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 365 --- 28 unchanged lines hidden --- |