| X86InstrInfo.h (210299) | X86InstrInfo.h (212904) |
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| 1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 297 unchanged lines hidden (view full) --- 306 MRM_C3 = 35, 307 MRM_C4 = 36, 308 MRM_C8 = 37, 309 MRM_C9 = 38, 310 MRM_E8 = 39, 311 MRM_F0 = 40, 312 MRM_F8 = 41, 313 MRM_F9 = 42, | 1//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 297 unchanged lines hidden (view full) --- 306 MRM_C3 = 35, 307 MRM_C4 = 36, 308 MRM_C8 = 37, 309 MRM_C9 = 38, 310 MRM_E8 = 39, 311 MRM_F0 = 40, 312 MRM_F8 = 41, 313 MRM_F9 = 42, |
| 314 315 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 316 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 317 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 318 /// manual, this operand is described as pntr16:32 and pntr16:16 319 RawFrmImm16 = 43, |
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| 314 315 FormMask = 63, 316 317 //===------------------------------------------------------------------===// 318 // Actual flags... 319 320 // OpSize - Set if this instruction requires an operand size prefix (0x66), 321 // which most often indicates that the instruction operates on 16 bit data --- 112 unchanged lines hidden (view full) --- 434 // 0 in bits 22-23 means normal, non-SSE instruction. 435 SSEDomainShift = 22, 436 437 OpcodeShift = 24, 438 OpcodeMask = 0xFF << OpcodeShift, 439 440 //===------------------------------------------------------------------===// 441 // VEX - The opcode prefix used by AVX instructions | 320 321 FormMask = 63, 322 323 //===------------------------------------------------------------------===// 324 // Actual flags... 325 326 // OpSize - Set if this instruction requires an operand size prefix (0x66), 327 // which most often indicates that the instruction operates on 16 bit data --- 112 unchanged lines hidden (view full) --- 440 // 0 in bits 22-23 means normal, non-SSE instruction. 441 SSEDomainShift = 22, 442 443 OpcodeShift = 24, 444 OpcodeMask = 0xFF << OpcodeShift, 445 446 //===------------------------------------------------------------------===// 447 // VEX - The opcode prefix used by AVX instructions |
| 442 VEX = 1ULL << 32, | 448 VEX = 1U << 0, |
| 443 444 // VEX_W - Has a opcode specific functionality, but is used in the same 445 // way as REX_W is for regular SSE instructions. | 449 450 // VEX_W - Has a opcode specific functionality, but is used in the same 451 // way as REX_W is for regular SSE instructions. |
| 446 VEX_W = 1ULL << 33, | 452 VEX_W = 1U << 1, |
| 447 448 // VEX_4V - Used to specify an additional AVX/SSE register. Several 2 449 // address instructions in SSE are represented as 3 address ones in AVX 450 // and the additional register is encoded in VEX_VVVV prefix. | 453 454 // VEX_4V - Used to specify an additional AVX/SSE register. Several 2 455 // address instructions in SSE are represented as 3 address ones in AVX 456 // and the additional register is encoded in VEX_VVVV prefix. |
| 451 VEX_4V = 1ULL << 34, | 457 VEX_4V = 1U << 2, |
| 452 453 // VEX_I8IMM - Specifies that the last register used in a AVX instruction, 454 // must be encoded in the i8 immediate field. This usually happens in 455 // instructions with 4 operands. | 458 459 // VEX_I8IMM - Specifies that the last register used in a AVX instruction, 460 // must be encoded in the i8 immediate field. This usually happens in 461 // instructions with 4 operands. |
| 456 VEX_I8IMM = 1ULL << 35, | 462 VEX_I8IMM = 1U << 3, |
| 457 458 // VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 459 // instruction uses 256-bit wide registers. This is usually auto detected if 460 // a VR256 register is used, but some AVX instructions also have this field 461 // marked when using a f256 memory references. | 463 464 // VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 465 // instruction uses 256-bit wide registers. This is usually auto detected if 466 // a VR256 register is used, but some AVX instructions also have this field 467 // marked when using a f256 memory references. |
| 462 VEX_L = 1ULL << 36 | 468 VEX_L = 1U << 4 |
| 463 }; 464 465 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 466 // specified machine instruction. 467 // 468 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 469 return TSFlags >> X86II::OpcodeShift; 470 } --- 46 unchanged lines hidden (view full) --- 517 switch (TSFlags & X86II::FormMask) { 518 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); 519 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); 520 case X86II::Pseudo: 521 case X86II::RawFrm: 522 case X86II::AddRegFrm: 523 case X86II::MRMDestReg: 524 case X86II::MRMSrcReg: | 469 }; 470 471 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the 472 // specified machine instruction. 473 // 474 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { 475 return TSFlags >> X86II::OpcodeShift; 476 } --- 46 unchanged lines hidden (view full) --- 523 switch (TSFlags & X86II::FormMask) { 524 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this form"); 525 default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!"); 526 case X86II::Pseudo: 527 case X86II::RawFrm: 528 case X86II::AddRegFrm: 529 case X86II::MRMDestReg: 530 case X86II::MRMSrcReg: |
| 531 case X86II::RawFrmImm16: |
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| 525 return -1; 526 case X86II::MRMDestMem: 527 return 0; 528 case X86II::MRMSrcMem: { | 532 return -1; 533 case X86II::MRMDestMem: 534 return 0; 535 case X86II::MRMSrcMem: { |
| 529 bool HasVEX_4V = TSFlags & X86II::VEX_4V; | 536 bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V; |
| 530 unsigned FirstMemOp = 1; 531 if (HasVEX_4V) 532 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 533 534 // FIXME: Maybe lea should have its own form? This is a horrible hack. 535 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 536 // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 537 return FirstMemOp; --- 67 unchanged lines hidden (view full) --- 605 explicit X86InstrInfo(X86TargetMachine &tm); 606 607 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 608 /// such, whenever a client has an instance of instruction info, it should 609 /// always be able to get register info as well (through this method). 610 /// 611 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 612 | 537 unsigned FirstMemOp = 1; 538 if (HasVEX_4V) 539 ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV). 540 541 // FIXME: Maybe lea should have its own form? This is a horrible hack. 542 //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 543 // Opcode == X86::LEA16r || Opcode == X86::LEA32r) 544 return FirstMemOp; --- 67 unchanged lines hidden (view full) --- 612 explicit X86InstrInfo(X86TargetMachine &tm); 613 614 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 615 /// such, whenever a client has an instance of instruction info, it should 616 /// always be able to get register info as well (through this method). 617 /// 618 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } 619 |
| 613 /// Return true if the instruction is a register to register move and return 614 /// the source and dest operands and their sub-register indices by reference. 615 virtual bool isMoveInstr(const MachineInstr &MI, 616 unsigned &SrcReg, unsigned &DstReg, 617 unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 618 | |
| 619 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 620 /// extension instruction. That is, it's like a copy where it's legal for the 621 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 622 /// true, then it's expected the pre-extension value is available as a subreg 623 /// of the result register. This also returns the sub-register index in 624 /// SubIdx. 625 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 626 unsigned &SrcReg, unsigned &DstReg, --- 194 unchanged lines hidden (view full) --- 821 return (reg == X86::SPL || reg == X86::BPL || 822 reg == X86::SIL || reg == X86::DIL); 823 } 824 825 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 826 if (!MO.isReg()) return false; 827 return isX86_64ExtendedReg(MO.getReg()); 828 } | 620 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 621 /// extension instruction. That is, it's like a copy where it's legal for the 622 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 623 /// true, then it's expected the pre-extension value is available as a subreg 624 /// of the result register. This also returns the sub-register index in 625 /// SubIdx. 626 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 627 unsigned &SrcReg, unsigned &DstReg, --- 194 unchanged lines hidden (view full) --- 822 return (reg == X86::SPL || reg == X86::BPL || 823 reg == X86::SIL || reg == X86::DIL); 824 } 825 826 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 827 if (!MO.isReg()) return false; 828 return isX86_64ExtendedReg(MO.getReg()); 829 } |
| 829 static unsigned determineREX(const MachineInstr &MI); | |
| 830 831 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 832 /// higher) register? e.g. r8, xmm8, xmm13, etc. 833 static bool isX86_64ExtendedReg(unsigned RegNo); 834 | 830 831 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or 832 /// higher) register? e.g. r8, xmm8, xmm13, etc. 833 static bool isX86_64ExtendedReg(unsigned RegNo); 834 |
| 835 /// GetInstSize - Returns the size of the specified MachineInstr. 836 /// 837 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 838 | |
| 839 /// getGlobalBaseReg - Return a virtual register initialized with the 840 /// the global base register value. Output instructions required to 841 /// initialize the register in the function entry block, if necessary. 842 /// 843 unsigned getGlobalBaseReg(MachineFunction *MF) const; 844 845 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 846 /// and a bitmask of possible arguments to SetSSEDomain ase the second. --- 26 unchanged lines hidden --- | 835 /// getGlobalBaseReg - Return a virtual register initialized with the 836 /// the global base register value. Output instructions required to 837 /// initialize the register in the function entry block, if necessary. 838 /// 839 unsigned getGlobalBaseReg(MachineFunction *MF) const; 840 841 /// GetSSEDomain - Return the SSE execution domain of MI as the first element, 842 /// and a bitmask of possible arguments to SetSSEDomain ase the second. --- 26 unchanged lines hidden --- |