| PPCScheduleG4Plus.td (225736) | PPCScheduleG4Plus.td (235633) |
|---|---|
| 1//===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===// 2// | 1//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===// 2// |
| 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. | 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. |
| 7// | 7// |
| 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the G4+ (7450) processor. 11// 12//===----------------------------------------------------------------------===// 13 14def IU3 : FuncUnit; // integer unit 3 (7450 simple) 15def IU4 : FuncUnit; // integer unit 4 (7450 simple) --- 13 unchanged lines hidden (view full) --- 29 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 30 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 31 InstrItinData<BrB , [InstrStage<1, [BPU]>]>, 32 InstrItinData<BrCR , [InstrStage<2, [IU2]>]>, 33 InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>, 34 InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>, 35 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, 36 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, | 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the G4+ (7450) processor. 11// 12//===----------------------------------------------------------------------===// 13 14def IU3 : FuncUnit; // integer unit 3 (7450 simple) 15def IU4 : FuncUnit; // integer unit 4 (7450 simple) --- 13 unchanged lines hidden (view full) --- 29 InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 30 InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, 31 InstrItinData<BrB , [InstrStage<1, [BPU]>]>, 32 InstrItinData<BrCR , [InstrStage<2, [IU2]>]>, 33 InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>, 34 InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>, 35 InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, 36 InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, |
| 37 InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>, | 37 InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>, 38 InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>, |
| 38 InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>, 39 InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>, 40 InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>, 41 InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>, 42 InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>, 43 InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>, 44 InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>, 45 InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, --- 35 unchanged lines hidden --- | 39 InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>, 40 InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>, 41 InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>, 42 InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>, 43 InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>, 44 InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>, 45 InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>, 46 InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, --- 35 unchanged lines hidden --- |