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itanium1.md (132718) itanium1.md (169689)
1;; Itanium1 (original Itanium) DFA descriptions for insn scheduling
2;; and bundling.
1;; Itanium1 (original Itanium) DFA descriptions for insn scheduling
2;; and bundling.
3;; Copyright (C) 2002 Free Software Foundation, Inc.
3;; Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
4;; Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5;;
6;; This file is part of GCC.
7;;
8;; GCC is free software; you can redistribute it and/or modify
9;; it under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 2, or (at your option)
11;; any later version.
12;;
13;; GCC is distributed in the hope that it will be useful,
14;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16;; GNU General Public License for more details.
17;;
18;; You should have received a copy of the GNU General Public License
19;; along with GCC; see the file COPYING. If not, write to
4;; Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5;;
6;; This file is part of GCC.
7;;
8;; GCC is free software; you can redistribute it and/or modify
9;; it under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 2, or (at your option)
11;; any later version.
12;;
13;; GCC is distributed in the hope that it will be useful,
14;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16;; GNU General Public License for more details.
17;;
18;; You should have received a copy of the GNU General Public License
19;; along with GCC; see the file COPYING. If not, write to
20;; the Free Software Foundation, 59 Temple Place - Suite 330,
21;; Boston, MA 02111-1307, USA. */
20;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21;; Boston, MA 02110-1301, USA. */
22;;
23
24
25/* This is description of pipeline hazards based on DFA. The
26 following constructions can be used for this:
27
28 o define_cpu_unit string [string]) describes a cpu functional unit
29 (separated by comma).
30
31 1st operand: Names of cpu function units.
32 2nd operand: Name of automaton (see comments for
33 DEFINE_AUTOMATON).
34
35 All define_reservations and define_cpu_units should have unique
22;;
23
24
25/* This is description of pipeline hazards based on DFA. The
26 following constructions can be used for this:
27
28 o define_cpu_unit string [string]) describes a cpu functional unit
29 (separated by comma).
30
31 1st operand: Names of cpu function units.
32 2nd operand: Name of automaton (see comments for
33 DEFINE_AUTOMATON).
34
35 All define_reservations and define_cpu_units should have unique
36 names which can not be "nothing".
36 names which cannot be "nothing".
37
38 o (exclusion_set string string) means that each CPU function unit
37
38 o (exclusion_set string string) means that each CPU function unit
39 in the first string can not be reserved simultaneously with each
39 in the first string cannot be reserved simultaneously with each
40 unit whose name is in the second string and vise versa. CPU
41 units in the string are separated by commas. For example, it is
42 useful for description CPU with fully pipelined floating point
43 functional unit which can execute simultaneously only single
44 floating point insns or only double floating point insns.
45
46 o (presence_set string string) means that each CPU function unit in
40 unit whose name is in the second string and vise versa. CPU
41 units in the string are separated by commas. For example, it is
42 useful for description CPU with fully pipelined floating point
43 functional unit which can execute simultaneously only single
44 floating point insns or only double floating point insns.
45
46 o (presence_set string string) means that each CPU function unit in
47 the first string can not be reserved unless at least one of
47 the first string cannot be reserved unless at least one of
48 pattern of units whose names are in the second string is
49 reserved. This is an asymmetric relation. CPU units or unit
50 patterns in the strings are separated by commas. Pattern is one
51 unit name or unit names separated by white-spaces.
52
53 For example, it is useful for description that slot1 is reserved
54 after slot0 reservation for a VLIW processor. We could describe
55 it by the following construction

--- 31 unchanged lines hidden (view full) ---

87 o (absence_set string string) means that each CPU function unit in
88 the first string can be reserved only if each pattern of units
89 whose names are in the second string is not reserved. This is an
90 asymmetric relation (actually exclusion set is analogous to this
91 one but it is symmetric). CPU units or unit patterns in the
92 string are separated by commas. Pattern is one unit name or unit
93 names separated by white-spaces.
94
48 pattern of units whose names are in the second string is
49 reserved. This is an asymmetric relation. CPU units or unit
50 patterns in the strings are separated by commas. Pattern is one
51 unit name or unit names separated by white-spaces.
52
53 For example, it is useful for description that slot1 is reserved
54 after slot0 reservation for a VLIW processor. We could describe
55 it by the following construction

--- 31 unchanged lines hidden (view full) ---

87 o (absence_set string string) means that each CPU function unit in
88 the first string can be reserved only if each pattern of units
89 whose names are in the second string is not reserved. This is an
90 asymmetric relation (actually exclusion set is analogous to this
91 one but it is symmetric). CPU units or unit patterns in the
92 string are separated by commas. Pattern is one unit name or unit
93 names separated by white-spaces.
94
95 For example, it is useful for description that slot0 can not be
95 For example, it is useful for description that slot0 cannot be
96 reserved after slot1 or slot2 reservation for a VLIW processor.
97 We could describe it by the following construction
98
99 (absence_set "slot2" "slot0, slot1")
100
96 reserved after slot1 or slot2 reservation for a VLIW processor.
97 We could describe it by the following construction
98
99 (absence_set "slot2" "slot0, slot1")
100
101 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
101 Or slot2 cannot be reserved if slot0 and unit b0 are reserved or
102 slot1 and unit b1 are reserved . In this case we could write
103
104 (absence_set "slot2" "slot0 b0, slot1 b1")
105
106 All CPU functional units in a set should to belong the same
107 automaton.
108
109 o (final_absence_set string string) is analogous to `absence_set' but

--- 25 unchanged lines hidden (view full) ---

135 by insns.
136
137 o (define_reservation string string) names reservation (the first
138 string) of cpu functional units (the 2nd string). Sometimes unit
139 reservations for different insns contain common parts. In such
140 case, you describe common part and use one its name (the 1st
141 parameter) in regular expression in define_insn_reservation. All
142 define_reservations, define results and define_cpu_units should
102 slot1 and unit b1 are reserved . In this case we could write
103
104 (absence_set "slot2" "slot0 b0, slot1 b1")
105
106 All CPU functional units in a set should to belong the same
107 automaton.
108
109 o (final_absence_set string string) is analogous to `absence_set' but

--- 25 unchanged lines hidden (view full) ---

135 by insns.
136
137 o (define_reservation string string) names reservation (the first
138 string) of cpu functional units (the 2nd string). Sometimes unit
139 reservations for different insns contain common parts. In such
140 case, you describe common part and use one its name (the 1st
141 parameter) in regular expression in define_insn_reservation. All
142 define_reservations, define results and define_cpu_units should
143 have unique names which can not be "nothing".
143 have unique names which cannot be "nothing".
144
145 o (define_insn_reservation name default_latency condition regexpr)
146 describes reservation of cpu functional units (the 3nd operand)
147 for instruction which is selected by the condition (the 2nd
148 parameter). The first parameter is used for output of debugging
149 information. The reservations are described by a regular
150 expression according the following syntax:
151

--- 368 unchanged lines hidden (view full) ---

520 (and (and (eq_attr "cpu" "itanium")
521 (eq_attr "itanium_class" "fcmp"))
522 (eq (symbol_ref "bundling_p") (const_int 0)))
523 "1_F+1_not_uf1")
524(define_insn_reservation "1_fcvtfx" 7
525 (and (and (eq_attr "cpu" "itanium")
526 (eq_attr "itanium_class" "fcvtfx"))
527 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
144
145 o (define_insn_reservation name default_latency condition regexpr)
146 describes reservation of cpu functional units (the 3nd operand)
147 for instruction which is selected by the condition (the 2nd
148 parameter). The first parameter is used for output of debugging
149 information. The reservations are described by a regular
150 expression according the following syntax:
151

--- 368 unchanged lines hidden (view full) ---

520 (and (and (eq_attr "cpu" "itanium")
521 (eq_attr "itanium_class" "fcmp"))
522 (eq (symbol_ref "bundling_p") (const_int 0)))
523 "1_F+1_not_uf1")
524(define_insn_reservation "1_fcvtfx" 7
525 (and (and (eq_attr "cpu" "itanium")
526 (eq_attr "itanium_class" "fcvtfx"))
527 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
528
528(define_insn_reservation "1_fld" 9
529(define_insn_reservation "1_fld" 9
529 (and (and (eq_attr "cpu" "itanium")
530 (eq_attr "itanium_class" "fld"))
530 (and (and (and (eq_attr "cpu" "itanium")
531 (eq_attr "itanium_class" "fld"))
532 (eq_attr "check_load" "no"))
531 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
533 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
534(define_insn_reservation "1_fldc" 0
535 (and (and (and (eq_attr "cpu" "itanium")
536 (eq_attr "itanium_class" "fld"))
537 (eq_attr "check_load" "yes"))
538 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
539
540(define_insn_reservation "1_fldp" 9
541 (and (and (and (eq_attr "cpu" "itanium")
542 (eq_attr "itanium_class" "fldp"))
543 (eq_attr "check_load" "no"))
544 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
545(define_insn_reservation "1_fldpc" 0
546 (and (and (and (eq_attr "cpu" "itanium")
547 (eq_attr "itanium_class" "fldp"))
548 (eq_attr "check_load" "yes"))
549 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
550
532(define_insn_reservation "1_fmac" 5
533 (and (and (eq_attr "cpu" "itanium")
534 (eq_attr "itanium_class" "fmac"))
535 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
536(define_insn_reservation "1_fmisc" 5
537 (and (and (eq_attr "cpu" "itanium")
538 (eq_attr "itanium_class" "fmisc"))
539 (eq (symbol_ref "bundling_p") (const_int 0)))

--- 44 unchanged lines hidden (view full) ---

584(define_insn_reservation "1_icmp" 1
585 (and (and (eq_attr "cpu" "itanium")
586 (eq_attr "itanium_class" "icmp"))
587 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
588(define_insn_reservation "1_ilog" 1
589 (and (and (eq_attr "cpu" "itanium")
590 (eq_attr "itanium_class" "ilog"))
591 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
551(define_insn_reservation "1_fmac" 5
552 (and (and (eq_attr "cpu" "itanium")
553 (eq_attr "itanium_class" "fmac"))
554 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
555(define_insn_reservation "1_fmisc" 5
556 (and (and (eq_attr "cpu" "itanium")
557 (eq_attr "itanium_class" "fmisc"))
558 (eq (symbol_ref "bundling_p") (const_int 0)))

--- 44 unchanged lines hidden (view full) ---

603(define_insn_reservation "1_icmp" 1
604 (and (and (eq_attr "cpu" "itanium")
605 (eq_attr "itanium_class" "icmp"))
606 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
607(define_insn_reservation "1_ilog" 1
608 (and (and (eq_attr "cpu" "itanium")
609 (eq_attr "itanium_class" "ilog"))
610 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
611(define_insn_reservation "1_mmalua" 2
612 (and (and (eq_attr "cpu" "itanium")
613 (eq_attr "itanium_class" "mmalua"))
614 (eq (symbol_ref "bundling_p") (const_int 0)))
615 "1_A")
592(define_insn_reservation "1_ishf" 1
593 (and (and (eq_attr "cpu" "itanium")
594 (eq_attr "itanium_class" "ishf"))
595 (eq (symbol_ref "bundling_p") (const_int 0)))
596 "1_I+1_not_ui1")
597(define_insn_reservation "1_ld" 2
616(define_insn_reservation "1_ishf" 1
617 (and (and (eq_attr "cpu" "itanium")
618 (eq_attr "itanium_class" "ishf"))
619 (eq (symbol_ref "bundling_p") (const_int 0)))
620 "1_I+1_not_ui1")
621(define_insn_reservation "1_ld" 2
598 (and (and (eq_attr "cpu" "itanium")
599 (eq_attr "itanium_class" "ld"))
622 (and (and (and (eq_attr "cpu" "itanium")
623 (eq_attr "itanium_class" "ld"))
624 (eq_attr "check_load" "no"))
600 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
625 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
626(define_insn_reservation "1_ldc" 0
627 (and (and (and (eq_attr "cpu" "itanium")
628 (eq_attr "itanium_class" "ld"))
629 (eq_attr "check_load" "yes"))
630 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
601(define_insn_reservation "1_long_i" 1
602 (and (and (eq_attr "cpu" "itanium")
603 (eq_attr "itanium_class" "long_i"))
604 (eq (symbol_ref "bundling_p") (const_int 0))) "1_L")
605(define_insn_reservation "1_mmmul" 2
606 (and (and (eq_attr "cpu" "itanium")
607 (eq_attr "itanium_class" "mmmul"))
608 (eq (symbol_ref "bundling_p") (const_int 0)))

--- 73 unchanged lines hidden (view full) ---

682 (and (and (eq_attr "cpu" "itanium")
683 (eq_attr "itanium_class" "xmpy"))
684 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
685(define_insn_reservation "1_xtd" 1
686 (and (and (eq_attr "cpu" "itanium")
687 (eq_attr "itanium_class" "xtd"))
688 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
689
631(define_insn_reservation "1_long_i" 1
632 (and (and (eq_attr "cpu" "itanium")
633 (eq_attr "itanium_class" "long_i"))
634 (eq (symbol_ref "bundling_p") (const_int 0))) "1_L")
635(define_insn_reservation "1_mmmul" 2
636 (and (and (eq_attr "cpu" "itanium")
637 (eq_attr "itanium_class" "mmmul"))
638 (eq (symbol_ref "bundling_p") (const_int 0)))

--- 73 unchanged lines hidden (view full) ---

712 (and (and (eq_attr "cpu" "itanium")
713 (eq_attr "itanium_class" "xmpy"))
714 (eq (symbol_ref "bundling_p") (const_int 0))) "1_F")
715(define_insn_reservation "1_xtd" 1
716 (and (and (eq_attr "cpu" "itanium")
717 (eq_attr "itanium_class" "xtd"))
718 (eq (symbol_ref "bundling_p") (const_int 0))) "1_I")
719
690(define_insn_reservation "1_chk_s" 0
720(define_insn_reservation "1_chk_s_i" 0
691 (and (and (eq_attr "cpu" "itanium")
721 (and (and (eq_attr "cpu" "itanium")
692 (eq_attr "itanium_class" "chk_s"))
722 (eq_attr "itanium_class" "chk_s_i"))
693 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
723 (eq (symbol_ref "bundling_p") (const_int 0))) "1_A")
724(define_insn_reservation "1_chk_s_f" 0
725 (and (and (eq_attr "cpu" "itanium")
726 (eq_attr "itanium_class" "chk_s_f"))
727 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
728(define_insn_reservation "1_chk_a" 0
729 (and (and (eq_attr "cpu" "itanium")
730 (eq_attr "itanium_class" "chk_a"))
731 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
732
694(define_insn_reservation "1_lfetch" 0
695 (and (and (eq_attr "cpu" "itanium")
696 (eq_attr "itanium_class" "lfetch"))
697 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
698
699(define_insn_reservation "1_nop_m" 0
700 (and (and (eq_attr "cpu" "itanium")
701 (eq_attr "itanium_class" "nop_m"))

--- 213 unchanged lines hidden (view full) ---

915(define_bypass 3 "1_frbr" "1_mmmul,1_mmshf")
916(define_bypass 14 "1_frar_i" "1_mmmul,1_mmshf")
917(define_bypass 7 "1_frar_m" "1_mmmul,1_mmshf")
918
919;; ????
920;; There is only one insn `mov ar.pfs =' for toar_i.
921(define_bypass 0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall")
922
733(define_insn_reservation "1_lfetch" 0
734 (and (and (eq_attr "cpu" "itanium")
735 (eq_attr "itanium_class" "lfetch"))
736 (eq (symbol_ref "bundling_p") (const_int 0))) "1_M")
737
738(define_insn_reservation "1_nop_m" 0
739 (and (and (eq_attr "cpu" "itanium")
740 (eq_attr "itanium_class" "nop_m"))

--- 213 unchanged lines hidden (view full) ---

954(define_bypass 3 "1_frbr" "1_mmmul,1_mmshf")
955(define_bypass 14 "1_frar_i" "1_mmmul,1_mmshf")
956(define_bypass 7 "1_frar_m" "1_mmmul,1_mmshf")
957
958;; ????
959;; There is only one insn `mov ar.pfs =' for toar_i.
960(define_bypass 0 "1_tobr,1_topr,1_toar_i" "1_br,1_scall")
961
923(define_bypass 3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf")
962(define_bypass 3 "1_ialu,1_ialu_addr" "1_mmmul,1_mmshf,1_mmalua")
924;; ??? howto describe ialu for I slot only. We use ialu_addr for that
925;;(define_bypass 2 "1_ialu" "1_ld" "ia64_ld_address_bypass_p")
926;; ??? howto describe ialu st/address for I slot only. We use ialu_addr
927;; for that.
928;;(define_bypass 2 "1_ialu" "1_st" "ia64_st_address_bypass_p")
929
930(define_bypass 0 "1_icmp" "1_br,1_scall")
931
932(define_bypass 3 "1_ilog" "1_mmmul,1_mmshf")
933
934(define_bypass 2 "1_ilog,1_xtd" "1_ld" "ia64_ld_address_bypass_p")
935(define_bypass 2 "1_ilog,1_xtd" "1_st" "ia64_st_address_bypass_p")
936
963;; ??? howto describe ialu for I slot only. We use ialu_addr for that
964;;(define_bypass 2 "1_ialu" "1_ld" "ia64_ld_address_bypass_p")
965;; ??? howto describe ialu st/address for I slot only. We use ialu_addr
966;; for that.
967;;(define_bypass 2 "1_ialu" "1_st" "ia64_st_address_bypass_p")
968
969(define_bypass 0 "1_icmp" "1_br,1_scall")
970
971(define_bypass 3 "1_ilog" "1_mmmul,1_mmshf")
972
973(define_bypass 2 "1_ilog,1_xtd" "1_ld" "ia64_ld_address_bypass_p")
974(define_bypass 2 "1_ilog,1_xtd" "1_st" "ia64_st_address_bypass_p")
975
937(define_bypass 3 "1_ld" "1_mmmul,1_mmshf")
976(define_bypass 3 "1_ld,1_ldc" "1_mmmul,1_mmshf")
938(define_bypass 3 "1_ld" "1_ld" "ia64_ld_address_bypass_p")
939(define_bypass 3 "1_ld" "1_st" "ia64_st_address_bypass_p")
940
941;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4,
942;; but HP engineers say any non-MM operation.
977(define_bypass 3 "1_ld" "1_ld" "ia64_ld_address_bypass_p")
978(define_bypass 3 "1_ld" "1_st" "ia64_st_address_bypass_p")
979
980;; Intel docs say only LD, ST, IALU, ILOG, ISHF consumers have latency 4,
981;; but HP engineers say any non-MM operation.
943(define_bypass 4 "1_mmmul,1_mmshf"
944 "1_br,1_fcmp,1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
945 1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_chk_s,\
982(define_bypass 4 "1_mmmul,1_mmshf,1_mmalua"
983 "1_br,1_fcmp,1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
984 1_frbr,1_frfr,1_frpr,1_ialu,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,1_chk_s_i,1_chk_s_f,1_chk_a,\
946 1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\
947 1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd")
948
949;; ??? how to describe that if scheduled < 4 cycle then latency is 10 cycles.
950;; (define_bypass 10 "1_mmmul,1_mmshf" "1_ialu,1_ilog,1_ishf,1_st,1_ld")
951
952(define_bypass 0 "1_tbit" "1_br,1_scall")
953
954(define_bypass 8 "1_tofr" "1_frfr,1_stf")
955(define_bypass 7 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_frfr")
956(define_bypass 8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_stf")
957
958;; We don't use here fcmp because scall may be predicated.
985 1_long_i,1_rse_m,1_sem,1_stf,1_st,1_syst_m0,1_syst_m,\
986 1_tbit,1_toar_i,1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd")
987
988;; ??? how to describe that if scheduled < 4 cycle then latency is 10 cycles.
989;; (define_bypass 10 "1_mmmul,1_mmshf" "1_ialu,1_ilog,1_ishf,1_st,1_ld")
990
991(define_bypass 0 "1_tbit" "1_br,1_scall")
992
993(define_bypass 8 "1_tofr" "1_frfr,1_stf")
994(define_bypass 7 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_frfr")
995(define_bypass 8 "1_fmisc,1_fcvtfx,1_fmac,1_xmpy" "1_stf")
996
997;; We don't use here fcmp because scall may be predicated.
959(define_bypass 0 "1_fcvtfx,1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
998(define_bypass 0 "1_fcvtfx,1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,\
960 1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\
999 1_frbr,1_frfr,1_frpr,1_ialu,1_ialu_addr,1_ilog,1_ishf,\
961 1_ld,1_long_i,1_mmmul,1_mmshf,1_mmshfi,1_toar_m,1_tofr,\
962 1_xmpy,1_xtd" "1_scall")
1000 1_ld,1_ldc,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,\
1001 1_toar_m,1_tofr,1_xmpy,1_xtd" "1_scall")
963
964(define_bypass 0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\
1002
1003(define_bypass 0 "1_unknown,1_ignore,1_stop_bit,1_br,1_fcmp,1_fcvtfx,\
965 1_fld,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\
966 1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,\
967 1_chk_s,1_long_i,1_mmmul,1_mmshf,1_mmshfi,1_nop,\
1004 1_fld,1_fldc,1_fmac,1_fmisc,1_frar_i,1_frar_m,1_frbr,1_frfr,\
1005 1_frpr,1_ialu,1_ialu_addr,1_icmp,1_ilog,1_ishf,1_ld,1_ldc,\
1006 1_chk_s_i,1_chk_s_f,1_chk_a,1_long_i,1_mmalua,1_mmmul,1_mmshf,1_mmshfi,1_nop,\
968 1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\
969 1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\
970 1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch"
971 "1_ignore")
972
973
974;; Bundling
975

--- 417 unchanged lines hidden (view full) ---

1393 (and (and (eq_attr "cpu" "itanium")
1394 (eq_attr "itanium_class" "fcmp"))
1395 (ne (symbol_ref "bundling_p") (const_int 0)))
1396 "1b_F+1b_not_uf1")
1397(define_insn_reservation "1b_fcvtfx" 7
1398 (and (and (eq_attr "cpu" "itanium")
1399 (eq_attr "itanium_class" "fcvtfx"))
1400 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1007 1_nop_b,1_nop_f,1_nop_i,1_nop_m,1_nop_x,1_rse_m,1_scall,\
1008 1_sem,1_stf,1_st,1_syst_m0,1_syst_m,1_tbit,1_toar_i,\
1009 1_toar_m,1_tobr,1_tofr,1_topr,1_xmpy,1_xtd,1_lfetch"
1010 "1_ignore")
1011
1012
1013;; Bundling
1014

--- 417 unchanged lines hidden (view full) ---

1432 (and (and (eq_attr "cpu" "itanium")
1433 (eq_attr "itanium_class" "fcmp"))
1434 (ne (symbol_ref "bundling_p") (const_int 0)))
1435 "1b_F+1b_not_uf1")
1436(define_insn_reservation "1b_fcvtfx" 7
1437 (and (and (eq_attr "cpu" "itanium")
1438 (eq_attr "itanium_class" "fcvtfx"))
1439 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1440
1401(define_insn_reservation "1b_fld" 9
1441(define_insn_reservation "1b_fld" 9
1402 (and (and (eq_attr "cpu" "itanium")
1403 (eq_attr "itanium_class" "fld"))
1442 (and (and (and (eq_attr "cpu" "itanium")
1443 (eq_attr "itanium_class" "fld"))
1444 (eq_attr "check_load" "no"))
1404 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1445 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1446(define_insn_reservation "1b_fldc" 0
1447 (and (and (and (eq_attr "cpu" "itanium")
1448 (eq_attr "itanium_class" "fld"))
1449 (eq_attr "check_load" "yes"))
1450 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1451
1452(define_insn_reservation "1b_fldp" 9
1453 (and (and (and (eq_attr "cpu" "itanium")
1454 (eq_attr "itanium_class" "fldp"))
1455 (eq_attr "check_load" "no"))
1456 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1457(define_insn_reservation "1b_fldpc" 0
1458 (and (and (and (eq_attr "cpu" "itanium")
1459 (eq_attr "itanium_class" "fldp"))
1460 (eq_attr "check_load" "yes"))
1461 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1462
1405(define_insn_reservation "1b_fmac" 5
1406 (and (and (eq_attr "cpu" "itanium")
1407 (eq_attr "itanium_class" "fmac"))
1408 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1409(define_insn_reservation "1b_fmisc" 5
1410 (and (and (eq_attr "cpu" "itanium")
1411 (eq_attr "itanium_class" "fmisc"))
1412 (ne (symbol_ref "bundling_p") (const_int 0)))

--- 40 unchanged lines hidden (view full) ---

1453(define_insn_reservation "1b_icmp" 1
1454 (and (and (eq_attr "cpu" "itanium")
1455 (eq_attr "itanium_class" "icmp"))
1456 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1457(define_insn_reservation "1b_ilog" 1
1458 (and (and (eq_attr "cpu" "itanium")
1459 (eq_attr "itanium_class" "ilog"))
1460 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1463(define_insn_reservation "1b_fmac" 5
1464 (and (and (eq_attr "cpu" "itanium")
1465 (eq_attr "itanium_class" "fmac"))
1466 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1467(define_insn_reservation "1b_fmisc" 5
1468 (and (and (eq_attr "cpu" "itanium")
1469 (eq_attr "itanium_class" "fmisc"))
1470 (ne (symbol_ref "bundling_p") (const_int 0)))

--- 40 unchanged lines hidden (view full) ---

1511(define_insn_reservation "1b_icmp" 1
1512 (and (and (eq_attr "cpu" "itanium")
1513 (eq_attr "itanium_class" "icmp"))
1514 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1515(define_insn_reservation "1b_ilog" 1
1516 (and (and (eq_attr "cpu" "itanium")
1517 (eq_attr "itanium_class" "ilog"))
1518 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1519(define_insn_reservation "1b_mmalua" 2
1520 (and (and (eq_attr "cpu" "itanium")
1521 (eq_attr "itanium_class" "mmalua"))
1522 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1461(define_insn_reservation "1b_ishf" 1
1462 (and (and (eq_attr "cpu" "itanium")
1463 (eq_attr "itanium_class" "ishf"))
1464 (ne (symbol_ref "bundling_p") (const_int 0)))
1465 "1b_I+1b_not_ui1")
1523(define_insn_reservation "1b_ishf" 1
1524 (and (and (eq_attr "cpu" "itanium")
1525 (eq_attr "itanium_class" "ishf"))
1526 (ne (symbol_ref "bundling_p") (const_int 0)))
1527 "1b_I+1b_not_ui1")
1528
1466(define_insn_reservation "1b_ld" 2
1529(define_insn_reservation "1b_ld" 2
1467 (and (and (eq_attr "cpu" "itanium")
1468 (eq_attr "itanium_class" "ld"))
1530 (and (and (and (eq_attr "cpu" "itanium")
1531 (eq_attr "itanium_class" "ld"))
1532 (eq_attr "check_load" "no"))
1469 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1533 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1534(define_insn_reservation "1b_ldc" 0
1535 (and (and (and (eq_attr "cpu" "itanium")
1536 (eq_attr "itanium_class" "ld"))
1537 (eq_attr "check_load" "yes"))
1538 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1539
1470(define_insn_reservation "1b_long_i" 1
1471 (and (and (eq_attr "cpu" "itanium")
1472 (eq_attr "itanium_class" "long_i"))
1473 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
1474(define_insn_reservation "1b_mmmul" 2
1475 (and (and (eq_attr "cpu" "itanium")
1476 (eq_attr "itanium_class" "mmmul"))
1477 (ne (symbol_ref "bundling_p") (const_int 0)))

--- 66 unchanged lines hidden (view full) ---

1544(define_insn_reservation "1b_xmpy" 7
1545 (and (and (eq_attr "cpu" "itanium")
1546 (eq_attr "itanium_class" "xmpy"))
1547 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1548(define_insn_reservation "1b_xtd" 1
1549 (and (and (eq_attr "cpu" "itanium")
1550 (eq_attr "itanium_class" "xtd"))
1551 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
1540(define_insn_reservation "1b_long_i" 1
1541 (and (and (eq_attr "cpu" "itanium")
1542 (eq_attr "itanium_class" "long_i"))
1543 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_L")
1544(define_insn_reservation "1b_mmmul" 2
1545 (and (and (eq_attr "cpu" "itanium")
1546 (eq_attr "itanium_class" "mmmul"))
1547 (ne (symbol_ref "bundling_p") (const_int 0)))

--- 66 unchanged lines hidden (view full) ---

1614(define_insn_reservation "1b_xmpy" 7
1615 (and (and (eq_attr "cpu" "itanium")
1616 (eq_attr "itanium_class" "xmpy"))
1617 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_F")
1618(define_insn_reservation "1b_xtd" 1
1619 (and (and (eq_attr "cpu" "itanium")
1620 (eq_attr "itanium_class" "xtd"))
1621 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_I")
1552(define_insn_reservation "1b_chk_s" 0
1622
1623(define_insn_reservation "1b_chk_s_i" 0
1553 (and (and (eq_attr "cpu" "itanium")
1624 (and (and (eq_attr "cpu" "itanium")
1554 (eq_attr "itanium_class" "chk_s"))
1625 (eq_attr "itanium_class" "chk_s_i"))
1555 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1626 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_A")
1627(define_insn_reservation "1b_chk_s_f" 0
1628 (and (and (eq_attr "cpu" "itanium")
1629 (eq_attr "itanium_class" "chk_s_f"))
1630 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1631(define_insn_reservation "1b_chk_a" 0
1632 (and (and (eq_attr "cpu" "itanium")
1633 (eq_attr "itanium_class" "chk_a"))
1634 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1635
1556(define_insn_reservation "1b_lfetch" 0
1557 (and (and (eq_attr "cpu" "itanium")
1558 (eq_attr "itanium_class" "lfetch"))
1559 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1560(define_insn_reservation "1b_nop_m" 0
1561 (and (and (eq_attr "cpu" "itanium")
1562 (eq_attr "itanium_class" "nop_m"))
1563 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")

--- 53 unchanged lines hidden --- 		1636(define_insn_reservation "1b_lfetch" 0
1637 (and (and (eq_attr "cpu" "itanium")
1638 (eq_attr "itanium_class" "lfetch"))
1639 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")
1640(define_insn_reservation "1b_nop_m" 0
1641 (and (and (eq_attr "cpu" "itanium")
1642 (eq_attr "itanium_class" "nop_m"))
1643 (ne (symbol_ref "bundling_p") (const_int 0))) "1b_M")

--- 53 unchanged lines hidden ---