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bt-load.c (132718) bt-load.c (169689)
1/* Perform branch target register load optimizations.
1/* Perform branch target register load optimizations.
2 Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
2 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006
3 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 2, or (at your option) any later
9version.
10
11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING. If not, write to the Free
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to the Free
18Software Foundation, 59 Temple Place - Suite 330, Boston, MA
1902111-1307, USA. */
19Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
2002110-1301, USA. */
20
21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "tm.h"
21
22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
25#include "tm.h"
25#include "bitmap.h"
26#include "sbitmap.h"
27#include "rtl.h"
28#include "hard-reg-set.h"
26#include "rtl.h"
27#include "hard-reg-set.h"
29#include "basic-block.h"
30#include "regs.h"
28#include "regs.h"
31#include "obstack.h"
32#include "fibheap.h"
33#include "output.h"
34#include "target.h"
35#include "expr.h"
36#include "flags.h"
37#include "insn-attr.h"
38#include "function.h"
29#include "fibheap.h"
30#include "output.h"
31#include "target.h"
32#include "expr.h"
33#include "flags.h"
34#include "insn-attr.h"
35#include "function.h"
36#include "except.h"
39#include "tm_p.h"
37#include "tm_p.h"
38#include "toplev.h"
39#include "tree-pass.h"
40
41/* Target register optimizations - these are performed after reload. */
42
43typedef struct btr_def_group_s
44{
45 struct btr_def_group_s *next;
46 rtx src;
47 struct btr_def_s *members;

--- 48 unchanged lines hidden (view full) ---

96 the live range. There could be other live ranges for the same
97 branch register in that set of blocks, either in the block
98 containing the def (before the def), or in a block containing
99 a use (after the use). If there are such other live ranges, then
100 other_btr_uses_before_def or other_btr_uses_after_use must be set true
101 as appropriate. */
102 char other_btr_uses_before_def;
103 char other_btr_uses_after_use;
40
41/* Target register optimizations - these are performed after reload. */
42
43typedef struct btr_def_group_s
44{
45 struct btr_def_group_s *next;
46 rtx src;
47 struct btr_def_s *members;

--- 48 unchanged lines hidden (view full) ---

96 the live range. There could be other live ranges for the same
97 branch register in that set of blocks, either in the block
98 containing the def (before the def), or in a block containing
99 a use (after the use). If there are such other live ranges, then
100 other_btr_uses_before_def or other_btr_uses_after_use must be set true
101 as appropriate. */
102 char other_btr_uses_before_def;
103 char other_btr_uses_after_use;
104 /* We set own_end when we have moved a definition into a dominator.
105 Thus, when a later combination removes this definition again, we know
106 to clear out trs_live_at_end again. */
107 char own_end;
104 bitmap live_range;
105} *btr_def;
106
107static int issue_rate;
108
109static int basic_block_freq (basic_block);
110static int insn_sets_btr_p (rtx, int, int *);
111static rtx *find_btr_use (rtx);

--- 9 unchanged lines hidden (view full) ---

121static void compute_defs_uses_and_gen (fibheap_t, btr_def *,btr_user *,
122 sbitmap *, sbitmap *, HARD_REG_SET *);
123static void compute_kill (sbitmap *, sbitmap *, HARD_REG_SET *);
124static void compute_out (sbitmap *bb_out, sbitmap *, sbitmap *, int);
125static void link_btr_uses (btr_def *, btr_user *, sbitmap *, sbitmap *, int);
126static void build_btr_def_use_webs (fibheap_t);
127static int block_at_edge_of_live_range_p (int, btr_def);
128static void clear_btr_from_live_range (btr_def def);
108 bitmap live_range;
109} *btr_def;
110
111static int issue_rate;
112
113static int basic_block_freq (basic_block);
114static int insn_sets_btr_p (rtx, int, int *);
115static rtx *find_btr_use (rtx);

--- 9 unchanged lines hidden (view full) ---

125static void compute_defs_uses_and_gen (fibheap_t, btr_def *,btr_user *,
126 sbitmap *, sbitmap *, HARD_REG_SET *);
127static void compute_kill (sbitmap *, sbitmap *, HARD_REG_SET *);
128static void compute_out (sbitmap *bb_out, sbitmap *, sbitmap *, int);
129static void link_btr_uses (btr_def *, btr_user *, sbitmap *, sbitmap *, int);
130static void build_btr_def_use_webs (fibheap_t);
131static int block_at_edge_of_live_range_p (int, btr_def);
132static void clear_btr_from_live_range (btr_def def);
129static void add_btr_to_live_range (btr_def);
133static void add_btr_to_live_range (btr_def, int);
130static void augment_live_range (bitmap, HARD_REG_SET *, basic_block,
134static void augment_live_range (bitmap, HARD_REG_SET *, basic_block,
131 basic_block);
135 basic_block, int);
132static int choose_btr (HARD_REG_SET);
133static void combine_btr_defs (btr_def, HARD_REG_SET *);
134static void btr_def_live_range (btr_def, HARD_REG_SET *);
135static void move_btr_def (basic_block, int, btr_def, bitmap, HARD_REG_SET *);
136static int migrate_btr_def (btr_def, int);
137static void migrate_btr_defs (enum reg_class, int);
138static int can_move_up (basic_block, rtx, int);
139static void note_btr_set (rtx, rtx, void *);

--- 14 unchanged lines hidden (view full) ---

154/* An obstack to hold the def-use web data structures built up for
155 migrating branch target load instructions. */
156static struct obstack migrate_btrl_obstack;
157
158/* Array indexed by basic block number, giving the set of registers
159 live in that block. */
160static HARD_REG_SET *btrs_live;
161
136static int choose_btr (HARD_REG_SET);
137static void combine_btr_defs (btr_def, HARD_REG_SET *);
138static void btr_def_live_range (btr_def, HARD_REG_SET *);
139static void move_btr_def (basic_block, int, btr_def, bitmap, HARD_REG_SET *);
140static int migrate_btr_def (btr_def, int);
141static void migrate_btr_defs (enum reg_class, int);
142static int can_move_up (basic_block, rtx, int);
143static void note_btr_set (rtx, rtx, void *);

--- 14 unchanged lines hidden (view full) ---

158/* An obstack to hold the def-use web data structures built up for
159 migrating branch target load instructions. */
160static struct obstack migrate_btrl_obstack;
161
162/* Array indexed by basic block number, giving the set of registers
163 live in that block. */
164static HARD_REG_SET *btrs_live;
165
166/* Array indexed by basic block number, giving the set of registers live at
167 the end of that block, including any uses by a final jump insn, if any. */
168static HARD_REG_SET *btrs_live_at_end;
169
162/* Set of all target registers that we are willing to allocate. */
163static HARD_REG_SET all_btrs;
164
165/* Provide lower and upper bounds for target register numbers, so that
166 we don't need to search through all the hard registers all the time. */
167static int first_btr, last_btr;
168
169
170
170/* Set of all target registers that we are willing to allocate. */
171static HARD_REG_SET all_btrs;
172
173/* Provide lower and upper bounds for target register numbers, so that
174 we don't need to search through all the hard registers all the time. */
175static int first_btr, last_btr;
176
177
178
171/* Return an estimate of the frequency of execution of block bb.
172 If we have a profiling count available, we could use it here. */
179/* Return an estimate of the frequency of execution of block bb. */
173static int
174basic_block_freq (basic_block bb)
175{
176 return bb->frequency;
177}
178
179static rtx *btr_reference_found;
180

--- 5 unchanged lines hidden (view full) ---

186find_btr_reference (rtx *px, void *preg)
187{
188 rtx x;
189 int regno, i;
190
191 if (px == preg)
192 return -1;
193 x = *px;
180static int
181basic_block_freq (basic_block bb)
182{
183 return bb->frequency;
184}
185
186static rtx *btr_reference_found;
187

--- 5 unchanged lines hidden (view full) ---

193find_btr_reference (rtx *px, void *preg)
194{
195 rtx x;
196 int regno, i;
197
198 if (px == preg)
199 return -1;
200 x = *px;
194 if (GET_CODE (x) != REG)
201 if (!REG_P (x))
195 return 0;
196 regno = REGNO (x);
202 return 0;
203 regno = REGNO (x);
197 for (i = HARD_REGNO_NREGS (regno, GET_MODE (x)) - 1; i >= 0; i--)
204 for (i = hard_regno_nregs[regno][GET_MODE (x)] - 1; i >= 0; i--)
198 if (TEST_HARD_REG_BIT (all_btrs, regno+i))
199 {
200 btr_reference_found = px;
201 return 1;
202 }
203 return -1;
204}
205

--- 10 unchanged lines hidden (view full) ---

216 if CHECK_CONST is true, only return true if the source is constant.
217 If such a set is found and REGNO is nonzero, assign the register number
218 of the destination register to *REGNO. */
219static int
220insn_sets_btr_p (rtx insn, int check_const, int *regno)
221{
222 rtx set;
223
205 if (TEST_HARD_REG_BIT (all_btrs, regno+i))
206 {
207 btr_reference_found = px;
208 return 1;
209 }
210 return -1;
211}
212

--- 10 unchanged lines hidden (view full) ---

223 if CHECK_CONST is true, only return true if the source is constant.
224 If such a set is found and REGNO is nonzero, assign the register number
225 of the destination register to *REGNO. */
226static int
227insn_sets_btr_p (rtx insn, int check_const, int *regno)
228{
229 rtx set;
230
224 if (GET_CODE (insn) == INSN
231 if (NONJUMP_INSN_P (insn)
225 && (set = single_set (insn)))
226 {
227 rtx dest = SET_DEST (set);
228 rtx src = SET_SRC (set);
229
230 if (GET_CODE (dest) == SUBREG)
231 dest = XEXP (dest, 0);
232
232 && (set = single_set (insn)))
233 {
234 rtx dest = SET_DEST (set);
235 rtx src = SET_SRC (set);
236
237 if (GET_CODE (dest) == SUBREG)
238 dest = XEXP (dest, 0);
239
233 if (GET_CODE (dest) == REG
240 if (REG_P (dest)
234 && TEST_HARD_REG_BIT (all_btrs, REGNO (dest)))
235 {
241 && TEST_HARD_REG_BIT (all_btrs, REGNO (dest)))
242 {
236 if (btr_referenced_p (src, NULL))
237 abort();
243 gcc_assert (!btr_referenced_p (src, NULL));
244
238 if (!check_const || CONSTANT_P (src))
239 {
240 if (regno)
241 *regno = REGNO (dest);
242 return 1;
243 }
244 }
245 }

--- 64 unchanged lines hidden (view full) ---

310 this->next_this_bb = NULL;
311 this->next_this_group = NULL;
312 this->uses = NULL;
313 this->live_range = NULL;
314 find_btr_def_group (all_btr_def_groups, this);
315
316 fibheap_insert (all_btr_defs, -this->cost, this);
317
245 if (!check_const || CONSTANT_P (src))
246 {
247 if (regno)
248 *regno = REGNO (dest);
249 return 1;
250 }
251 }
252 }

--- 64 unchanged lines hidden (view full) ---

317 this->next_this_bb = NULL;
318 this->next_this_group = NULL;
319 this->uses = NULL;
320 this->live_range = NULL;
321 find_btr_def_group (all_btr_def_groups, this);
322
323 fibheap_insert (all_btr_defs, -this->cost, this);
324
318 if (rtl_dump_file)
319 fprintf (rtl_dump_file,
325 if (dump_file)
326 fprintf (dump_file,
320 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
321 dest_reg, bb->index, INSN_UID (insn), (this->group ? "" : ":not const"),
322 this->cost);
323
324 return this;
325}
326
327/* Create a new target register user structure, for a use in block BB,

--- 26 unchanged lines hidden (view full) ---

354 user->luid = insn_luid;
355 user->insn = insn;
356 user->use = use;
357 user->other_use_this_block = 0;
358 user->next = NULL;
359 user->n_reaching_defs = 0;
360 user->first_reaching_def = -1;
361
327 "Found target reg definition: sets %u { bb %d, insn %d }%s priority %d\n",
328 dest_reg, bb->index, INSN_UID (insn), (this->group ? "" : ":not const"),
329 this->cost);
330
331 return this;
332}
333
334/* Create a new target register user structure, for a use in block BB,

--- 26 unchanged lines hidden (view full) ---

361 user->luid = insn_luid;
362 user->insn = insn;
363 user->use = use;
364 user->other_use_this_block = 0;
365 user->next = NULL;
366 user->n_reaching_defs = 0;
367 user->first_reaching_def = -1;
368
362 if (rtl_dump_file)
369 if (dump_file)
363 {
370 {
364 fprintf (rtl_dump_file, "Uses target reg: { bb %d, insn %d }",
371 fprintf (dump_file, "Uses target reg: { bb %d, insn %d }",
365 bb->index, INSN_UID (insn));
366
367 if (user->use)
372 bb->index, INSN_UID (insn));
373
374 if (user->use)
368 fprintf (rtl_dump_file, ": unambiguous use of reg %d\n",
375 fprintf (dump_file, ": unambiguous use of reg %d\n",
369 REGNO (user->use));
370 }
371
372 return user;
373}
374
375/* Write the contents of S to the dump file. */
376static void
377dump_hard_reg_set (HARD_REG_SET s)
378{
379 int reg;
380 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
381 if (TEST_HARD_REG_BIT (s, reg))
376 REGNO (user->use));
377 }
378
379 return user;
380}
381
382/* Write the contents of S to the dump file. */
383static void
384dump_hard_reg_set (HARD_REG_SET s)
385{
386 int reg;
387 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
388 if (TEST_HARD_REG_BIT (s, reg))
382 fprintf (rtl_dump_file, " %d", reg);
389 fprintf (dump_file, " %d", reg);
383}
384
385/* Write the set of target regs live in block BB to the dump file. */
386static void
387dump_btrs_live (int bb)
388{
390}
391
392/* Write the set of target regs live in block BB to the dump file. */
393static void
394dump_btrs_live (int bb)
395{
389 fprintf (rtl_dump_file, "BB%d live:", bb);
396 fprintf (dump_file, "BB%d live:", bb);
390 dump_hard_reg_set (btrs_live[bb]);
397 dump_hard_reg_set (btrs_live[bb]);
391 fprintf (rtl_dump_file, "\n");
398 fprintf (dump_file, "\n");
392}
393
394/* REGNO is the number of a branch target register that is being used or
395 set. USERS_THIS_BB is a list of preceding branch target register users;
396 If any of them use the same register, set their other_use_this_block
397 flag. */
398static void
399note_other_use_this_block (unsigned int regno, btr_user users_this_bb)

--- 18 unchanged lines hidden (view full) ---

418 straightforward definitions. DATA points to information about the
419 current basic block that needs updating. */
420static void
421note_btr_set (rtx dest, rtx set ATTRIBUTE_UNUSED, void *data)
422{
423 defs_uses_info *info = data;
424 int regno, end_regno;
425
399}
400
401/* REGNO is the number of a branch target register that is being used or
402 set. USERS_THIS_BB is a list of preceding branch target register users;
403 If any of them use the same register, set their other_use_this_block
404 flag. */
405static void
406note_other_use_this_block (unsigned int regno, btr_user users_this_bb)

--- 18 unchanged lines hidden (view full) ---

425 straightforward definitions. DATA points to information about the
426 current basic block that needs updating. */
427static void
428note_btr_set (rtx dest, rtx set ATTRIBUTE_UNUSED, void *data)
429{
430 defs_uses_info *info = data;
431 int regno, end_regno;
432
426 if (GET_CODE (dest) != REG)
433 if (!REG_P (dest))
427 return;
428 regno = REGNO (dest);
434 return;
435 regno = REGNO (dest);
429 end_regno = regno + HARD_REGNO_NREGS (regno, GET_MODE (dest));
436 end_regno = regno + hard_regno_nregs[regno][GET_MODE (dest)];
430 for (; regno < end_regno; regno++)
431 if (TEST_HARD_REG_BIT (all_btrs, regno))
432 {
433 note_other_use_this_block (regno, info->users_this_bb);
434 SET_HARD_REG_BIT (info->btrs_written_in_block, regno);
435 SET_HARD_REG_BIT (info->btrs_live_in_block, regno);
436 sbitmap_difference (info->bb_gen, info->bb_gen,
437 info->btr_defset[regno - first_btr]);

--- 12 unchanged lines hidden (view full) ---

450 Also calculate the set of btrs ever live in that block.
451 */
452 int i;
453 int insn_luid = 0;
454 btr_def_group all_btr_def_groups = NULL;
455 defs_uses_info info;
456
457 sbitmap_vector_zero (bb_gen, n_basic_blocks);
437 for (; regno < end_regno; regno++)
438 if (TEST_HARD_REG_BIT (all_btrs, regno))
439 {
440 note_other_use_this_block (regno, info->users_this_bb);
441 SET_HARD_REG_BIT (info->btrs_written_in_block, regno);
442 SET_HARD_REG_BIT (info->btrs_live_in_block, regno);
443 sbitmap_difference (info->bb_gen, info->bb_gen,
444 info->btr_defset[regno - first_btr]);

--- 12 unchanged lines hidden (view full) ---

457 Also calculate the set of btrs ever live in that block.
458 */
459 int i;
460 int insn_luid = 0;
461 btr_def_group all_btr_def_groups = NULL;
462 defs_uses_info info;
463
464 sbitmap_vector_zero (bb_gen, n_basic_blocks);
458 for (i = 0; i < n_basic_blocks; i++)
465 for (i = NUM_FIXED_BLOCKS; i < n_basic_blocks; i++)
459 {
460 basic_block bb = BASIC_BLOCK (i);
461 int reg;
462 btr_def defs_this_bb = NULL;
463 rtx insn;
464 rtx last;
466 {
467 basic_block bb = BASIC_BLOCK (i);
468 int reg;
469 btr_def defs_this_bb = NULL;
470 rtx insn;
471 rtx last;
472 int can_throw = 0;
465
466 info.users_this_bb = NULL;
467 info.bb_gen = bb_gen[i];
468 info.btr_defset = btr_defset;
469
470 CLEAR_HARD_REG_SET (info.btrs_live_in_block);
471 CLEAR_HARD_REG_SET (info.btrs_written_in_block);
472 for (reg = first_btr; reg <= last_btr; reg++)
473 if (TEST_HARD_REG_BIT (all_btrs, reg)
473
474 info.users_this_bb = NULL;
475 info.bb_gen = bb_gen[i];
476 info.btr_defset = btr_defset;
477
478 CLEAR_HARD_REG_SET (info.btrs_live_in_block);
479 CLEAR_HARD_REG_SET (info.btrs_written_in_block);
480 for (reg = first_btr; reg <= last_btr; reg++)
481 if (TEST_HARD_REG_BIT (all_btrs, reg)
474 && REGNO_REG_SET_P (bb->global_live_at_start, reg))
482 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start, reg))
475 SET_HARD_REG_BIT (info.btrs_live_in_block, reg);
476
477 for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb));
478 insn != last;
479 insn = NEXT_INSN (insn), insn_luid++)
480 {
481 if (INSN_P (insn))
482 {

--- 13 unchanged lines hidden (view full) ---

496 sbitmap_difference (bb_gen[i], bb_gen[i],
497 btr_defset[regno - first_btr]);
498 SET_BIT (bb_gen[i], insn_uid);
499 def->next_this_bb = defs_this_bb;
500 defs_this_bb = def;
501 SET_BIT (btr_defset[regno - first_btr], insn_uid);
502 note_other_use_this_block (regno, info.users_this_bb);
503 }
483 SET_HARD_REG_BIT (info.btrs_live_in_block, reg);
484
485 for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb));
486 insn != last;
487 insn = NEXT_INSN (insn), insn_luid++)
488 {
489 if (INSN_P (insn))
490 {

--- 13 unchanged lines hidden (view full) ---

504 sbitmap_difference (bb_gen[i], bb_gen[i],
505 btr_defset[regno - first_btr]);
506 SET_BIT (bb_gen[i], insn_uid);
507 def->next_this_bb = defs_this_bb;
508 defs_this_bb = def;
509 SET_BIT (btr_defset[regno - first_btr], insn_uid);
510 note_other_use_this_block (regno, info.users_this_bb);
511 }
512 /* Check for the blockage emitted by expand_nl_goto_receiver. */
513 else if (current_function_has_nonlocal_label
514 && GET_CODE (PATTERN (insn)) == ASM_INPUT)
515 {
516 btr_user user;
517
518 /* Do the equivalent of calling note_other_use_this_block
519 for every target register. */
520 for (user = info.users_this_bb; user != NULL;
521 user = user->next)
522 if (user->use)
523 user->other_use_this_block = 1;
524 IOR_HARD_REG_SET (info.btrs_written_in_block, all_btrs);
525 IOR_HARD_REG_SET (info.btrs_live_in_block, all_btrs);
526 sbitmap_zero (info.bb_gen);
527 }
504 else
505 {
506 if (btr_referenced_p (PATTERN (insn), NULL))
507 {
508 btr_user user = new_btr_user (bb, insn_luid, insn);
509
510 use_array[insn_uid] = user;
511 if (user->use)

--- 11 unchanged lines hidden (view full) ---

523 info.users_this_bb);
524 SET_HARD_REG_BIT (info.btrs_live_in_block, reg);
525 }
526 note_stores (PATTERN (insn), note_btr_set, &info);
527 }
528 user->next = info.users_this_bb;
529 info.users_this_bb = user;
530 }
528 else
529 {
530 if (btr_referenced_p (PATTERN (insn), NULL))
531 {
532 btr_user user = new_btr_user (bb, insn_luid, insn);
533
534 use_array[insn_uid] = user;
535 if (user->use)

--- 11 unchanged lines hidden (view full) ---

547 info.users_this_bb);
548 SET_HARD_REG_BIT (info.btrs_live_in_block, reg);
549 }
550 note_stores (PATTERN (insn), note_btr_set, &info);
551 }
552 user->next = info.users_this_bb;
553 info.users_this_bb = user;
554 }
531 if (GET_CODE (insn) == CALL_INSN)
555 if (CALL_P (insn))
532 {
533 HARD_REG_SET *clobbered = &call_used_reg_set;
534 HARD_REG_SET call_saved;
535 rtx pat = PATTERN (insn);
536 int i;
537
538 /* Check for sibcall. */
539 if (GET_CODE (pat) == PARALLEL)
540 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
541 if (GET_CODE (XVECEXP (pat, 0, i)) == RETURN)
542 {
543 COMPL_HARD_REG_SET (call_saved,
544 call_used_reg_set);
545 clobbered = &call_saved;
546 }
556 {
557 HARD_REG_SET *clobbered = &call_used_reg_set;
558 HARD_REG_SET call_saved;
559 rtx pat = PATTERN (insn);
560 int i;
561
562 /* Check for sibcall. */
563 if (GET_CODE (pat) == PARALLEL)
564 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
565 if (GET_CODE (XVECEXP (pat, 0, i)) == RETURN)
566 {
567 COMPL_HARD_REG_SET (call_saved,
568 call_used_reg_set);
569 clobbered = &call_saved;
570 }
547
571
548 for (regno = first_btr; regno <= last_btr; regno++)
549 if (TEST_HARD_REG_BIT (*clobbered, regno))
550 note_btr_set (regno_reg_rtx[regno], NULL_RTX, &info);
551 }
552 }
553 }
554 }
555
556 COPY_HARD_REG_SET (btrs_live[i], info.btrs_live_in_block);
557 COPY_HARD_REG_SET (btrs_written[i], info.btrs_written_in_block);
572 for (regno = first_btr; regno <= last_btr; regno++)
573 if (TEST_HARD_REG_BIT (*clobbered, regno))
574 note_btr_set (regno_reg_rtx[regno], NULL_RTX, &info);
575 }
576 }
577 }
578 }
579
580 COPY_HARD_REG_SET (btrs_live[i], info.btrs_live_in_block);
581 COPY_HARD_REG_SET (btrs_written[i], info.btrs_written_in_block);
558 if (rtl_dump_file)
582
583 REG_SET_TO_HARD_REG_SET (btrs_live_at_end[i], bb->il.rtl->global_live_at_end);
584 /* If this block ends in a jump insn, add any uses or even clobbers
585 of branch target registers that it might have. */
586 for (insn = BB_END (bb); insn != BB_HEAD (bb) && ! INSN_P (insn); )
587 insn = PREV_INSN (insn);
588 /* ??? for the fall-through edge, it would make sense to insert the
589 btr set on the edge, but that would require to split the block
590 early on so that we can distinguish between dominance from the fall
591 through edge - which can use the call-clobbered registers - from
592 dominance by the throw edge. */
593 if (can_throw_internal (insn))
594 {
595 HARD_REG_SET tmp;
596
597 COPY_HARD_REG_SET (tmp, call_used_reg_set);
598 AND_HARD_REG_SET (tmp, all_btrs);
599 IOR_HARD_REG_SET (btrs_live_at_end[i], tmp);
600 can_throw = 1;
601 }
602 if (can_throw || JUMP_P (insn))
603 {
604 int regno;
605
606 for (regno = first_btr; regno <= last_btr; regno++)
607 if (refers_to_regno_p (regno, regno+1, insn, NULL))
608 SET_HARD_REG_BIT (btrs_live_at_end[i], regno);
609 }
610
611 if (dump_file)
559 dump_btrs_live(i);
560 }
561}
562
563static void
564compute_kill (sbitmap *bb_kill, sbitmap *btr_defset,
565 HARD_REG_SET *btrs_written)
566{
567 int i;
568 int regno;
569
570 /* For each basic block, form the set BB_KILL - the set
571 of definitions that the block kills. */
572 sbitmap_vector_zero (bb_kill, n_basic_blocks);
612 dump_btrs_live(i);
613 }
614}
615
616static void
617compute_kill (sbitmap *bb_kill, sbitmap *btr_defset,
618 HARD_REG_SET *btrs_written)
619{
620 int i;
621 int regno;
622
623 /* For each basic block, form the set BB_KILL - the set
624 of definitions that the block kills. */
625 sbitmap_vector_zero (bb_kill, n_basic_blocks);
573 for (i = 0; i < n_basic_blocks; i++)
626 for (i = NUM_FIXED_BLOCKS; i < n_basic_blocks; i++)
574 {
575 for (regno = first_btr; regno <= last_btr; regno++)
576 if (TEST_HARD_REG_BIT (all_btrs, regno)
577 && TEST_HARD_REG_BIT (btrs_written[i], regno))
578 sbitmap_a_or_b (bb_kill[i], bb_kill[i],
579 btr_defset[regno - first_btr]);
580 }
581}

--- 6 unchanged lines hidden (view full) ---

588 For each block,
589 BB_IN = union over predecessors of BB_OUT(pred)
590 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
591 Iterate until the bb_out sets stop growing. */
592 int i;
593 int changed;
594 sbitmap bb_in = sbitmap_alloc (max_uid);
595
627 {
628 for (regno = first_btr; regno <= last_btr; regno++)
629 if (TEST_HARD_REG_BIT (all_btrs, regno)
630 && TEST_HARD_REG_BIT (btrs_written[i], regno))
631 sbitmap_a_or_b (bb_kill[i], bb_kill[i],
632 btr_defset[regno - first_btr]);
633 }
634}

--- 6 unchanged lines hidden (view full) ---

641 For each block,
642 BB_IN = union over predecessors of BB_OUT(pred)
643 BB_OUT = (BB_IN - BB_KILL) + BB_GEN
644 Iterate until the bb_out sets stop growing. */
645 int i;
646 int changed;
647 sbitmap bb_in = sbitmap_alloc (max_uid);
648
596 for (i = 0; i < n_basic_blocks; i++)
649 for (i = NUM_FIXED_BLOCKS; i < n_basic_blocks; i++)
597 sbitmap_copy (bb_out[i], bb_gen[i]);
598
599 changed = 1;
600 while (changed)
601 {
602 changed = 0;
650 sbitmap_copy (bb_out[i], bb_gen[i]);
651
652 changed = 1;
653 while (changed)
654 {
655 changed = 0;
603 for (i = 0; i < n_basic_blocks; i++)
656 for (i = NUM_FIXED_BLOCKS; i < n_basic_blocks; i++)
604 {
605 sbitmap_union_of_preds (bb_in, bb_out, i);
606 changed |= sbitmap_union_of_diff_cg (bb_out[i], bb_gen[i],
607 bb_in, bb_kill[i]);
608 }
609 }
610 sbitmap_free (bb_in);
611}
612
613static void
614link_btr_uses (btr_def *def_array, btr_user *use_array, sbitmap *bb_out,
615 sbitmap *btr_defset, int max_uid)
616{
617 int i;
618 sbitmap reaching_defs = sbitmap_alloc (max_uid);
619
620 /* Link uses to the uses lists of all of their reaching defs.
621 Count up the number of reaching defs of each use. */
657 {
658 sbitmap_union_of_preds (bb_in, bb_out, i);
659 changed |= sbitmap_union_of_diff_cg (bb_out[i], bb_gen[i],
660 bb_in, bb_kill[i]);
661 }
662 }
663 sbitmap_free (bb_in);
664}
665
666static void
667link_btr_uses (btr_def *def_array, btr_user *use_array, sbitmap *bb_out,
668 sbitmap *btr_defset, int max_uid)
669{
670 int i;
671 sbitmap reaching_defs = sbitmap_alloc (max_uid);
672
673 /* Link uses to the uses lists of all of their reaching defs.
674 Count up the number of reaching defs of each use. */
622 for (i = 0; i < n_basic_blocks; i++)
675 for (i = NUM_FIXED_BLOCKS; i < n_basic_blocks; i++)
623 {
624 basic_block bb = BASIC_BLOCK (i);
625 rtx insn;
626 rtx last;
627
628 sbitmap_union_of_preds (reaching_defs, bb_out, i);
629 for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb));
630 insn != last;

--- 13 unchanged lines hidden (view full) ---

644 btr_defset[def->btr - first_btr]);
645 SET_BIT(reaching_defs, insn_uid);
646 }
647
648 if (user != NULL)
649 {
650 /* Find all the reaching defs for this use. */
651 sbitmap reaching_defs_of_reg = sbitmap_alloc(max_uid);
676 {
677 basic_block bb = BASIC_BLOCK (i);
678 rtx insn;
679 rtx last;
680
681 sbitmap_union_of_preds (reaching_defs, bb_out, i);
682 for (insn = BB_HEAD (bb), last = NEXT_INSN (BB_END (bb));
683 insn != last;

--- 13 unchanged lines hidden (view full) ---

697 btr_defset[def->btr - first_btr]);
698 SET_BIT(reaching_defs, insn_uid);
699 }
700
701 if (user != NULL)
702 {
703 /* Find all the reaching defs for this use. */
704 sbitmap reaching_defs_of_reg = sbitmap_alloc(max_uid);
652 int uid;
705 unsigned int uid = 0;
706 sbitmap_iterator sbi;
653
654 if (user->use)
655 sbitmap_a_and_b (
656 reaching_defs_of_reg,
657 reaching_defs,
658 btr_defset[REGNO (user->use) - first_btr]);
659 else
660 {

--- 4 unchanged lines hidden (view full) ---

665 if (TEST_HARD_REG_BIT (all_btrs, reg)
666 && refers_to_regno_p (reg, reg + 1, user->insn,
667 NULL))
668 sbitmap_a_or_b_and_c (reaching_defs_of_reg,
669 reaching_defs_of_reg,
670 reaching_defs,
671 btr_defset[reg - first_btr]);
672 }
707
708 if (user->use)
709 sbitmap_a_and_b (
710 reaching_defs_of_reg,
711 reaching_defs,
712 btr_defset[REGNO (user->use) - first_btr]);
713 else
714 {

--- 4 unchanged lines hidden (view full) ---

719 if (TEST_HARD_REG_BIT (all_btrs, reg)
720 && refers_to_regno_p (reg, reg + 1, user->insn,
721 NULL))
722 sbitmap_a_or_b_and_c (reaching_defs_of_reg,
723 reaching_defs_of_reg,
724 reaching_defs,
725 btr_defset[reg - first_btr]);
726 }
673 EXECUTE_IF_SET_IN_SBITMAP (reaching_defs_of_reg, 0, uid,
727 EXECUTE_IF_SET_IN_SBITMAP (reaching_defs_of_reg, 0, uid, sbi)
674 {
675 btr_def def = def_array[uid];
676
677 /* We now know that def reaches user. */
678
728 {
729 btr_def def = def_array[uid];
730
731 /* We now know that def reaches user. */
732
679 if (rtl_dump_file)
680 fprintf (rtl_dump_file,
733 if (dump_file)
734 fprintf (dump_file,
681 "Def in insn %d reaches use in insn %d\n",
682 uid, insn_uid);
683
684 user->n_reaching_defs++;
685 if (!user->use)
686 def->has_ambiguous_use = 1;
687 if (user->first_reaching_def != -1)
688 { /* There is more than one reaching def. This is
689 a rare case, so just give up on this def/use
690 web when it occurs. */
691 def->has_ambiguous_use = 1;
692 def_array[user->first_reaching_def]
693 ->has_ambiguous_use = 1;
735 "Def in insn %d reaches use in insn %d\n",
736 uid, insn_uid);
737
738 user->n_reaching_defs++;
739 if (!user->use)
740 def->has_ambiguous_use = 1;
741 if (user->first_reaching_def != -1)
742 { /* There is more than one reaching def. This is
743 a rare case, so just give up on this def/use
744 web when it occurs. */
745 def->has_ambiguous_use = 1;
746 def_array[user->first_reaching_def]
747 ->has_ambiguous_use = 1;
694 if (rtl_dump_file)
695 fprintf (rtl_dump_file,
748 if (dump_file)
749 fprintf (dump_file,
696 "(use %d has multiple reaching defs)\n",
697 insn_uid);
698 }
699 else
700 user->first_reaching_def = uid;
701 if (user->other_use_this_block)
702 def->other_btr_uses_after_use = 1;
703 user->next = def->uses;
704 def->uses = user;
750 "(use %d has multiple reaching defs)\n",
751 insn_uid);
752 }
753 else
754 user->first_reaching_def = uid;
755 if (user->other_use_this_block)
756 def->other_btr_uses_after_use = 1;
757 user->next = def->uses;
758 def->uses = user;
705 });
759 }
706 sbitmap_free (reaching_defs_of_reg);
707 }
708
760 sbitmap_free (reaching_defs_of_reg);
761 }
762
709 if (GET_CODE (insn) == CALL_INSN)
763 if (CALL_P (insn))
710 {
711 int regno;
712
713 for (regno = first_btr; regno <= last_btr; regno++)
714 if (TEST_HARD_REG_BIT (all_btrs, regno)
715 && TEST_HARD_REG_BIT (call_used_reg_set, regno))
716 sbitmap_difference (reaching_defs, reaching_defs,
717 btr_defset[regno - first_btr]);
718 }
719 }
720 }
721 }
722 sbitmap_free (reaching_defs);
723}
724
725static void
726build_btr_def_use_webs (fibheap_t all_btr_defs)
727{
728 const int max_uid = get_max_uid ();
764 {
765 int regno;
766
767 for (regno = first_btr; regno <= last_btr; regno++)
768 if (TEST_HARD_REG_BIT (all_btrs, regno)
769 && TEST_HARD_REG_BIT (call_used_reg_set, regno))
770 sbitmap_difference (reaching_defs, reaching_defs,
771 btr_defset[regno - first_btr]);
772 }
773 }
774 }
775 }
776 sbitmap_free (reaching_defs);
777}
778
779static void
780build_btr_def_use_webs (fibheap_t all_btr_defs)
781{
782 const int max_uid = get_max_uid ();
729 btr_def *def_array = xcalloc (max_uid, sizeof (btr_def));
730 btr_user *use_array = xcalloc (max_uid, sizeof (btr_user));
783 btr_def *def_array = XCNEWVEC (btr_def, max_uid);
784 btr_user *use_array = XCNEWVEC (btr_user, max_uid);
731 sbitmap *btr_defset = sbitmap_vector_alloc (
732 (last_btr - first_btr) + 1, max_uid);
733 sbitmap *bb_gen = sbitmap_vector_alloc (n_basic_blocks, max_uid);
785 sbitmap *btr_defset = sbitmap_vector_alloc (
786 (last_btr - first_btr) + 1, max_uid);
787 sbitmap *bb_gen = sbitmap_vector_alloc (n_basic_blocks, max_uid);
734 HARD_REG_SET *btrs_written = xcalloc (n_basic_blocks, sizeof (HARD_REG_SET));
788 HARD_REG_SET *btrs_written = XCNEWVEC (HARD_REG_SET, n_basic_blocks);
735 sbitmap *bb_kill;
736 sbitmap *bb_out;
737
738 sbitmap_vector_zero (btr_defset, (last_btr - first_btr) + 1);
739
740 compute_defs_uses_and_gen (all_btr_defs, def_array, use_array, btr_defset,
741 bb_gen, btrs_written);
742

--- 39 unchanged lines hidden (view full) ---

782 in the live range of the web.
783 Blocks at the boundary of the live range may contain other live
784 ranges for the same target register, so we have to be careful
785 to remove the target register from the live set of these blocks
786 only if they do not contain other live ranges for the same register. */
787static void
788clear_btr_from_live_range (btr_def def)
789{
789 sbitmap *bb_kill;
790 sbitmap *bb_out;
791
792 sbitmap_vector_zero (btr_defset, (last_btr - first_btr) + 1);
793
794 compute_defs_uses_and_gen (all_btr_defs, def_array, use_array, btr_defset,
795 bb_gen, btrs_written);
796

--- 39 unchanged lines hidden (view full) ---

836 in the live range of the web.
837 Blocks at the boundary of the live range may contain other live
838 ranges for the same target register, so we have to be careful
839 to remove the target register from the live set of these blocks
840 only if they do not contain other live ranges for the same register. */
841static void
842clear_btr_from_live_range (btr_def def)
843{
790 int bb;
844 unsigned bb;
845 bitmap_iterator bi;
791
846
792 EXECUTE_IF_SET_IN_BITMAP
793 (def->live_range, 0, bb,
794 {
795 if ((!def->other_btr_uses_before_def
796 && !def->other_btr_uses_after_use)
797 || !block_at_edge_of_live_range_p (bb, def))
798 {
799 CLEAR_HARD_REG_BIT (btrs_live[bb], def->btr);
800 if (rtl_dump_file)
801 dump_btrs_live (bb);
802 }
803 });
847 EXECUTE_IF_SET_IN_BITMAP (def->live_range, 0, bb, bi)
848 {
849 if ((!def->other_btr_uses_before_def
850 && !def->other_btr_uses_after_use)
851 || !block_at_edge_of_live_range_p (bb, def))
852 {
853 CLEAR_HARD_REG_BIT (btrs_live[bb], def->btr);
854 CLEAR_HARD_REG_BIT (btrs_live_at_end[bb], def->btr);
855 if (dump_file)
856 dump_btrs_live (bb);
857 }
858 }
859 if (def->own_end)
860 CLEAR_HARD_REG_BIT (btrs_live_at_end[def->bb->index], def->btr);
804}
805
806
807/* We are adding the def/use web DEF. Add the target register used
808 in this web to the live set of all of the basic blocks that contain
861}
862
863
864/* We are adding the def/use web DEF. Add the target register used
865 in this web to the live set of all of the basic blocks that contain
809 the live range of the web. */
866 the live range of the web.
867 If OWN_END is set, also show that the register is live from our
868 definitions at the end of the basic block where it is defined. */
810static void
869static void
811add_btr_to_live_range (btr_def def)
870add_btr_to_live_range (btr_def def, int own_end)
812{
871{
813 int bb;
814 EXECUTE_IF_SET_IN_BITMAP
815 (def->live_range, 0, bb,
816 {
817 SET_HARD_REG_BIT (btrs_live[bb], def->btr);
818 if (rtl_dump_file)
819 dump_btrs_live (bb);
820 });
872 unsigned bb;
873 bitmap_iterator bi;
874
875 EXECUTE_IF_SET_IN_BITMAP (def->live_range, 0, bb, bi)
876 {
877 SET_HARD_REG_BIT (btrs_live[bb], def->btr);
878 SET_HARD_REG_BIT (btrs_live_at_end[bb], def->btr);
879 if (dump_file)
880 dump_btrs_live (bb);
881 }
882 if (own_end)
883 {
884 SET_HARD_REG_BIT (btrs_live_at_end[def->bb->index], def->btr);
885 def->own_end = 1;
886 }
821}
822
823/* Update a live range to contain the basic block NEW_BLOCK, and all
824 blocks on paths between the existing live range and NEW_BLOCK.
825 HEAD is a block contained in the existing live range that dominates
826 all other blocks in the existing live range.
827 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
828 are live in the blocks that we add to the live range.
887}
888
889/* Update a live range to contain the basic block NEW_BLOCK, and all
890 blocks on paths between the existing live range and NEW_BLOCK.
891 HEAD is a block contained in the existing live range that dominates
892 all other blocks in the existing live range.
893 Also add to the set BTRS_LIVE_IN_RANGE all target registers that
894 are live in the blocks that we add to the live range.
895 If FULL_RANGE is set, include the full live range of NEW_BB;
896 otherwise, if NEW_BB dominates HEAD_BB, only add registers that
897 are life at the end of NEW_BB for NEW_BB itself.
829 It is a precondition that either NEW_BLOCK dominates HEAD,or
830 HEAD dom NEW_BLOCK. This is used to speed up the
831 implementation of this function. */
832static void
833augment_live_range (bitmap live_range, HARD_REG_SET *btrs_live_in_range,
898 It is a precondition that either NEW_BLOCK dominates HEAD,or
899 HEAD dom NEW_BLOCK. This is used to speed up the
900 implementation of this function. */
901static void
902augment_live_range (bitmap live_range, HARD_REG_SET *btrs_live_in_range,
834 basic_block head_bb, basic_block new_bb)
903 basic_block head_bb, basic_block new_bb, int full_range)
835{
836 basic_block *worklist, *tos;
837
904{
905 basic_block *worklist, *tos;
906
838 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
907 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
839
840 if (dominated_by_p (CDI_DOMINATORS, new_bb, head_bb))
908
909 if (dominated_by_p (CDI_DOMINATORS, new_bb, head_bb))
841 *tos++ = new_bb;
842 else if (dominated_by_p (CDI_DOMINATORS, head_bb, new_bb))
843 {
910 {
911 if (new_bb == head_bb)
912 {
913 if (full_range)
914 IOR_HARD_REG_SET (*btrs_live_in_range, btrs_live[new_bb->index]);
915 free (tos);
916 return;
917 }
918 *tos++ = new_bb;
919 }
920 else
921 {
844 edge e;
922 edge e;
923 edge_iterator ei;
845 int new_block = new_bb->index;
846
924 int new_block = new_bb->index;
925
926 gcc_assert (dominated_by_p (CDI_DOMINATORS, head_bb, new_bb));
927
928 IOR_HARD_REG_SET (*btrs_live_in_range, btrs_live[head_bb->index]);
847 bitmap_set_bit (live_range, new_block);
929 bitmap_set_bit (live_range, new_block);
848 IOR_HARD_REG_SET (*btrs_live_in_range, btrs_live[new_block]);
849 if (rtl_dump_file)
930 /* A previous btr migration could have caused a register to be
931 live just at the end of new_block which we need in full, so
932 use trs_live_at_end even if full_range is set. */
933 IOR_HARD_REG_SET (*btrs_live_in_range, btrs_live_at_end[new_block]);
934 if (full_range)
935 IOR_HARD_REG_SET (*btrs_live_in_range, btrs_live[new_block]);
936 if (dump_file)
850 {
937 {
851 fprintf (rtl_dump_file,
852 "Adding block %d to live range\n", new_block);
853 fprintf (rtl_dump_file,"Now live btrs are ");
938 fprintf (dump_file,
939 "Adding end of block %d and rest of %d to live range\n",
940 new_block, head_bb->index);
941 fprintf (dump_file,"Now live btrs are ");
854 dump_hard_reg_set (*btrs_live_in_range);
942 dump_hard_reg_set (*btrs_live_in_range);
855 fprintf (rtl_dump_file, "\n");
943 fprintf (dump_file, "\n");
856 }
944 }
857 for (e = head_bb->pred; e; e = e->pred_next)
945 FOR_EACH_EDGE (e, ei, head_bb->preds)
858 *tos++ = e->src;
859 }
946 *tos++ = e->src;
947 }
860 else
861 abort();
862
863 while (tos != worklist)
864 {
865 basic_block bb = *--tos;
866 if (!bitmap_bit_p (live_range, bb->index))
867 {
868 edge e;
948
949 while (tos != worklist)
950 {
951 basic_block bb = *--tos;
952 if (!bitmap_bit_p (live_range, bb->index))
953 {
954 edge e;
955 edge_iterator ei;
869
870 bitmap_set_bit (live_range, bb->index);
871 IOR_HARD_REG_SET (*btrs_live_in_range,
872 btrs_live[bb->index]);
956
957 bitmap_set_bit (live_range, bb->index);
958 IOR_HARD_REG_SET (*btrs_live_in_range,
959 btrs_live[bb->index]);
873 if (rtl_dump_file)
960 /* A previous btr migration could have caused a register to be
961 live just at the end of a block which we need in full. */
962 IOR_HARD_REG_SET (*btrs_live_in_range,
963 btrs_live_at_end[bb->index]);
964 if (dump_file)
874 {
965 {
875 fprintf (rtl_dump_file,
966 fprintf (dump_file,
876 "Adding block %d to live range\n", bb->index);
967 "Adding block %d to live range\n", bb->index);
877 fprintf (rtl_dump_file,"Now live btrs are ");
968 fprintf (dump_file,"Now live btrs are ");
878 dump_hard_reg_set (*btrs_live_in_range);
969 dump_hard_reg_set (*btrs_live_in_range);
879 fprintf (rtl_dump_file, "\n");
970 fprintf (dump_file, "\n");
880 }
881
971 }
972
882 for (e = bb->pred; e != NULL; e = e->pred_next)
973 FOR_EACH_EDGE (e, ei, bb->preds)
883 {
884 basic_block pred = e->src;
885 if (!bitmap_bit_p (live_range, pred->index))
886 *tos++ = pred;
887 }
888 }
889 }
890

--- 30 unchanged lines hidden (view full) ---

921 when calculating this set. */
922static void
923btr_def_live_range (btr_def def, HARD_REG_SET *btrs_live_in_range)
924{
925 if (!def->live_range)
926 {
927 btr_user user;
928
974 {
975 basic_block pred = e->src;
976 if (!bitmap_bit_p (live_range, pred->index))
977 *tos++ = pred;
978 }
979 }
980 }
981

--- 30 unchanged lines hidden (view full) ---

1012 when calculating this set. */
1013static void
1014btr_def_live_range (btr_def def, HARD_REG_SET *btrs_live_in_range)
1015{
1016 if (!def->live_range)
1017 {
1018 btr_user user;
1019
929 def->live_range = BITMAP_XMALLOC ();
1020 def->live_range = BITMAP_ALLOC (NULL);
930
931 bitmap_set_bit (def->live_range, def->bb->index);
1021
1022 bitmap_set_bit (def->live_range, def->bb->index);
932 COPY_HARD_REG_SET (*btrs_live_in_range, btrs_live[def->bb->index]);
1023 COPY_HARD_REG_SET (*btrs_live_in_range,
1024 (flag_btr_bb_exclusive
1025 ? btrs_live : btrs_live_at_end)[def->bb->index]);
933
934 for (user = def->uses; user != NULL; user = user->next)
935 augment_live_range (def->live_range, btrs_live_in_range,
1026
1027 for (user = def->uses; user != NULL; user = user->next)
1028 augment_live_range (def->live_range, btrs_live_in_range,
936 def->bb, user->bb);
1029 def->bb, user->bb,
1030 (flag_btr_bb_exclusive
1031 || user->insn != BB_END (def->bb)
1032 || !JUMP_P (user->insn)));
937 }
938 else
939 {
940 /* def->live_range is accurate, but we need to recompute
941 the set of target registers live over it, because migration
942 of other PT instructions may have affected it.
943 */
1033 }
1034 else
1035 {
1036 /* def->live_range is accurate, but we need to recompute
1037 the set of target registers live over it, because migration
1038 of other PT instructions may have affected it.
1039 */
944 int bb;
1040 unsigned bb;
1041 unsigned def_bb = flag_btr_bb_exclusive ? -1 : def->bb->index;
1042 bitmap_iterator bi;
945
946 CLEAR_HARD_REG_SET (*btrs_live_in_range);
1043
1044 CLEAR_HARD_REG_SET (*btrs_live_in_range);
947 EXECUTE_IF_SET_IN_BITMAP
948 (def->live_range, 0, bb,
949 {
950 IOR_HARD_REG_SET (*btrs_live_in_range,
951 btrs_live[bb]);
952 });
1045 EXECUTE_IF_SET_IN_BITMAP (def->live_range, 0, bb, bi)
1046 {
1047 IOR_HARD_REG_SET (*btrs_live_in_range,
1048 (def_bb == bb
1049 ? btrs_live_at_end : btrs_live) [bb]);
1050 }
953 }
954 if (!def->other_btr_uses_before_def &&
955 !def->other_btr_uses_after_use)
956 CLEAR_HARD_REG_BIT (*btrs_live_in_range, def->btr);
957}
958
959/* Merge into the def/use web DEF any other def/use webs in the same
960 group that are dominated by DEF, provided that there is a target

--- 13 unchanged lines hidden (view full) ---

974 && dominated_by_p (CDI_DOMINATORS, other_def->bb, def->bb))
975 {
976 /* def->bb dominates the other def, so def and other_def could
977 be combined. */
978 /* Merge their live ranges, and get the set of
979 target registers live over the merged range. */
980 int btr;
981 HARD_REG_SET combined_btrs_live;
1051 }
1052 if (!def->other_btr_uses_before_def &&
1053 !def->other_btr_uses_after_use)
1054 CLEAR_HARD_REG_BIT (*btrs_live_in_range, def->btr);
1055}
1056
1057/* Merge into the def/use web DEF any other def/use webs in the same
1058 group that are dominated by DEF, provided that there is a target

--- 13 unchanged lines hidden (view full) ---

1072 && dominated_by_p (CDI_DOMINATORS, other_def->bb, def->bb))
1073 {
1074 /* def->bb dominates the other def, so def and other_def could
1075 be combined. */
1076 /* Merge their live ranges, and get the set of
1077 target registers live over the merged range. */
1078 int btr;
1079 HARD_REG_SET combined_btrs_live;
982 bitmap combined_live_range = BITMAP_XMALLOC ();
1080 bitmap combined_live_range = BITMAP_ALLOC (NULL);
983 btr_user user;
984
985 if (other_def->live_range == NULL)
986 {
987 HARD_REG_SET dummy_btrs_live_in_range;
988 btr_def_live_range (other_def, &dummy_btrs_live_in_range);
989 }
990 COPY_HARD_REG_SET (combined_btrs_live, *btrs_live_in_range);
991 bitmap_copy (combined_live_range, def->live_range);
992
993 for (user = other_def->uses; user != NULL; user = user->next)
994 augment_live_range (combined_live_range, &combined_btrs_live,
1081 btr_user user;
1082
1083 if (other_def->live_range == NULL)
1084 {
1085 HARD_REG_SET dummy_btrs_live_in_range;
1086 btr_def_live_range (other_def, &dummy_btrs_live_in_range);
1087 }
1088 COPY_HARD_REG_SET (combined_btrs_live, *btrs_live_in_range);
1089 bitmap_copy (combined_live_range, def->live_range);
1090
1091 for (user = other_def->uses; user != NULL; user = user->next)
1092 augment_live_range (combined_live_range, &combined_btrs_live,
995 def->bb, user->bb);
1093 def->bb, user->bb,
1094 (flag_btr_bb_exclusive
1095 || user->insn != BB_END (def->bb)
1096 || !JUMP_P (user->insn)));
996
997 btr = choose_btr (combined_btrs_live);
998 if (btr != -1)
999 {
1000 /* We can combine them. */
1097
1098 btr = choose_btr (combined_btrs_live);
1099 if (btr != -1)
1100 {
1101 /* We can combine them. */
1001 if (rtl_dump_file)
1002 fprintf (rtl_dump_file,
1102 if (dump_file)
1103 fprintf (dump_file,
1003 "Combining def in insn %d with def in insn %d\n",
1004 INSN_UID (other_def->insn), INSN_UID (def->insn));
1005
1006 def->btr = btr;
1007 user = other_def->uses;
1008 while (user != NULL)
1009 {
1010 btr_user next = user->next;

--- 10 unchanged lines hidden (view full) ---

1021 in case they are no longer correct. */
1022 for (user = def->uses; user != NULL; user = user->next)
1023 remove_note (user->insn,
1024 find_regno_note (user->insn, REG_DEAD,
1025 REGNO (user->use)));
1026 clear_btr_from_live_range (other_def);
1027 other_def->uses = NULL;
1028 bitmap_copy (def->live_range, combined_live_range);
1104 "Combining def in insn %d with def in insn %d\n",
1105 INSN_UID (other_def->insn), INSN_UID (def->insn));
1106
1107 def->btr = btr;
1108 user = other_def->uses;
1109 while (user != NULL)
1110 {
1111 btr_user next = user->next;

--- 10 unchanged lines hidden (view full) ---

1122 in case they are no longer correct. */
1123 for (user = def->uses; user != NULL; user = user->next)
1124 remove_note (user->insn,
1125 find_regno_note (user->insn, REG_DEAD,
1126 REGNO (user->use)));
1127 clear_btr_from_live_range (other_def);
1128 other_def->uses = NULL;
1129 bitmap_copy (def->live_range, combined_live_range);
1029 if (other_def->other_btr_uses_after_use)
1130 if (other_def->btr == btr && other_def->other_btr_uses_after_use)
1030 def->other_btr_uses_after_use = 1;
1031 COPY_HARD_REG_SET (*btrs_live_in_range, combined_btrs_live);
1032
1033 /* Delete the old target register initialization. */
1034 delete_insn (other_def->insn);
1035
1036 }
1131 def->other_btr_uses_after_use = 1;
1132 COPY_HARD_REG_SET (*btrs_live_in_range, combined_btrs_live);
1133
1134 /* Delete the old target register initialization. */
1135 delete_insn (other_def->insn);
1136
1137 }
1037 BITMAP_XFREE (combined_live_range);
1138 BITMAP_FREE (combined_live_range);
1038 }
1039 }
1040}
1041
1042/* Move the definition DEF from its current position to basic
1043 block NEW_DEF_BB, and modify it to use branch target register BTR.
1044 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1045 Update all reaching uses of DEF in the RTL to use BTR.

--- 13 unchanged lines hidden (view full) ---

1059 rtx old_insn = def->insn;
1060 rtx src;
1061 rtx btr_rtx;
1062 rtx new_insn;
1063 enum machine_mode btr_mode;
1064 btr_user user;
1065 rtx set;
1066
1139 }
1140 }
1141}
1142
1143/* Move the definition DEF from its current position to basic
1144 block NEW_DEF_BB, and modify it to use branch target register BTR.
1145 Delete the old defining insn, and insert a new one in NEW_DEF_BB.
1146 Update all reaching uses of DEF in the RTL to use BTR.

--- 13 unchanged lines hidden (view full) ---

1160 rtx old_insn = def->insn;
1161 rtx src;
1162 rtx btr_rtx;
1163 rtx new_insn;
1164 enum machine_mode btr_mode;
1165 btr_user user;
1166 rtx set;
1167
1067 if (rtl_dump_file)
1068 fprintf(rtl_dump_file, "migrating to basic block %d, using reg %d\n",
1168 if (dump_file)
1169 fprintf(dump_file, "migrating to basic block %d, using reg %d\n",
1069 new_def_bb->index, btr);
1070
1071 clear_btr_from_live_range (def);
1072 def->btr = btr;
1073 def->bb = new_def_bb;
1074 def->luid = 0;
1075 def->cost = basic_block_freq (new_def_bb);
1170 new_def_bb->index, btr);
1171
1172 clear_btr_from_live_range (def);
1173 def->btr = btr;
1174 def->bb = new_def_bb;
1175 def->luid = 0;
1176 def->cost = basic_block_freq (new_def_bb);
1076 def->other_btr_uses_before_def = 0;
1077 bitmap_copy (def->live_range, live_range);
1078 combine_btr_defs (def, btrs_live_in_range);
1079 btr = def->btr;
1177 bitmap_copy (def->live_range, live_range);
1178 combine_btr_defs (def, btrs_live_in_range);
1179 btr = def->btr;
1080 add_btr_to_live_range (def);
1081 if (GET_CODE (insp) == CODE_LABEL)
1180 def->other_btr_uses_before_def
1181 = TEST_HARD_REG_BIT (btrs_live[b->index], btr) ? 1 : 0;
1182 add_btr_to_live_range (def, 1);
1183 if (LABEL_P (insp))
1082 insp = NEXT_INSN (insp);
1083 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1084 optimizations can result in insp being both first and last insn of
1085 its basic block. */
1086 /* ?? some assertions to check that insp is sensible? */
1087
1184 insp = NEXT_INSN (insp);
1185 /* N.B.: insp is expected to be NOTE_INSN_BASIC_BLOCK now. Some
1186 optimizations can result in insp being both first and last insn of
1187 its basic block. */
1188 /* ?? some assertions to check that insp is sensible? */
1189
1190 if (def->other_btr_uses_before_def)
1191 {
1192 insp = BB_END (b);
1193 for (insp = BB_END (b); ! INSN_P (insp); insp = PREV_INSN (insp))
1194 gcc_assert (insp != BB_HEAD (b));
1195
1196 if (JUMP_P (insp) || can_throw_internal (insp))
1197 insp = PREV_INSN (insp);
1198 }
1199
1088 set = single_set (old_insn);
1089 src = SET_SRC (set);
1090 btr_mode = GET_MODE (SET_DEST (set));
1200 set = single_set (old_insn);
1201 src = SET_SRC (set);
1202 btr_mode = GET_MODE (SET_DEST (set));
1091 btr_rtx = gen_rtx (REG, btr_mode, btr);
1203 btr_rtx = gen_rtx_REG (btr_mode, btr);
1092
1093 new_insn = gen_move_insn (btr_rtx, src);
1094
1095 /* Insert target register initialization at head of basic block. */
1096 def->insn = emit_insn_after (new_insn, insp);
1097
1098 regs_ever_live[btr] = 1;
1099
1204
1205 new_insn = gen_move_insn (btr_rtx, src);
1206
1207 /* Insert target register initialization at head of basic block. */
1208 def->insn = emit_insn_after (new_insn, insp);
1209
1210 regs_ever_live[btr] = 1;
1211
1100 if (rtl_dump_file)
1101 fprintf (rtl_dump_file, "New pt is insn %d, inserted after insn %d\n",
1212 if (dump_file)
1213 fprintf (dump_file, "New pt is insn %d, inserted after insn %d\n",
1102 INSN_UID (def->insn), INSN_UID (insp));
1103
1104 /* Delete the old target register initialization. */
1105 delete_insn (old_insn);
1106
1107 /* Replace each use of the old target register by a use of the new target
1108 register. */
1109 for (user = def->uses; user != NULL; user = user->next)
1110 {
1111 /* Some extra work here to ensure consistent modes, because
1112 it seems that a target register REG rtx can be given a different
1113 mode depending on the context (surely that should not be
1114 the case?). */
1115 rtx replacement_rtx;
1116 if (GET_MODE (user->use) == GET_MODE (btr_rtx)
1117 || GET_MODE (user->use) == VOIDmode)
1118 replacement_rtx = btr_rtx;
1119 else
1214 INSN_UID (def->insn), INSN_UID (insp));
1215
1216 /* Delete the old target register initialization. */
1217 delete_insn (old_insn);
1218
1219 /* Replace each use of the old target register by a use of the new target
1220 register. */
1221 for (user = def->uses; user != NULL; user = user->next)
1222 {
1223 /* Some extra work here to ensure consistent modes, because
1224 it seems that a target register REG rtx can be given a different
1225 mode depending on the context (surely that should not be
1226 the case?). */
1227 rtx replacement_rtx;
1228 if (GET_MODE (user->use) == GET_MODE (btr_rtx)
1229 || GET_MODE (user->use) == VOIDmode)
1230 replacement_rtx = btr_rtx;
1231 else
1120 replacement_rtx = gen_rtx (REG, GET_MODE (user->use), btr);
1232 replacement_rtx = gen_rtx_REG (GET_MODE (user->use), btr);
1121 replace_rtx (user->insn, user->use, replacement_rtx);
1122 user->use = replacement_rtx;
1123 }
1124}
1125
1126/* We anticipate intra-block scheduling to be done. See if INSN could move
1127 up within BB by N_INSNS. */
1128static int

--- 36 unchanged lines hidden (view full) ---

1165 bitmap live_range;
1166 HARD_REG_SET btrs_live_in_range;
1167 int btr_used_near_def = 0;
1168 int def_basic_block_freq;
1169 basic_block try;
1170 int give_up = 0;
1171 int def_moved = 0;
1172 btr_user user;
1233 replace_rtx (user->insn, user->use, replacement_rtx);
1234 user->use = replacement_rtx;
1235 }
1236}
1237
1238/* We anticipate intra-block scheduling to be done. See if INSN could move
1239 up within BB by N_INSNS. */
1240static int

--- 36 unchanged lines hidden (view full) ---

1277 bitmap live_range;
1278 HARD_REG_SET btrs_live_in_range;
1279 int btr_used_near_def = 0;
1280 int def_basic_block_freq;
1281 basic_block try;
1282 int give_up = 0;
1283 int def_moved = 0;
1284 btr_user user;
1173 int def_latency = 1;
1285 int def_latency;
1174
1286
1175 if (rtl_dump_file)
1176 fprintf (rtl_dump_file,
1287 if (dump_file)
1288 fprintf (dump_file,
1177 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1178 INSN_UID (def->insn), def->cost, min_cost);
1179
1180 if (!def->group || def->has_ambiguous_use)
1181 /* These defs are not migratable. */
1182 {
1289 "Attempting to migrate pt from insn %d (cost = %d, min_cost = %d) ... ",
1290 INSN_UID (def->insn), def->cost, min_cost);
1291
1292 if (!def->group || def->has_ambiguous_use)
1293 /* These defs are not migratable. */
1294 {
1183 if (rtl_dump_file)
1184 fprintf (rtl_dump_file, "it's not migratable\n");
1295 if (dump_file)
1296 fprintf (dump_file, "it's not migratable\n");
1185 return 0;
1186 }
1187
1188 if (!def->uses)
1189 /* We have combined this def with another in the same group, so
1190 no need to consider it further.
1191 */
1192 {
1297 return 0;
1298 }
1299
1300 if (!def->uses)
1301 /* We have combined this def with another in the same group, so
1302 no need to consider it further.
1303 */
1304 {
1193 if (rtl_dump_file)
1194 fprintf (rtl_dump_file, "it's already combined with another pt\n");
1305 if (dump_file)
1306 fprintf (dump_file, "it's already combined with another pt\n");
1195 return 0;
1196 }
1197
1198 btr_def_live_range (def, &btrs_live_in_range);
1307 return 0;
1308 }
1309
1310 btr_def_live_range (def, &btrs_live_in_range);
1199 live_range = BITMAP_XMALLOC ();
1311 live_range = BITMAP_ALLOC (NULL);
1200 bitmap_copy (live_range, def->live_range);
1201
1202#ifdef INSN_SCHEDULING
1312 bitmap_copy (live_range, def->live_range);
1313
1314#ifdef INSN_SCHEDULING
1203 if ((*targetm.sched.use_dfa_pipeline_interface) ())
1204 def_latency = insn_default_latency (def->insn);
1205 else
1206 def_latency = result_ready_cost (def->insn);
1315 def_latency = insn_default_latency (def->insn) * issue_rate;
1316#else
1317 def_latency = issue_rate;
1207#endif
1208
1318#endif
1319
1209 def_latency *= issue_rate;
1210
1211 for (user = def->uses; user != NULL; user = user->next)
1212 {
1213 if (user->bb == def->bb
1214 && user->luid > def->luid
1215 && (def->luid + def_latency) > user->luid
1216 && ! can_move_up (def->bb, def->insn,
1217 (def->luid + def_latency) - user->luid))
1218 {

--- 6 unchanged lines hidden (view full) ---

1225
1226 for (try = get_immediate_dominator (CDI_DOMINATORS, def->bb);
1227 !give_up && try && try != ENTRY_BLOCK_PTR && def->cost >= min_cost;
1228 try = get_immediate_dominator (CDI_DOMINATORS, try))
1229 {
1230 /* Try to move the instruction that sets the target register into
1231 basic block TRY. */
1232 int try_freq = basic_block_freq (try);
1320 for (user = def->uses; user != NULL; user = user->next)
1321 {
1322 if (user->bb == def->bb
1323 && user->luid > def->luid
1324 && (def->luid + def_latency) > user->luid
1325 && ! can_move_up (def->bb, def->insn,
1326 (def->luid + def_latency) - user->luid))
1327 {

--- 6 unchanged lines hidden (view full) ---

1334
1335 for (try = get_immediate_dominator (CDI_DOMINATORS, def->bb);
1336 !give_up && try && try != ENTRY_BLOCK_PTR && def->cost >= min_cost;
1337 try = get_immediate_dominator (CDI_DOMINATORS, try))
1338 {
1339 /* Try to move the instruction that sets the target register into
1340 basic block TRY. */
1341 int try_freq = basic_block_freq (try);
1342 edge_iterator ei;
1343 edge e;
1233
1344
1234 if (rtl_dump_file)
1235 fprintf (rtl_dump_file, "trying block %d ...", try->index);
1345 /* If TRY has abnormal edges, skip it. */
1346 FOR_EACH_EDGE (e, ei, try->succs)
1347 if (e->flags & EDGE_COMPLEX)
1348 break;
1349 if (e)
1350 continue;
1236
1351
1352 if (dump_file)
1353 fprintf (dump_file, "trying block %d ...", try->index);
1354
1237 if (try_freq < def_basic_block_freq
1238 || (try_freq == def_basic_block_freq && btr_used_near_def))
1239 {
1240 int btr;
1355 if (try_freq < def_basic_block_freq
1356 || (try_freq == def_basic_block_freq && btr_used_near_def))
1357 {
1358 int btr;
1241 augment_live_range (live_range, &btrs_live_in_range, def->bb, try);
1242 if (rtl_dump_file)
1359 augment_live_range (live_range, &btrs_live_in_range, def->bb, try,
1360 flag_btr_bb_exclusive);
1361 if (dump_file)
1243 {
1362 {
1244 fprintf (rtl_dump_file, "Now btrs live in range are: ");
1363 fprintf (dump_file, "Now btrs live in range are: ");
1245 dump_hard_reg_set (btrs_live_in_range);
1364 dump_hard_reg_set (btrs_live_in_range);
1246 fprintf (rtl_dump_file, "\n");
1365 fprintf (dump_file, "\n");
1247 }
1248 btr = choose_btr (btrs_live_in_range);
1249 if (btr != -1)
1250 {
1251 move_btr_def (try, btr, def, live_range, &btrs_live_in_range);
1252 bitmap_copy(live_range, def->live_range);
1253 btr_used_near_def = 0;
1254 def_moved = 1;
1255 def_basic_block_freq = basic_block_freq (def->bb);
1256 }
1257 else
1258 {
1259 /* There are no free target registers available to move
1260 this far forward, so give up */
1261 give_up = 1;
1366 }
1367 btr = choose_btr (btrs_live_in_range);
1368 if (btr != -1)
1369 {
1370 move_btr_def (try, btr, def, live_range, &btrs_live_in_range);
1371 bitmap_copy(live_range, def->live_range);
1372 btr_used_near_def = 0;
1373 def_moved = 1;
1374 def_basic_block_freq = basic_block_freq (def->bb);
1375 }
1376 else
1377 {
1378 /* There are no free target registers available to move
1379 this far forward, so give up */
1380 give_up = 1;
1262 if (rtl_dump_file)
1263 fprintf (rtl_dump_file,
1381 if (dump_file)
1382 fprintf (dump_file,
1264 "giving up because there are no free target registers\n");
1265 }
1266
1267 }
1268 }
1269 if (!def_moved)
1270 {
1271 give_up = 1;
1383 "giving up because there are no free target registers\n");
1384 }
1385
1386 }
1387 }
1388 if (!def_moved)
1389 {
1390 give_up = 1;
1272 if (rtl_dump_file)
1273 fprintf (rtl_dump_file, "failed to move\n");
1391 if (dump_file)
1392 fprintf (dump_file, "failed to move\n");
1274 }
1393 }
1275 BITMAP_XFREE (live_range);
1394 BITMAP_FREE (live_range);
1276 return !give_up;
1277}
1278
1279/* Attempt to move instructions that set target registers earlier
1280 in the flowgraph, away from their corresponding uses. */
1281static void
1282migrate_btr_defs (enum reg_class btr_class, int allow_callee_save)
1283{
1284 fibheap_t all_btr_defs = fibheap_new ();
1285 int reg;
1286
1287 gcc_obstack_init (&migrate_btrl_obstack);
1395 return !give_up;
1396}
1397
1398/* Attempt to move instructions that set target registers earlier
1399 in the flowgraph, away from their corresponding uses. */
1400static void
1401migrate_btr_defs (enum reg_class btr_class, int allow_callee_save)
1402{
1403 fibheap_t all_btr_defs = fibheap_new ();
1404 int reg;
1405
1406 gcc_obstack_init (&migrate_btrl_obstack);
1288 if (rtl_dump_file)
1407 if (dump_file)
1289 {
1290 int i;
1291
1408 {
1409 int i;
1410
1292 for (i = 0; i < n_basic_blocks; i++)
1411 for (i = NUM_FIXED_BLOCKS; i < n_basic_blocks; i++)
1293 {
1294 basic_block bb = BASIC_BLOCK (i);
1412 {
1413 basic_block bb = BASIC_BLOCK (i);
1295 fprintf(rtl_dump_file,
1414 fprintf(dump_file,
1296 "Basic block %d: count = " HOST_WIDEST_INT_PRINT_DEC
1297 " loop-depth = %d idom = %d\n",
1298 i, (HOST_WIDEST_INT) bb->count, bb->loop_depth,
1299 get_immediate_dominator (CDI_DOMINATORS, bb)->index);
1300 }
1301 }
1302
1303 CLEAR_HARD_REG_SET (all_btrs);
1304 for (first_btr = -1, reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
1305 if (TEST_HARD_REG_BIT (reg_class_contents[(int) btr_class], reg)
1306 && (allow_callee_save || call_used_regs[reg] || regs_ever_live[reg]))
1307 {
1308 SET_HARD_REG_BIT (all_btrs, reg);
1309 last_btr = reg;
1310 if (first_btr < 0)
1311 first_btr = reg;
1312 }
1313
1314 btrs_live = xcalloc (n_basic_blocks, sizeof (HARD_REG_SET));
1415 "Basic block %d: count = " HOST_WIDEST_INT_PRINT_DEC
1416 " loop-depth = %d idom = %d\n",
1417 i, (HOST_WIDEST_INT) bb->count, bb->loop_depth,
1418 get_immediate_dominator (CDI_DOMINATORS, bb)->index);
1419 }
1420 }
1421
1422 CLEAR_HARD_REG_SET (all_btrs);
1423 for (first_btr = -1, reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
1424 if (TEST_HARD_REG_BIT (reg_class_contents[(int) btr_class], reg)
1425 && (allow_callee_save || call_used_regs[reg] || regs_ever_live[reg]))
1426 {
1427 SET_HARD_REG_BIT (all_btrs, reg);
1428 last_btr = reg;
1429 if (first_btr < 0)
1430 first_btr = reg;
1431 }
1432
1433 btrs_live = xcalloc (n_basic_blocks, sizeof (HARD_REG_SET));
1434 btrs_live_at_end = xcalloc (n_basic_blocks, sizeof (HARD_REG_SET));
1315
1316 build_btr_def_use_webs (all_btr_defs);
1317
1318 while (!fibheap_empty (all_btr_defs))
1319 {
1435
1436 build_btr_def_use_webs (all_btr_defs);
1437
1438 while (!fibheap_empty (all_btr_defs))
1439 {
1320 btr_def def =
1321 (btr_def) fibheap_extract_min (all_btr_defs);
1440 btr_def def = fibheap_extract_min (all_btr_defs);
1322 int min_cost = -fibheap_min_key (all_btr_defs);
1323 if (migrate_btr_def (def, min_cost))
1324 {
1325 fibheap_insert (all_btr_defs, -def->cost, (void *) def);
1441 int min_cost = -fibheap_min_key (all_btr_defs);
1442 if (migrate_btr_def (def, min_cost))
1443 {
1444 fibheap_insert (all_btr_defs, -def->cost, (void *) def);
1326 if (rtl_dump_file)
1445 if (dump_file)
1327 {
1446 {
1328 fprintf (rtl_dump_file,
1447 fprintf (dump_file,
1329 "Putting insn %d back on queue with priority %d\n",
1330 INSN_UID (def->insn), def->cost);
1331 }
1332 }
1333 else
1448 "Putting insn %d back on queue with priority %d\n",
1449 INSN_UID (def->insn), def->cost);
1450 }
1451 }
1452 else
1334 {
1335 if (def->live_range)
1336 BITMAP_XFREE (def->live_range);
1337 }
1453 BITMAP_FREE (def->live_range);
1338 }
1339
1340 free (btrs_live);
1454 }
1455
1456 free (btrs_live);
1457 free (btrs_live_at_end);
1341 obstack_free (&migrate_btrl_obstack, NULL);
1342 fibheap_delete (all_btr_defs);
1343}
1344
1345void
1458 obstack_free (&migrate_btrl_obstack, NULL);
1459 fibheap_delete (all_btr_defs);
1460}
1461
1462void
1346branch_target_load_optimize (rtx insns, bool after_prologue_epilogue_gen)
1463branch_target_load_optimize (bool after_prologue_epilogue_gen)
1347{
1464{
1348 enum reg_class class = (*targetm.branch_target_register_class) ();
1465 enum reg_class class = targetm.branch_target_register_class ();
1349 if (class != NO_REGS)
1350 {
1351 /* Initialize issue_rate. */
1352 if (targetm.sched.issue_rate)
1466 if (class != NO_REGS)
1467 {
1468 /* Initialize issue_rate. */
1469 if (targetm.sched.issue_rate)
1353 issue_rate = (*targetm.sched.issue_rate) ();
1470 issue_rate = targetm.sched.issue_rate ();
1354 else
1355 issue_rate = 1;
1356
1357 /* Build the CFG for migrate_btr_defs. */
1358#if 1
1359 /* This may or may not be needed, depending on where we
1360 run this phase. */
1361 cleanup_cfg (optimize ? CLEANUP_EXPENSIVE : 0);
1362#endif
1363
1471 else
1472 issue_rate = 1;
1473
1474 /* Build the CFG for migrate_btr_defs. */
1475#if 1
1476 /* This may or may not be needed, depending on where we
1477 run this phase. */
1478 cleanup_cfg (optimize ? CLEANUP_EXPENSIVE : 0);
1479#endif
1480
1364 life_analysis (insns, NULL, 0);
1481 life_analysis (0);
1365
1366 /* Dominator info is also needed for migrate_btr_def. */
1367 calculate_dominance_info (CDI_DOMINATORS);
1368 migrate_btr_defs (class,
1482
1483 /* Dominator info is also needed for migrate_btr_def. */
1484 calculate_dominance_info (CDI_DOMINATORS);
1485 migrate_btr_defs (class,
1369 ((*targetm.branch_target_register_callee_saved)
1486 (targetm.branch_target_register_callee_saved
1370 (after_prologue_epilogue_gen)));
1371
1372 free_dominance_info (CDI_DOMINATORS);
1373
1374 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES,
1375 PROP_DEATH_NOTES | PROP_REG_INFO);
1376 }
1377}
1487 (after_prologue_epilogue_gen)));
1488
1489 free_dominance_info (CDI_DOMINATORS);
1490
1491 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES,
1492 PROP_DEATH_NOTES | PROP_REG_INFO);
1493 }
1494}
1495
1496static bool
1497gate_handle_branch_target_load_optimize (void)
1498{
1499 return (optimize > 0 && flag_branch_target_load_optimize2);
1500}
1501
1502
1503static unsigned int
1504rest_of_handle_branch_target_load_optimize (void)
1505{
1506 static int warned = 0;
1507
1508 /* Leave this a warning for now so that it is possible to experiment
1509 with running this pass twice. In 3.6, we should either make this
1510 an error, or use separate dump files. */
1511 if (flag_branch_target_load_optimize
1512 && flag_branch_target_load_optimize2
1513 && !warned)
1514 {
1515 warning (0, "branch target register load optimization is not intended "
1516 "to be run twice");
1517
1518 warned = 1;
1519 }
1520
1521 branch_target_load_optimize (epilogue_completed);
1522 return 0;
1523}
1524
1525struct tree_opt_pass pass_branch_target_load_optimize =
1526{
1527 "btl", /* name */
1528 gate_handle_branch_target_load_optimize, /* gate */
1529 rest_of_handle_branch_target_load_optimize, /* execute */
1530 NULL, /* sub */
1531 NULL, /* next */
1532 0, /* static_pass_number */
1533 0, /* tv_id */
1534 0, /* properties_required */
1535 0, /* properties_provided */
1536 0, /* properties_destroyed */
1537 0, /* todo_flags_start */
1538 TODO_dump_func |
1539 TODO_ggc_collect, /* todo_flags_finish */
1540 'd' /* letter */
1541};
1542