1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
| 1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
|
37 * $FreeBSD: head/sys/i386/isa/nmi.c 77582 2001-06-01 13:23:28Z tmm $
| 37 * $FreeBSD: head/sys/i386/isa/nmi.c 80028 2001-07-20 06:07:34Z takawata $
|
38 */
39
40#include "opt_auto_eoi.h"
41#include "opt_isa.h"
42#include "opt_mca.h"
43
44#include <sys/param.h>
45#include <sys/bus.h>
46#include <sys/errno.h>
47#include <sys/interrupt.h>
48#include <sys/kernel.h>
49#include <sys/kthread.h>
50#include <sys/lock.h>
51#include <sys/malloc.h>
52#include <sys/module.h>
53#include <sys/mutex.h>
54#include <sys/proc.h>
55#include <sys/syslog.h>
56#include <sys/systm.h>
57#include <sys/unistd.h>
58
59#include <machine/md_var.h>
60#include <machine/segments.h>
61
62#if defined(APIC_IO)
63#include <machine/smptests.h> /** FAST_HI */
64#include <machine/smp.h>
65#include <machine/resource.h>
66#endif /* APIC_IO */
67#ifdef PC98
68#include <pc98/pc98/pc98.h>
69#include <pc98/pc98/pc98_machdep.h>
70#include <pc98/pc98/epsonio.h>
71#else
72#include <i386/isa/isa.h>
73#endif
74#include <i386/isa/icu.h>
75
76#ifdef DEV_ISA
77#include <isa/isavar.h>
78#endif
79#include <i386/isa/intr_machdep.h>
80#include <sys/interrupt.h>
81#ifdef APIC_IO
82#include <machine/clock.h>
83#endif
84
85#ifdef DEV_MCA
86#include <i386/isa/mca_machdep.h>
87#endif
88
89/*
90 * Per-interrupt data.
91 */
92u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */
93driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */
94struct ithd *ithds[ICU_LEN]; /* real interrupt handler */
95void *intr_unit[ICU_LEN];
96
97static struct mtx ithds_table_lock; /* protect the ithds table */
98
99static inthand_t *fastintr[ICU_LEN] = {
100 &IDTVEC(fastintr0), &IDTVEC(fastintr1),
101 &IDTVEC(fastintr2), &IDTVEC(fastintr3),
102 &IDTVEC(fastintr4), &IDTVEC(fastintr5),
103 &IDTVEC(fastintr6), &IDTVEC(fastintr7),
104 &IDTVEC(fastintr8), &IDTVEC(fastintr9),
105 &IDTVEC(fastintr10), &IDTVEC(fastintr11),
106 &IDTVEC(fastintr12), &IDTVEC(fastintr13),
107 &IDTVEC(fastintr14), &IDTVEC(fastintr15),
108#if defined(APIC_IO)
109 &IDTVEC(fastintr16), &IDTVEC(fastintr17),
110 &IDTVEC(fastintr18), &IDTVEC(fastintr19),
111 &IDTVEC(fastintr20), &IDTVEC(fastintr21),
112 &IDTVEC(fastintr22), &IDTVEC(fastintr23),
113 &IDTVEC(fastintr24), &IDTVEC(fastintr25),
114 &IDTVEC(fastintr26), &IDTVEC(fastintr27),
115 &IDTVEC(fastintr28), &IDTVEC(fastintr29),
116 &IDTVEC(fastintr30), &IDTVEC(fastintr31),
117#endif /* APIC_IO */
118};
119
120static inthand_t *slowintr[ICU_LEN] = {
121 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
122 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
123 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
124 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15),
125#if defined(APIC_IO)
126 &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
127 &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23),
128 &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27),
129 &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31),
130#endif /* APIC_IO */
131};
132
133static driver_intr_t isa_strayintr;
134
135static void ithds_init(void *dummy);
136static void ithread_enable(int vector);
137static void ithread_disable(int vector);
| 38 */
39
40#include "opt_auto_eoi.h"
41#include "opt_isa.h"
42#include "opt_mca.h"
43
44#include <sys/param.h>
45#include <sys/bus.h>
46#include <sys/errno.h>
47#include <sys/interrupt.h>
48#include <sys/kernel.h>
49#include <sys/kthread.h>
50#include <sys/lock.h>
51#include <sys/malloc.h>
52#include <sys/module.h>
53#include <sys/mutex.h>
54#include <sys/proc.h>
55#include <sys/syslog.h>
56#include <sys/systm.h>
57#include <sys/unistd.h>
58
59#include <machine/md_var.h>
60#include <machine/segments.h>
61
62#if defined(APIC_IO)
63#include <machine/smptests.h> /** FAST_HI */
64#include <machine/smp.h>
65#include <machine/resource.h>
66#endif /* APIC_IO */
67#ifdef PC98
68#include <pc98/pc98/pc98.h>
69#include <pc98/pc98/pc98_machdep.h>
70#include <pc98/pc98/epsonio.h>
71#else
72#include <i386/isa/isa.h>
73#endif
74#include <i386/isa/icu.h>
75
76#ifdef DEV_ISA
77#include <isa/isavar.h>
78#endif
79#include <i386/isa/intr_machdep.h>
80#include <sys/interrupt.h>
81#ifdef APIC_IO
82#include <machine/clock.h>
83#endif
84
85#ifdef DEV_MCA
86#include <i386/isa/mca_machdep.h>
87#endif
88
89/*
90 * Per-interrupt data.
91 */
92u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */
93driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */
94struct ithd *ithds[ICU_LEN]; /* real interrupt handler */
95void *intr_unit[ICU_LEN];
96
97static struct mtx ithds_table_lock; /* protect the ithds table */
98
99static inthand_t *fastintr[ICU_LEN] = {
100 &IDTVEC(fastintr0), &IDTVEC(fastintr1),
101 &IDTVEC(fastintr2), &IDTVEC(fastintr3),
102 &IDTVEC(fastintr4), &IDTVEC(fastintr5),
103 &IDTVEC(fastintr6), &IDTVEC(fastintr7),
104 &IDTVEC(fastintr8), &IDTVEC(fastintr9),
105 &IDTVEC(fastintr10), &IDTVEC(fastintr11),
106 &IDTVEC(fastintr12), &IDTVEC(fastintr13),
107 &IDTVEC(fastintr14), &IDTVEC(fastintr15),
108#if defined(APIC_IO)
109 &IDTVEC(fastintr16), &IDTVEC(fastintr17),
110 &IDTVEC(fastintr18), &IDTVEC(fastintr19),
111 &IDTVEC(fastintr20), &IDTVEC(fastintr21),
112 &IDTVEC(fastintr22), &IDTVEC(fastintr23),
113 &IDTVEC(fastintr24), &IDTVEC(fastintr25),
114 &IDTVEC(fastintr26), &IDTVEC(fastintr27),
115 &IDTVEC(fastintr28), &IDTVEC(fastintr29),
116 &IDTVEC(fastintr30), &IDTVEC(fastintr31),
117#endif /* APIC_IO */
118};
119
120static inthand_t *slowintr[ICU_LEN] = {
121 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
122 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
123 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
124 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15),
125#if defined(APIC_IO)
126 &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
127 &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23),
128 &IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27),
129 &IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31),
130#endif /* APIC_IO */
131};
132
133static driver_intr_t isa_strayintr;
134
135static void ithds_init(void *dummy);
136static void ithread_enable(int vector);
137static void ithread_disable(int vector);
|
| 138static void init_i8259(void);
|
138
139#ifdef PC98
140#define NMI_PARITY 0x04
141#define NMI_EPARITY 0x02
142#else
143#define NMI_PARITY (1 << 7)
144#define NMI_IOCHAN (1 << 6)
145#define ENMI_WATCHDOG (1 << 7)
146#define ENMI_BUSTIMER (1 << 6)
147#define ENMI_IOSTATUS (1 << 5)
148#endif
149
150/*
151 * Bus attachment for the ISA PIC.
152 */
153static struct isa_pnp_id atpic_ids[] = {
154 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
155 { 0 }
156};
157
158static int
159atpic_probe(device_t dev)
160{
161 int result;
162
163 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
164 device_quiet(dev);
165 return(result);
166}
167
168/*
169 * In the APIC_IO case we might be granted IRQ 2, as this is typically
170 * consumed by chaining between the two PIC components. If we're using
171 * the APIC, however, this may not be the case, and as such we should
172 * free the resource. (XXX untested)
173 *
174 * The generic ISA attachment code will handle allocating any other resources
175 * that we don't explicitly claim here.
176 */
177static int
178atpic_attach(device_t dev)
179{
180#ifdef APIC_IO
181 int rid;
182 struct resource *res;
183
184 /* try to allocate our IRQ and then free it */
185 rid = 0;
186 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
187 if (res != NULL)
188 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
189#endif
190 return(0);
191}
192
193static device_method_t atpic_methods[] = {
194 /* Device interface */
195 DEVMETHOD(device_probe, atpic_probe),
196 DEVMETHOD(device_attach, atpic_attach),
197 DEVMETHOD(device_detach, bus_generic_detach),
198 DEVMETHOD(device_shutdown, bus_generic_shutdown),
199 DEVMETHOD(device_suspend, bus_generic_suspend),
200 DEVMETHOD(device_resume, bus_generic_resume),
201 { 0, 0 }
202};
203
204static driver_t atpic_driver = {
205 "atpic",
206 atpic_methods,
207 1, /* no softc */
208};
209
210static devclass_t atpic_devclass;
211
212DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
213
214/*
215 * Handle a NMI, possibly a machine check.
216 * return true to panic system, false to ignore.
217 */
218int
219isa_nmi(cd)
220 int cd;
221{
222 int retval = 0;
223#ifdef PC98
224 int port = inb(0x33);
225
226 log(LOG_CRIT, "NMI PC98 port = %x\n", port);
227 if (epson_machine_id == 0x20)
228 epson_outb(0xc16, epson_inb(0xc16) | 0x1);
229 if (port & NMI_PARITY) {
230 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
231 retval = 1;
232 } else if (port & NMI_EPARITY) {
233 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
234 retval = 1;
235 } else {
236 log(LOG_CRIT, "\nNMI Resume ??\n");
237 }
238#else /* IBM-PC */
239 int isa_port = inb(0x61);
240 int eisa_port = inb(0x461);
241
242 log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
243#ifdef DEV_MCA
244 if (MCA_system && mca_bus_nmi())
245 return(0);
246#endif
247
248 if (isa_port & NMI_PARITY) {
249 log(LOG_CRIT, "RAM parity error, likely hardware failure.");
250 retval = 1;
251 }
252
253 if (isa_port & NMI_IOCHAN) {
254 log(LOG_CRIT, "I/O channel check, likely hardware failure.");
255 retval = 1;
256 }
257
258 /*
259 * On a real EISA machine, this will never happen. However it can
260 * happen on ISA machines which implement XT style floating point
261 * error handling (very rare). Save them from a meaningless panic.
262 */
263 if (eisa_port == 0xff)
264 return(retval);
265
266 if (eisa_port & ENMI_WATCHDOG) {
267 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
268 retval = 1;
269 }
270
271 if (eisa_port & ENMI_BUSTIMER) {
272 log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
273 retval = 1;
274 }
275
276 if (eisa_port & ENMI_IOSTATUS) {
277 log(LOG_CRIT, "EISA I/O port status error.");
278 retval = 1;
279 }
280#endif
281 return(retval);
282}
283
284/*
| 139
140#ifdef PC98
141#define NMI_PARITY 0x04
142#define NMI_EPARITY 0x02
143#else
144#define NMI_PARITY (1 << 7)
145#define NMI_IOCHAN (1 << 6)
146#define ENMI_WATCHDOG (1 << 7)
147#define ENMI_BUSTIMER (1 << 6)
148#define ENMI_IOSTATUS (1 << 5)
149#endif
150
151/*
152 * Bus attachment for the ISA PIC.
153 */
154static struct isa_pnp_id atpic_ids[] = {
155 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
156 { 0 }
157};
158
159static int
160atpic_probe(device_t dev)
161{
162 int result;
163
164 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
165 device_quiet(dev);
166 return(result);
167}
168
169/*
170 * In the APIC_IO case we might be granted IRQ 2, as this is typically
171 * consumed by chaining between the two PIC components. If we're using
172 * the APIC, however, this may not be the case, and as such we should
173 * free the resource. (XXX untested)
174 *
175 * The generic ISA attachment code will handle allocating any other resources
176 * that we don't explicitly claim here.
177 */
178static int
179atpic_attach(device_t dev)
180{
181#ifdef APIC_IO
182 int rid;
183 struct resource *res;
184
185 /* try to allocate our IRQ and then free it */
186 rid = 0;
187 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
188 if (res != NULL)
189 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
190#endif
191 return(0);
192}
193
194static device_method_t atpic_methods[] = {
195 /* Device interface */
196 DEVMETHOD(device_probe, atpic_probe),
197 DEVMETHOD(device_attach, atpic_attach),
198 DEVMETHOD(device_detach, bus_generic_detach),
199 DEVMETHOD(device_shutdown, bus_generic_shutdown),
200 DEVMETHOD(device_suspend, bus_generic_suspend),
201 DEVMETHOD(device_resume, bus_generic_resume),
202 { 0, 0 }
203};
204
205static driver_t atpic_driver = {
206 "atpic",
207 atpic_methods,
208 1, /* no softc */
209};
210
211static devclass_t atpic_devclass;
212
213DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
214
215/*
216 * Handle a NMI, possibly a machine check.
217 * return true to panic system, false to ignore.
218 */
219int
220isa_nmi(cd)
221 int cd;
222{
223 int retval = 0;
224#ifdef PC98
225 int port = inb(0x33);
226
227 log(LOG_CRIT, "NMI PC98 port = %x\n", port);
228 if (epson_machine_id == 0x20)
229 epson_outb(0xc16, epson_inb(0xc16) | 0x1);
230 if (port & NMI_PARITY) {
231 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
232 retval = 1;
233 } else if (port & NMI_EPARITY) {
234 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
235 retval = 1;
236 } else {
237 log(LOG_CRIT, "\nNMI Resume ??\n");
238 }
239#else /* IBM-PC */
240 int isa_port = inb(0x61);
241 int eisa_port = inb(0x461);
242
243 log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
244#ifdef DEV_MCA
245 if (MCA_system && mca_bus_nmi())
246 return(0);
247#endif
248
249 if (isa_port & NMI_PARITY) {
250 log(LOG_CRIT, "RAM parity error, likely hardware failure.");
251 retval = 1;
252 }
253
254 if (isa_port & NMI_IOCHAN) {
255 log(LOG_CRIT, "I/O channel check, likely hardware failure.");
256 retval = 1;
257 }
258
259 /*
260 * On a real EISA machine, this will never happen. However it can
261 * happen on ISA machines which implement XT style floating point
262 * error handling (very rare). Save them from a meaningless panic.
263 */
264 if (eisa_port == 0xff)
265 return(retval);
266
267 if (eisa_port & ENMI_WATCHDOG) {
268 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
269 retval = 1;
270 }
271
272 if (eisa_port & ENMI_BUSTIMER) {
273 log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
274 retval = 1;
275 }
276
277 if (eisa_port & ENMI_IOSTATUS) {
278 log(LOG_CRIT, "EISA I/O port status error.");
279 retval = 1;
280 }
281#endif
282 return(retval);
283}
284
285/*
|
| 286 * ICU reinitialize when ICU configuration has lost.
287 */
288void icu_reinit()
289{
290 int i;
291 u_int32_t eflags;
292 eflags = read_eflags();
293 disable_intr();
294 init_i8259();
295 for(i=0;i<ICU_LEN;i++)
296 if(intr_handler[i] != isa_strayintr)
297 INTREN(1<<i);
298 write_eflags(eflags);
299}
300
301/*
|
285 * Create a default interrupt table to avoid problems caused by
286 * spurious interrupts during configuration of kernel, then setup
287 * interrupt control unit.
288 */
289void
290isa_defaultirq()
291{
292 int i;
293
294 /* icu vectors */
295 for (i = 0; i < ICU_LEN; i++)
296 icu_unset(i, (driver_intr_t *)NULL);
| 302 * Create a default interrupt table to avoid problems caused by
303 * spurious interrupts during configuration of kernel, then setup
304 * interrupt control unit.
305 */
306void
307isa_defaultirq()
308{
309 int i;
310
311 /* icu vectors */
312 for (i = 0; i < ICU_LEN; i++)
313 icu_unset(i, (driver_intr_t *)NULL);
|
| 314 init_i8259();
315}
|
297
| 316
|
298 /* initialize 8259's */
| 317
318/*
319 *initialize 8259's
320 */
321static void init_i8259()
322{
323
|
299#ifdef DEV_MCA
300 if (MCA_system)
301 outb(IO_ICU1, 0x19); /* reset; program device, four bytes */
302 else
303#endif
304 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
305
306 outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
307 outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
308#ifdef PC98
309#ifdef AUTO_EOI_1
310 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
311#else
312 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
313#endif
314#else /* IBM-PC */
315#ifdef AUTO_EOI_1
316 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
317#else
318 outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
319#endif
320#endif /* PC98 */
321 outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
322 outb(IO_ICU1, 0x0a); /* default to IRR on read */
323#ifndef PC98
324 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
325#endif /* !PC98 */
326
327#ifdef DEV_MCA
328 if (MCA_system)
329 outb(IO_ICU2, 0x19); /* reset; program device, four bytes */
330 else
331#endif
332 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
333
334 outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
335 outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
336#ifdef PC98
337 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
338#else /* IBM-PC */
339#ifdef AUTO_EOI_2
340 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
341#else
342 outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
343#endif
344#endif /* PC98 */
345 outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
346 outb(IO_ICU2, 0x0a); /* default to IRR on read */
347}
348
349/*
350 * Caught a stray interrupt, notify
351 */
352static void
353isa_strayintr(vcookiep)
354 void *vcookiep;
355{
356 int intr = (void **)vcookiep - &intr_unit[0];
357
358 /*
359 * XXX TODO print a different message for #7 if it is for a
360 * glitch. Glitches can be distinguished from real #7's by
361 * testing that the in-service bit is _not_ set. The test
362 * must be done before sending an EOI so it can't be done if
363 * we are using AUTO_EOI_1.
364 */
365 if (intrcnt[1 + intr] <= 5)
366 log(LOG_ERR, "stray irq %d\n", intr);
367 if (intrcnt[1 + intr] == 5)
368 log(LOG_CRIT,
369 "too many stray irq %d's; not logging any more\n", intr);
370}
371
372#ifdef DEV_ISA
373/*
374 * Return a bitmap of the current interrupt requests. This is 8259-specific
375 * and is only suitable for use at probe time.
376 */
377intrmask_t
378isa_irq_pending()
379{
380 u_char irr1;
381 u_char irr2;
382
383 irr1 = inb(IO_ICU1);
384 irr2 = inb(IO_ICU2);
385 return ((irr2 << 8) | irr1);
386}
387#endif
388
389/*
390 * Update intrnames array with the specified name. This is used by
391 * vmstat(8) and the like.
392 */
393static void
394update_intrname(int intr, const char *name)
395{
396 char buf[32];
397 char *cp;
398 int name_index, off, strayintr;
399
400 /*
401 * Initialise strings for bitbucket and stray interrupt counters.
402 * These have statically allocated indices 0 and 1 through ICU_LEN.
403 */
404 if (intrnames[0] == '\0') {
405 off = sprintf(intrnames, "???") + 1;
406 for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
407 off += sprintf(intrnames + off, "stray irq%d",
408 strayintr) + 1;
409 }
410
411 if (name == NULL)
412 name = "???";
413 if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
414 goto use_bitbucket;
415
416 /*
417 * Search for `buf' in `intrnames'. In the usual case when it is
418 * not found, append it to the end if there is enough space (the \0
419 * terminator for the previous string, if any, becomes a separator).
420 */
421 for (cp = intrnames, name_index = 0;
422 cp != eintrnames && name_index < NR_INTRNAMES;
423 cp += strlen(cp) + 1, name_index++) {
424 if (*cp == '\0') {
425 if (strlen(buf) >= eintrnames - cp)
426 break;
427 strcpy(cp, buf);
428 goto found;
429 }
430 if (strcmp(cp, buf) == 0)
431 goto found;
432 }
433
434use_bitbucket:
435 printf("update_intrname: counting %s irq%d as %s\n", name, intr,
436 intrnames);
437 name_index = 0;
438found:
439 intr_countp[intr] = &intrcnt[name_index];
440}
441
442int
443icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
444{
445#ifdef FAST_HI
446 int select; /* the select register is 8 bits */
447 int vector;
448 u_int32_t value; /* the window register is 32 bits */
449#endif /* FAST_HI */
450 u_long ef;
451
452#if defined(APIC_IO)
453 if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
454#else
455 if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
456#endif /* APIC_IO */
457 if (intr_handler[intr] != isa_strayintr)
458 return (EBUSY);
459
460 ef = read_eflags();
461 disable_intr();
462 intr_handler[intr] = handler;
463 intr_unit[intr] = arg;
464#ifdef FAST_HI
465 if (flags & INTR_FAST) {
466 vector = TPR_FAST_INTS + intr;
467 setidt(vector, fastintr[intr],
468 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
469 }
470 else {
471 vector = TPR_SLOW_INTS + intr;
472#ifdef APIC_INTR_REORDER
473#ifdef APIC_INTR_HIGHPRI_CLOCK
474 /* XXX: Hack (kludge?) for more accurate clock. */
475 if (intr == apic_8254_intr || intr == 8) {
476 vector = TPR_FAST_INTS + intr;
477 }
478#endif
479#endif
480 setidt(vector, slowintr[intr],
481 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
482 }
483#ifdef APIC_INTR_REORDER
484 set_lapic_isrloc(intr, vector);
485#endif
486 /*
487 * Reprogram the vector in the IO APIC.
488 */
489 if (int_to_apicintpin[intr].ioapic >= 0) {
490 select = int_to_apicintpin[intr].redirindex;
491 value = io_apic_read(int_to_apicintpin[intr].ioapic,
492 select) & ~IOART_INTVEC;
493 io_apic_write(int_to_apicintpin[intr].ioapic,
494 select, value | vector);
495 }
496#else
497 setidt(ICU_OFFSET + intr,
498 flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
499 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
500#endif /* FAST_HI */
501 INTREN(1 << intr);
502 write_eflags(ef);
503 return (0);
504}
505
506/*
507 * Dissociate an interrupt handler from an IRQ and set the handler to
508 * the stray interrupt handler. The 'handler' parameter is used only
509 * for consistency checking.
510 */
511int
512icu_unset(intr, handler)
513 int intr;
514 driver_intr_t *handler;
515{
516 u_long ef;
517
518 if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
519 return (EINVAL);
520
521 INTRDIS(1 << intr);
522 ef = read_eflags();
523 disable_intr();
524 intr_countp[intr] = &intrcnt[1 + intr];
525 intr_handler[intr] = isa_strayintr;
526 intr_unit[intr] = &intr_unit[intr];
527#ifdef FAST_HI_XXX
528 /* XXX how do I re-create dvp here? */
529 setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
530 slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
531#else /* FAST_HI */
532#ifdef APIC_INTR_REORDER
533 set_lapic_isrloc(intr, ICU_OFFSET + intr);
534#endif
535 setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
536 GSEL(GCODE_SEL, SEL_KPL));
537#endif /* FAST_HI */
538 write_eflags(ef);
539 return (0);
540}
541
542static void
543ithds_init(void *dummy)
544{
545
546 mtx_init(&ithds_table_lock, "ithread table lock", MTX_SPIN);
547}
548SYSINIT(ithds_init, SI_SUB_INTR, SI_ORDER_SECOND, ithds_init, NULL);
549
550static void
551ithread_enable(int vector)
552{
553
554 INTREN(1 << vector);
555}
556
557static void
558ithread_disable(int vector)
559{
560
561 INTRDIS(1 << vector);
562}
563
564int
565inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
566 enum intr_type flags, void **cookiep)
567{
568 struct ithd *ithd; /* descriptor for the IRQ */
569 int errcode = 0;
570 int created_ithd = 0;
571
572 /*
573 * Work around a race where more than one CPU may be registering
574 * handlers on the same IRQ at the same time.
575 */
576 mtx_lock_spin(&ithds_table_lock);
577 ithd = ithds[irq];
578 mtx_unlock_spin(&ithds_table_lock);
579 if (ithd == NULL) {
580 errcode = ithread_create(&ithd, irq, 0, ithread_disable,
581 ithread_enable, "irq%d:", irq);
582 if (errcode)
583 return (errcode);
584 mtx_lock_spin(&ithds_table_lock);
585 if (ithds[irq] == NULL) {
586 ithds[irq] = ithd;
587 created_ithd++;
588 mtx_unlock_spin(&ithds_table_lock);
589 } else {
590 struct ithd *orphan;
591
592 orphan = ithd;
593 ithd = ithds[irq];
594 mtx_unlock_spin(&ithds_table_lock);
595 ithread_destroy(orphan);
596 }
597 }
598
599 errcode = ithread_add_handler(ithd, name, handler, arg,
600 ithread_priority(flags), flags, cookiep);
601
602 if ((flags & INTR_FAST) == 0 || errcode)
603 /*
604 * The interrupt process must be in place, but
605 * not necessarily schedulable, before we
606 * initialize the ICU, since it may cause an
607 * immediate interrupt.
608 */
609 if (icu_setup(irq, &sched_ithd, arg, flags) != 0)
610 panic("inthand_add: Can't initialize ICU");
611
612 if (errcode)
613 return (errcode);
614
615 if (flags & INTR_FAST) {
616 errcode = icu_setup(irq, handler, arg, flags);
617 if (errcode && bootverbose)
618 printf("\tinthand_add(irq%d) failed, result=%d\n",
619 irq, errcode);
620 if (errcode)
621 return (errcode);
622 }
623
624 update_intrname(irq, name);
625 return (0);
626}
627
628/*
629 * Deactivate and remove linked list the interrupt handler descriptor
630 * data connected created by an earlier call of inthand_add(), then
631 * adjust the interrupt masks if necessary.
632 *
633 * Return the memory held by the interrupt handler descriptor data
634 * structure to the system. First ensure the handler is not actively
635 * in use.
636 */
637int
638inthand_remove(void *cookie)
639{
640
641 return (ithread_remove_handler(cookie));
642}
| 324#ifdef DEV_MCA
325 if (MCA_system)
326 outb(IO_ICU1, 0x19); /* reset; program device, four bytes */
327 else
328#endif
329 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
330
331 outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
332 outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
333#ifdef PC98
334#ifdef AUTO_EOI_1
335 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
336#else
337 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
338#endif
339#else /* IBM-PC */
340#ifdef AUTO_EOI_1
341 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
342#else
343 outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
344#endif
345#endif /* PC98 */
346 outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
347 outb(IO_ICU1, 0x0a); /* default to IRR on read */
348#ifndef PC98
349 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
350#endif /* !PC98 */
351
352#ifdef DEV_MCA
353 if (MCA_system)
354 outb(IO_ICU2, 0x19); /* reset; program device, four bytes */
355 else
356#endif
357 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
358
359 outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
360 outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
361#ifdef PC98
362 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
363#else /* IBM-PC */
364#ifdef AUTO_EOI_2
365 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
366#else
367 outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
368#endif
369#endif /* PC98 */
370 outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
371 outb(IO_ICU2, 0x0a); /* default to IRR on read */
372}
373
374/*
375 * Caught a stray interrupt, notify
376 */
377static void
378isa_strayintr(vcookiep)
379 void *vcookiep;
380{
381 int intr = (void **)vcookiep - &intr_unit[0];
382
383 /*
384 * XXX TODO print a different message for #7 if it is for a
385 * glitch. Glitches can be distinguished from real #7's by
386 * testing that the in-service bit is _not_ set. The test
387 * must be done before sending an EOI so it can't be done if
388 * we are using AUTO_EOI_1.
389 */
390 if (intrcnt[1 + intr] <= 5)
391 log(LOG_ERR, "stray irq %d\n", intr);
392 if (intrcnt[1 + intr] == 5)
393 log(LOG_CRIT,
394 "too many stray irq %d's; not logging any more\n", intr);
395}
396
397#ifdef DEV_ISA
398/*
399 * Return a bitmap of the current interrupt requests. This is 8259-specific
400 * and is only suitable for use at probe time.
401 */
402intrmask_t
403isa_irq_pending()
404{
405 u_char irr1;
406 u_char irr2;
407
408 irr1 = inb(IO_ICU1);
409 irr2 = inb(IO_ICU2);
410 return ((irr2 << 8) | irr1);
411}
412#endif
413
414/*
415 * Update intrnames array with the specified name. This is used by
416 * vmstat(8) and the like.
417 */
418static void
419update_intrname(int intr, const char *name)
420{
421 char buf[32];
422 char *cp;
423 int name_index, off, strayintr;
424
425 /*
426 * Initialise strings for bitbucket and stray interrupt counters.
427 * These have statically allocated indices 0 and 1 through ICU_LEN.
428 */
429 if (intrnames[0] == '\0') {
430 off = sprintf(intrnames, "???") + 1;
431 for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
432 off += sprintf(intrnames + off, "stray irq%d",
433 strayintr) + 1;
434 }
435
436 if (name == NULL)
437 name = "???";
438 if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
439 goto use_bitbucket;
440
441 /*
442 * Search for `buf' in `intrnames'. In the usual case when it is
443 * not found, append it to the end if there is enough space (the \0
444 * terminator for the previous string, if any, becomes a separator).
445 */
446 for (cp = intrnames, name_index = 0;
447 cp != eintrnames && name_index < NR_INTRNAMES;
448 cp += strlen(cp) + 1, name_index++) {
449 if (*cp == '\0') {
450 if (strlen(buf) >= eintrnames - cp)
451 break;
452 strcpy(cp, buf);
453 goto found;
454 }
455 if (strcmp(cp, buf) == 0)
456 goto found;
457 }
458
459use_bitbucket:
460 printf("update_intrname: counting %s irq%d as %s\n", name, intr,
461 intrnames);
462 name_index = 0;
463found:
464 intr_countp[intr] = &intrcnt[name_index];
465}
466
467int
468icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
469{
470#ifdef FAST_HI
471 int select; /* the select register is 8 bits */
472 int vector;
473 u_int32_t value; /* the window register is 32 bits */
474#endif /* FAST_HI */
475 u_long ef;
476
477#if defined(APIC_IO)
478 if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
479#else
480 if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
481#endif /* APIC_IO */
482 if (intr_handler[intr] != isa_strayintr)
483 return (EBUSY);
484
485 ef = read_eflags();
486 disable_intr();
487 intr_handler[intr] = handler;
488 intr_unit[intr] = arg;
489#ifdef FAST_HI
490 if (flags & INTR_FAST) {
491 vector = TPR_FAST_INTS + intr;
492 setidt(vector, fastintr[intr],
493 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
494 }
495 else {
496 vector = TPR_SLOW_INTS + intr;
497#ifdef APIC_INTR_REORDER
498#ifdef APIC_INTR_HIGHPRI_CLOCK
499 /* XXX: Hack (kludge?) for more accurate clock. */
500 if (intr == apic_8254_intr || intr == 8) {
501 vector = TPR_FAST_INTS + intr;
502 }
503#endif
504#endif
505 setidt(vector, slowintr[intr],
506 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
507 }
508#ifdef APIC_INTR_REORDER
509 set_lapic_isrloc(intr, vector);
510#endif
511 /*
512 * Reprogram the vector in the IO APIC.
513 */
514 if (int_to_apicintpin[intr].ioapic >= 0) {
515 select = int_to_apicintpin[intr].redirindex;
516 value = io_apic_read(int_to_apicintpin[intr].ioapic,
517 select) & ~IOART_INTVEC;
518 io_apic_write(int_to_apicintpin[intr].ioapic,
519 select, value | vector);
520 }
521#else
522 setidt(ICU_OFFSET + intr,
523 flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
524 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
525#endif /* FAST_HI */
526 INTREN(1 << intr);
527 write_eflags(ef);
528 return (0);
529}
530
531/*
532 * Dissociate an interrupt handler from an IRQ and set the handler to
533 * the stray interrupt handler. The 'handler' parameter is used only
534 * for consistency checking.
535 */
536int
537icu_unset(intr, handler)
538 int intr;
539 driver_intr_t *handler;
540{
541 u_long ef;
542
543 if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
544 return (EINVAL);
545
546 INTRDIS(1 << intr);
547 ef = read_eflags();
548 disable_intr();
549 intr_countp[intr] = &intrcnt[1 + intr];
550 intr_handler[intr] = isa_strayintr;
551 intr_unit[intr] = &intr_unit[intr];
552#ifdef FAST_HI_XXX
553 /* XXX how do I re-create dvp here? */
554 setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
555 slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
556#else /* FAST_HI */
557#ifdef APIC_INTR_REORDER
558 set_lapic_isrloc(intr, ICU_OFFSET + intr);
559#endif
560 setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
561 GSEL(GCODE_SEL, SEL_KPL));
562#endif /* FAST_HI */
563 write_eflags(ef);
564 return (0);
565}
566
567static void
568ithds_init(void *dummy)
569{
570
571 mtx_init(&ithds_table_lock, "ithread table lock", MTX_SPIN);
572}
573SYSINIT(ithds_init, SI_SUB_INTR, SI_ORDER_SECOND, ithds_init, NULL);
574
575static void
576ithread_enable(int vector)
577{
578
579 INTREN(1 << vector);
580}
581
582static void
583ithread_disable(int vector)
584{
585
586 INTRDIS(1 << vector);
587}
588
589int
590inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
591 enum intr_type flags, void **cookiep)
592{
593 struct ithd *ithd; /* descriptor for the IRQ */
594 int errcode = 0;
595 int created_ithd = 0;
596
597 /*
598 * Work around a race where more than one CPU may be registering
599 * handlers on the same IRQ at the same time.
600 */
601 mtx_lock_spin(&ithds_table_lock);
602 ithd = ithds[irq];
603 mtx_unlock_spin(&ithds_table_lock);
604 if (ithd == NULL) {
605 errcode = ithread_create(&ithd, irq, 0, ithread_disable,
606 ithread_enable, "irq%d:", irq);
607 if (errcode)
608 return (errcode);
609 mtx_lock_spin(&ithds_table_lock);
610 if (ithds[irq] == NULL) {
611 ithds[irq] = ithd;
612 created_ithd++;
613 mtx_unlock_spin(&ithds_table_lock);
614 } else {
615 struct ithd *orphan;
616
617 orphan = ithd;
618 ithd = ithds[irq];
619 mtx_unlock_spin(&ithds_table_lock);
620 ithread_destroy(orphan);
621 }
622 }
623
624 errcode = ithread_add_handler(ithd, name, handler, arg,
625 ithread_priority(flags), flags, cookiep);
626
627 if ((flags & INTR_FAST) == 0 || errcode)
628 /*
629 * The interrupt process must be in place, but
630 * not necessarily schedulable, before we
631 * initialize the ICU, since it may cause an
632 * immediate interrupt.
633 */
634 if (icu_setup(irq, &sched_ithd, arg, flags) != 0)
635 panic("inthand_add: Can't initialize ICU");
636
637 if (errcode)
638 return (errcode);
639
640 if (flags & INTR_FAST) {
641 errcode = icu_setup(irq, handler, arg, flags);
642 if (errcode && bootverbose)
643 printf("\tinthand_add(irq%d) failed, result=%d\n",
644 irq, errcode);
645 if (errcode)
646 return (errcode);
647 }
648
649 update_intrname(irq, name);
650 return (0);
651}
652
653/*
654 * Deactivate and remove linked list the interrupt handler descriptor
655 * data connected created by an earlier call of inthand_add(), then
656 * adjust the interrupt masks if necessary.
657 *
658 * Return the memory held by the interrupt handler descriptor data
659 * structure to the system. First ensure the handler is not actively
660 * in use.
661 */
662int
663inthand_remove(void *cookie)
664{
665
666 return (ithread_remove_handler(cookie));
667}
|