1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
| 1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
|
37 * $FreeBSD: head/sys/isa/atrtc.c 71797 2001-01-29 11:57:27Z peter $
| 37 * $FreeBSD: head/sys/isa/atrtc.c 72200 2001-02-09 06:11:45Z bmilekic $
|
38 */
39
40/*
41 * Routines to handle clock hardware.
42 */
43
44/*
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
47 *
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49 */
50
51#include "opt_clock.h"
52#include "opt_apm.h"
53#include "opt_mca.h"
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/bus.h>
58#include <sys/ipl.h>
59#include <sys/mutex.h>
60#include <sys/proc.h>
61#include <sys/time.h>
62#include <sys/timetc.h>
63#include <sys/kernel.h>
64#ifndef SMP
65#include <sys/lock.h>
66#endif
67#include <sys/sysctl.h>
68#include <sys/cons.h>
69
70#include <machine/clock.h>
71#ifdef CLK_CALIBRATION_LOOP
72#endif
73#include <machine/cputypes.h>
74#include <machine/frame.h>
75#include <machine/limits.h>
76#include <machine/md_var.h>
77#include <machine/psl.h>
78#ifdef APIC_IO
79#include <machine/segments.h>
80#endif
81#if defined(SMP) || defined(APIC_IO)
82#include <machine/smp.h>
83#endif /* SMP || APIC_IO */
84#include <machine/specialreg.h>
85
86#include <i386/isa/icu.h>
87#include <i386/isa/isa.h>
88#include <isa/rtc.h>
89#include <isa/isavar.h>
90#include <i386/isa/timerreg.h>
91
92#include <i386/isa/intr_machdep.h>
93
94#ifdef DEV_MCA
95#include <i386/isa/mca_machdep.h>
96#endif
97
98#ifdef APIC_IO
99#include <i386/isa/intr_machdep.h>
100/* The interrupt triggered by the 8254 (timer) chip */
101int apic_8254_intr;
102static u_long read_intr_count __P((int vec));
103static void setup_8254_mixed_mode __P((void));
104#endif
105
106/*
107 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
108 * can use a simple formula for leap years.
109 */
110#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
111#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
112
113#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
114
115/*
116 * Time in timer cycles that it takes for microtime() to disable interrupts
117 * and latch the count. microtime() currently uses "cli; outb ..." so it
118 * normally takes less than 2 timer cycles. Add a few for cache misses.
119 * Add a few more to allow for latency in bogus calls to microtime() with
120 * interrupts already disabled.
121 */
122#define TIMER0_LATCH_COUNT 20
123
124/*
125 * Maximum frequency that we are willing to allow for timer0. Must be
126 * low enough to guarantee that the timer interrupt handler returns
127 * before the next timer interrupt.
128 */
129#define TIMER0_MAX_FREQ 20000
130
131int adjkerntz; /* local offset from GMT in seconds */
132int clkintr_pending;
133int disable_rtc_set; /* disable resettodr() if != 0 */
134int statclock_disable;
135#ifndef TIMER_FREQ
136#define TIMER_FREQ 1193182
137#endif
138u_int timer_freq = TIMER_FREQ;
139int timer0_max_count;
140u_int tsc_freq;
141int tsc_is_broken;
142int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
143struct mtx clock_lock;
144
145static int beeping = 0;
146static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
147static u_int hardclock_max_count;
148static u_int32_t i8254_lastcount;
149static u_int32_t i8254_offset;
150static int i8254_ticked;
151/*
152 * XXX new_function and timer_func should not handle clockframes, but
153 * timer_func currently needs to hold hardclock to handle the
154 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
155 * to switch between clkintr() and a slightly different timerintr().
156 */
157static void (*new_function) __P((struct clockframe *frame));
158static u_int new_rate;
159static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
160static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
161static u_int timer0_prescaler_count;
162
163/* Values for timerX_state: */
164#define RELEASED 0
165#define RELEASE_PENDING 1
166#define ACQUIRED 2
167#define ACQUIRE_PENDING 3
168
169static u_char timer0_state;
170static u_char timer2_state;
171static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
172#if defined(I386_CPU) || defined(I486_CPU)
173 u_int tsc_present; /* Not static; other parts of the kernel
174 * Need to know this */
175#else
176static u_int tsc_present;
177#endif
178
179static unsigned i8254_get_timecount __P((struct timecounter *tc));
180static unsigned tsc_get_timecount __P((struct timecounter *tc));
181static void set_timer_freq(u_int freq, int intr_freq);
182
183static struct timecounter tsc_timecounter = {
184 tsc_get_timecount, /* get_timecount */
185 0, /* no poll_pps */
186 ~0u, /* counter_mask */
187 0, /* frequency */
188 "TSC" /* name */
189};
190
191SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
192 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
193
194static struct timecounter i8254_timecounter = {
195 i8254_get_timecount, /* get_timecount */
196 0, /* no poll_pps */
197 ~0u, /* counter_mask */
198 0, /* frequency */
199 "i8254" /* name */
200};
201
202SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
203 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
204
205static void
206clkintr(struct clockframe frame)
207{
208
209 if (timecounter->tc_get_timecount == i8254_get_timecount) {
| 38 */
39
40/*
41 * Routines to handle clock hardware.
42 */
43
44/*
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
47 *
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49 */
50
51#include "opt_clock.h"
52#include "opt_apm.h"
53#include "opt_mca.h"
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/bus.h>
58#include <sys/ipl.h>
59#include <sys/mutex.h>
60#include <sys/proc.h>
61#include <sys/time.h>
62#include <sys/timetc.h>
63#include <sys/kernel.h>
64#ifndef SMP
65#include <sys/lock.h>
66#endif
67#include <sys/sysctl.h>
68#include <sys/cons.h>
69
70#include <machine/clock.h>
71#ifdef CLK_CALIBRATION_LOOP
72#endif
73#include <machine/cputypes.h>
74#include <machine/frame.h>
75#include <machine/limits.h>
76#include <machine/md_var.h>
77#include <machine/psl.h>
78#ifdef APIC_IO
79#include <machine/segments.h>
80#endif
81#if defined(SMP) || defined(APIC_IO)
82#include <machine/smp.h>
83#endif /* SMP || APIC_IO */
84#include <machine/specialreg.h>
85
86#include <i386/isa/icu.h>
87#include <i386/isa/isa.h>
88#include <isa/rtc.h>
89#include <isa/isavar.h>
90#include <i386/isa/timerreg.h>
91
92#include <i386/isa/intr_machdep.h>
93
94#ifdef DEV_MCA
95#include <i386/isa/mca_machdep.h>
96#endif
97
98#ifdef APIC_IO
99#include <i386/isa/intr_machdep.h>
100/* The interrupt triggered by the 8254 (timer) chip */
101int apic_8254_intr;
102static u_long read_intr_count __P((int vec));
103static void setup_8254_mixed_mode __P((void));
104#endif
105
106/*
107 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
108 * can use a simple formula for leap years.
109 */
110#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
111#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
112
113#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
114
115/*
116 * Time in timer cycles that it takes for microtime() to disable interrupts
117 * and latch the count. microtime() currently uses "cli; outb ..." so it
118 * normally takes less than 2 timer cycles. Add a few for cache misses.
119 * Add a few more to allow for latency in bogus calls to microtime() with
120 * interrupts already disabled.
121 */
122#define TIMER0_LATCH_COUNT 20
123
124/*
125 * Maximum frequency that we are willing to allow for timer0. Must be
126 * low enough to guarantee that the timer interrupt handler returns
127 * before the next timer interrupt.
128 */
129#define TIMER0_MAX_FREQ 20000
130
131int adjkerntz; /* local offset from GMT in seconds */
132int clkintr_pending;
133int disable_rtc_set; /* disable resettodr() if != 0 */
134int statclock_disable;
135#ifndef TIMER_FREQ
136#define TIMER_FREQ 1193182
137#endif
138u_int timer_freq = TIMER_FREQ;
139int timer0_max_count;
140u_int tsc_freq;
141int tsc_is_broken;
142int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
143struct mtx clock_lock;
144
145static int beeping = 0;
146static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
147static u_int hardclock_max_count;
148static u_int32_t i8254_lastcount;
149static u_int32_t i8254_offset;
150static int i8254_ticked;
151/*
152 * XXX new_function and timer_func should not handle clockframes, but
153 * timer_func currently needs to hold hardclock to handle the
154 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
155 * to switch between clkintr() and a slightly different timerintr().
156 */
157static void (*new_function) __P((struct clockframe *frame));
158static u_int new_rate;
159static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
160static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
161static u_int timer0_prescaler_count;
162
163/* Values for timerX_state: */
164#define RELEASED 0
165#define RELEASE_PENDING 1
166#define ACQUIRED 2
167#define ACQUIRE_PENDING 3
168
169static u_char timer0_state;
170static u_char timer2_state;
171static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
172#if defined(I386_CPU) || defined(I486_CPU)
173 u_int tsc_present; /* Not static; other parts of the kernel
174 * Need to know this */
175#else
176static u_int tsc_present;
177#endif
178
179static unsigned i8254_get_timecount __P((struct timecounter *tc));
180static unsigned tsc_get_timecount __P((struct timecounter *tc));
181static void set_timer_freq(u_int freq, int intr_freq);
182
183static struct timecounter tsc_timecounter = {
184 tsc_get_timecount, /* get_timecount */
185 0, /* no poll_pps */
186 ~0u, /* counter_mask */
187 0, /* frequency */
188 "TSC" /* name */
189};
190
191SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
192 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
193
194static struct timecounter i8254_timecounter = {
195 i8254_get_timecount, /* get_timecount */
196 0, /* no poll_pps */
197 ~0u, /* counter_mask */
198 0, /* frequency */
199 "i8254" /* name */
200};
201
202SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
203 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
204
205static void
206clkintr(struct clockframe frame)
207{
208
209 if (timecounter->tc_get_timecount == i8254_get_timecount) {
|
210 mtx_enter(&clock_lock, MTX_SPIN);
| 210 mtx_lock_spin(&clock_lock);
|
211 if (i8254_ticked)
212 i8254_ticked = 0;
213 else {
214 i8254_offset += timer0_max_count;
215 i8254_lastcount = 0;
216 }
217 clkintr_pending = 0;
| 211 if (i8254_ticked)
212 i8254_ticked = 0;
213 else {
214 i8254_offset += timer0_max_count;
215 i8254_lastcount = 0;
216 }
217 clkintr_pending = 0;
|
218 mtx_exit(&clock_lock, MTX_SPIN);
| 218 mtx_unlock_spin(&clock_lock);
|
219 }
220 timer_func(&frame);
221 switch (timer0_state) {
222
223 case RELEASED:
224 break;
225
226 case ACQUIRED:
227 if ((timer0_prescaler_count += timer0_max_count)
228 >= hardclock_max_count) {
229 timer0_prescaler_count -= hardclock_max_count;
230 hardclock(&frame);
231 }
232 break;
233
234 case ACQUIRE_PENDING:
| 219 }
220 timer_func(&frame);
221 switch (timer0_state) {
222
223 case RELEASED:
224 break;
225
226 case ACQUIRED:
227 if ((timer0_prescaler_count += timer0_max_count)
228 >= hardclock_max_count) {
229 timer0_prescaler_count -= hardclock_max_count;
230 hardclock(&frame);
231 }
232 break;
233
234 case ACQUIRE_PENDING:
|
235 mtx_enter(&clock_lock, MTX_SPIN);
| 235 mtx_lock_spin(&clock_lock);
|
236 i8254_offset = i8254_get_timecount(NULL);
237 i8254_lastcount = 0;
238 timer0_max_count = TIMER_DIV(new_rate);
239 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
240 outb(TIMER_CNTR0, timer0_max_count & 0xff);
241 outb(TIMER_CNTR0, timer0_max_count >> 8);
| 236 i8254_offset = i8254_get_timecount(NULL);
237 i8254_lastcount = 0;
238 timer0_max_count = TIMER_DIV(new_rate);
239 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
240 outb(TIMER_CNTR0, timer0_max_count & 0xff);
241 outb(TIMER_CNTR0, timer0_max_count >> 8);
|
242 mtx_exit(&clock_lock, MTX_SPIN);
| 242 mtx_unlock_spin(&clock_lock);
|
243 timer_func = new_function;
244 timer0_state = ACQUIRED;
245 break;
246
247 case RELEASE_PENDING:
248 if ((timer0_prescaler_count += timer0_max_count)
249 >= hardclock_max_count) {
| 243 timer_func = new_function;
244 timer0_state = ACQUIRED;
245 break;
246
247 case RELEASE_PENDING:
248 if ((timer0_prescaler_count += timer0_max_count)
249 >= hardclock_max_count) {
|
250 mtx_enter(&clock_lock, MTX_SPIN);
| 250 mtx_lock_spin(&clock_lock);
|
251 i8254_offset = i8254_get_timecount(NULL);
252 i8254_lastcount = 0;
253 timer0_max_count = hardclock_max_count;
254 outb(TIMER_MODE,
255 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
256 outb(TIMER_CNTR0, timer0_max_count & 0xff);
257 outb(TIMER_CNTR0, timer0_max_count >> 8);
| 251 i8254_offset = i8254_get_timecount(NULL);
252 i8254_lastcount = 0;
253 timer0_max_count = hardclock_max_count;
254 outb(TIMER_MODE,
255 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
256 outb(TIMER_CNTR0, timer0_max_count & 0xff);
257 outb(TIMER_CNTR0, timer0_max_count >> 8);
|
258 mtx_exit(&clock_lock, MTX_SPIN);
| 258 mtx_unlock_spin(&clock_lock);
|
259 timer0_prescaler_count = 0;
260 timer_func = hardclock;
261 timer0_state = RELEASED;
262 hardclock(&frame);
263 }
264 break;
265 }
266#ifdef DEV_MCA
267 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
268 if (MCA_system)
269 outb(0x61, inb(0x61) | 0x80);
270#endif
271}
272
273/*
274 * The acquire and release functions must be called at ipl >= splclock().
275 */
276int
277acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
278{
279 static int old_rate;
280
281 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
282 return (-1);
283 switch (timer0_state) {
284
285 case RELEASED:
286 timer0_state = ACQUIRE_PENDING;
287 break;
288
289 case RELEASE_PENDING:
290 if (rate != old_rate)
291 return (-1);
292 /*
293 * The timer has been released recently, but is being
294 * re-acquired before the release completed. In this
295 * case, we simply reclaim it as if it had not been
296 * released at all.
297 */
298 timer0_state = ACQUIRED;
299 break;
300
301 default:
302 return (-1); /* busy */
303 }
304 new_function = function;
305 old_rate = new_rate = rate;
306 return (0);
307}
308
309int
310acquire_timer2(int mode)
311{
312
313 if (timer2_state != RELEASED)
314 return (-1);
315 timer2_state = ACQUIRED;
316
317 /*
318 * This access to the timer registers is as atomic as possible
319 * because it is a single instruction. We could do better if we
320 * knew the rate. Use of splclock() limits glitches to 10-100us,
321 * and this is probably good enough for timer2, so we aren't as
322 * careful with it as with timer0.
323 */
324 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
325
326 return (0);
327}
328
329int
330release_timer0()
331{
332 switch (timer0_state) {
333
334 case ACQUIRED:
335 timer0_state = RELEASE_PENDING;
336 break;
337
338 case ACQUIRE_PENDING:
339 /* Nothing happened yet, release quickly. */
340 timer0_state = RELEASED;
341 break;
342
343 default:
344 return (-1);
345 }
346 return (0);
347}
348
349int
350release_timer2()
351{
352
353 if (timer2_state != ACQUIRED)
354 return (-1);
355 timer2_state = RELEASED;
356 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
357 return (0);
358}
359
360/*
361 * This routine receives statistical clock interrupts from the RTC.
362 * As explained above, these occur at 128 interrupts per second.
363 * When profiling, we receive interrupts at a rate of 1024 Hz.
364 *
365 * This does not actually add as much overhead as it sounds, because
366 * when the statistical clock is active, the hardclock driver no longer
367 * needs to keep (inaccurate) statistics on its own. This decouples
368 * statistics gathering from scheduling interrupts.
369 *
370 * The RTC chip requires that we read status register C (RTC_INTR)
371 * to acknowledge an interrupt, before it will generate the next one.
372 * Under high interrupt load, rtcintr() can be indefinitely delayed and
373 * the clock can tick immediately after the read from RTC_INTR. In this
374 * case, the mc146818A interrupt signal will not drop for long enough
375 * to register with the 8259 PIC. If an interrupt is missed, the stat
376 * clock will halt, considerably degrading system performance. This is
377 * why we use 'while' rather than a more straightforward 'if' below.
378 * Stat clock ticks can still be lost, causing minor loss of accuracy
379 * in the statistics, but the stat clock will no longer stop.
380 */
381static void
382rtcintr(struct clockframe frame)
383{
384 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
385 statclock(&frame);
386}
387
388#include "opt_ddb.h"
389#ifdef DDB
390#include <ddb/ddb.h>
391
392DB_SHOW_COMMAND(rtc, rtc)
393{
394 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
395 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
396 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
397 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
398}
399#endif /* DDB */
400
401static int
402getit(void)
403{
404 int high, low;
405
| 259 timer0_prescaler_count = 0;
260 timer_func = hardclock;
261 timer0_state = RELEASED;
262 hardclock(&frame);
263 }
264 break;
265 }
266#ifdef DEV_MCA
267 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
268 if (MCA_system)
269 outb(0x61, inb(0x61) | 0x80);
270#endif
271}
272
273/*
274 * The acquire and release functions must be called at ipl >= splclock().
275 */
276int
277acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
278{
279 static int old_rate;
280
281 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
282 return (-1);
283 switch (timer0_state) {
284
285 case RELEASED:
286 timer0_state = ACQUIRE_PENDING;
287 break;
288
289 case RELEASE_PENDING:
290 if (rate != old_rate)
291 return (-1);
292 /*
293 * The timer has been released recently, but is being
294 * re-acquired before the release completed. In this
295 * case, we simply reclaim it as if it had not been
296 * released at all.
297 */
298 timer0_state = ACQUIRED;
299 break;
300
301 default:
302 return (-1); /* busy */
303 }
304 new_function = function;
305 old_rate = new_rate = rate;
306 return (0);
307}
308
309int
310acquire_timer2(int mode)
311{
312
313 if (timer2_state != RELEASED)
314 return (-1);
315 timer2_state = ACQUIRED;
316
317 /*
318 * This access to the timer registers is as atomic as possible
319 * because it is a single instruction. We could do better if we
320 * knew the rate. Use of splclock() limits glitches to 10-100us,
321 * and this is probably good enough for timer2, so we aren't as
322 * careful with it as with timer0.
323 */
324 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
325
326 return (0);
327}
328
329int
330release_timer0()
331{
332 switch (timer0_state) {
333
334 case ACQUIRED:
335 timer0_state = RELEASE_PENDING;
336 break;
337
338 case ACQUIRE_PENDING:
339 /* Nothing happened yet, release quickly. */
340 timer0_state = RELEASED;
341 break;
342
343 default:
344 return (-1);
345 }
346 return (0);
347}
348
349int
350release_timer2()
351{
352
353 if (timer2_state != ACQUIRED)
354 return (-1);
355 timer2_state = RELEASED;
356 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
357 return (0);
358}
359
360/*
361 * This routine receives statistical clock interrupts from the RTC.
362 * As explained above, these occur at 128 interrupts per second.
363 * When profiling, we receive interrupts at a rate of 1024 Hz.
364 *
365 * This does not actually add as much overhead as it sounds, because
366 * when the statistical clock is active, the hardclock driver no longer
367 * needs to keep (inaccurate) statistics on its own. This decouples
368 * statistics gathering from scheduling interrupts.
369 *
370 * The RTC chip requires that we read status register C (RTC_INTR)
371 * to acknowledge an interrupt, before it will generate the next one.
372 * Under high interrupt load, rtcintr() can be indefinitely delayed and
373 * the clock can tick immediately after the read from RTC_INTR. In this
374 * case, the mc146818A interrupt signal will not drop for long enough
375 * to register with the 8259 PIC. If an interrupt is missed, the stat
376 * clock will halt, considerably degrading system performance. This is
377 * why we use 'while' rather than a more straightforward 'if' below.
378 * Stat clock ticks can still be lost, causing minor loss of accuracy
379 * in the statistics, but the stat clock will no longer stop.
380 */
381static void
382rtcintr(struct clockframe frame)
383{
384 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
385 statclock(&frame);
386}
387
388#include "opt_ddb.h"
389#ifdef DDB
390#include <ddb/ddb.h>
391
392DB_SHOW_COMMAND(rtc, rtc)
393{
394 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
395 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
396 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
397 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
398}
399#endif /* DDB */
400
401static int
402getit(void)
403{
404 int high, low;
405
|
406 mtx_enter(&clock_lock, MTX_SPIN);
| 406 mtx_lock_spin(&clock_lock);
|
407
408 /* Select timer0 and latch counter value. */
409 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
410
411 low = inb(TIMER_CNTR0);
412 high = inb(TIMER_CNTR0);
413
| 407
408 /* Select timer0 and latch counter value. */
409 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
410
411 low = inb(TIMER_CNTR0);
412 high = inb(TIMER_CNTR0);
413
|
414 mtx_exit(&clock_lock, MTX_SPIN);
| 414 mtx_unlock_spin(&clock_lock);
|
415 return ((high << 8) | low);
416}
417
418/*
419 * Wait "n" microseconds.
420 * Relies on timer 1 counting down from (timer_freq / hz)
421 * Note: timer had better have been programmed before this is first used!
422 */
423void
424DELAY(int n)
425{
426 int delta, prev_tick, tick, ticks_left;
427
428#ifdef DELAYDEBUG
429 int getit_calls = 1;
430 int n1;
431 static int state = 0;
432
433 if (state == 0) {
434 state = 1;
435 for (n1 = 1; n1 <= 10000000; n1 *= 10)
436 DELAY(n1);
437 state = 2;
438 }
439 if (state == 1)
440 printf("DELAY(%d)...", n);
441#endif
442 /*
443 * Guard against the timer being uninitialized if we are called
444 * early for console i/o.
445 */
446 if (timer0_max_count == 0)
447 set_timer_freq(timer_freq, hz);
448
449 /*
450 * Read the counter first, so that the rest of the setup overhead is
451 * counted. Guess the initial overhead is 20 usec (on most systems it
452 * takes about 1.5 usec for each of the i/o's in getit(). The loop
453 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
454 * multiplications and divisions to scale the count take a while).
455 */
456 prev_tick = getit();
457 n -= 0; /* XXX actually guess no initial overhead */
458 /*
459 * Calculate (n * (timer_freq / 1e6)) without using floating point
460 * and without any avoidable overflows.
461 */
462 if (n <= 0)
463 ticks_left = 0;
464 else if (n < 256)
465 /*
466 * Use fixed point to avoid a slow division by 1000000.
467 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
468 * 2^15 is the first power of 2 that gives exact results
469 * for n between 0 and 256.
470 */
471 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
472 else
473 /*
474 * Don't bother using fixed point, although gcc-2.7.2
475 * generates particularly poor code for the long long
476 * division, since even the slow way will complete long
477 * before the delay is up (unless we're interrupted).
478 */
479 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
480 / 1000000;
481
482 while (ticks_left > 0) {
483 tick = getit();
484#ifdef DELAYDEBUG
485 ++getit_calls;
486#endif
487 delta = prev_tick - tick;
488 prev_tick = tick;
489 if (delta < 0) {
490 delta += timer0_max_count;
491 /*
492 * Guard against timer0_max_count being wrong.
493 * This shouldn't happen in normal operation,
494 * but it may happen if set_timer_freq() is
495 * traced.
496 */
497 if (delta < 0)
498 delta = 0;
499 }
500 ticks_left -= delta;
501 }
502#ifdef DELAYDEBUG
503 if (state == 1)
504 printf(" %d calls to getit() at %d usec each\n",
505 getit_calls, (n + 5) / getit_calls);
506#endif
507}
508
509static void
510sysbeepstop(void *chan)
511{
512 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
513 release_timer2();
514 beeping = 0;
515}
516
517int
518sysbeep(int pitch, int period)
519{
520 int x = splclock();
521
522 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
523 if (!beeping) {
524 /* Something else owns it. */
525 splx(x);
526 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
527 }
| 415 return ((high << 8) | low);
416}
417
418/*
419 * Wait "n" microseconds.
420 * Relies on timer 1 counting down from (timer_freq / hz)
421 * Note: timer had better have been programmed before this is first used!
422 */
423void
424DELAY(int n)
425{
426 int delta, prev_tick, tick, ticks_left;
427
428#ifdef DELAYDEBUG
429 int getit_calls = 1;
430 int n1;
431 static int state = 0;
432
433 if (state == 0) {
434 state = 1;
435 for (n1 = 1; n1 <= 10000000; n1 *= 10)
436 DELAY(n1);
437 state = 2;
438 }
439 if (state == 1)
440 printf("DELAY(%d)...", n);
441#endif
442 /*
443 * Guard against the timer being uninitialized if we are called
444 * early for console i/o.
445 */
446 if (timer0_max_count == 0)
447 set_timer_freq(timer_freq, hz);
448
449 /*
450 * Read the counter first, so that the rest of the setup overhead is
451 * counted. Guess the initial overhead is 20 usec (on most systems it
452 * takes about 1.5 usec for each of the i/o's in getit(). The loop
453 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
454 * multiplications and divisions to scale the count take a while).
455 */
456 prev_tick = getit();
457 n -= 0; /* XXX actually guess no initial overhead */
458 /*
459 * Calculate (n * (timer_freq / 1e6)) without using floating point
460 * and without any avoidable overflows.
461 */
462 if (n <= 0)
463 ticks_left = 0;
464 else if (n < 256)
465 /*
466 * Use fixed point to avoid a slow division by 1000000.
467 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
468 * 2^15 is the first power of 2 that gives exact results
469 * for n between 0 and 256.
470 */
471 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
472 else
473 /*
474 * Don't bother using fixed point, although gcc-2.7.2
475 * generates particularly poor code for the long long
476 * division, since even the slow way will complete long
477 * before the delay is up (unless we're interrupted).
478 */
479 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
480 / 1000000;
481
482 while (ticks_left > 0) {
483 tick = getit();
484#ifdef DELAYDEBUG
485 ++getit_calls;
486#endif
487 delta = prev_tick - tick;
488 prev_tick = tick;
489 if (delta < 0) {
490 delta += timer0_max_count;
491 /*
492 * Guard against timer0_max_count being wrong.
493 * This shouldn't happen in normal operation,
494 * but it may happen if set_timer_freq() is
495 * traced.
496 */
497 if (delta < 0)
498 delta = 0;
499 }
500 ticks_left -= delta;
501 }
502#ifdef DELAYDEBUG
503 if (state == 1)
504 printf(" %d calls to getit() at %d usec each\n",
505 getit_calls, (n + 5) / getit_calls);
506#endif
507}
508
509static void
510sysbeepstop(void *chan)
511{
512 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
513 release_timer2();
514 beeping = 0;
515}
516
517int
518sysbeep(int pitch, int period)
519{
520 int x = splclock();
521
522 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
523 if (!beeping) {
524 /* Something else owns it. */
525 splx(x);
526 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
527 }
|
528 mtx_enter(&clock_lock, MTX_SPIN);
| 528 mtx_lock_spin(&clock_lock);
|
529 outb(TIMER_CNTR2, pitch);
530 outb(TIMER_CNTR2, (pitch>>8));
| 529 outb(TIMER_CNTR2, pitch);
530 outb(TIMER_CNTR2, (pitch>>8));
|
531 mtx_exit(&clock_lock, MTX_SPIN);
| 531 mtx_unlock_spin(&clock_lock);
|
532 if (!beeping) {
533 /* enable counter2 output to speaker */
534 outb(IO_PPI, inb(IO_PPI) | 3);
535 beeping = period;
536 timeout(sysbeepstop, (void *)NULL, period);
537 }
538 splx(x);
539 return (0);
540}
541
542/*
543 * RTC support routines
544 */
545
546int
547rtcin(reg)
548 int reg;
549{
550 int s;
551 u_char val;
552
553 s = splhigh();
554 outb(IO_RTC, reg);
555 inb(0x84);
556 val = inb(IO_RTC + 1);
557 inb(0x84);
558 splx(s);
559 return (val);
560}
561
562static __inline void
563writertc(u_char reg, u_char val)
564{
565 int s;
566
567 s = splhigh();
568 inb(0x84);
569 outb(IO_RTC, reg);
570 inb(0x84);
571 outb(IO_RTC + 1, val);
572 inb(0x84); /* XXX work around wrong order in rtcin() */
573 splx(s);
574}
575
576static __inline int
577readrtc(int port)
578{
579 return(bcd2bin(rtcin(port)));
580}
581
582static u_int
583calibrate_clocks(void)
584{
585 u_int64_t old_tsc;
586 u_int count, prev_count, tot_count;
587 int sec, start_sec, timeout;
588
589 if (bootverbose)
590 printf("Calibrating clock(s) ... ");
591 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
592 goto fail;
593 timeout = 100000000;
594
595 /* Read the mc146818A seconds counter. */
596 for (;;) {
597 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
598 sec = rtcin(RTC_SEC);
599 break;
600 }
601 if (--timeout == 0)
602 goto fail;
603 }
604
605 /* Wait for the mC146818A seconds counter to change. */
606 start_sec = sec;
607 for (;;) {
608 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
609 sec = rtcin(RTC_SEC);
610 if (sec != start_sec)
611 break;
612 }
613 if (--timeout == 0)
614 goto fail;
615 }
616
617 /* Start keeping track of the i8254 counter. */
618 prev_count = getit();
619 if (prev_count == 0 || prev_count > timer0_max_count)
620 goto fail;
621 tot_count = 0;
622
623 if (tsc_present)
624 old_tsc = rdtsc();
625 else
626 old_tsc = 0; /* shut up gcc */
627
628 /*
629 * Wait for the mc146818A seconds counter to change. Read the i8254
630 * counter for each iteration since this is convenient and only
631 * costs a few usec of inaccuracy. The timing of the final reads
632 * of the counters almost matches the timing of the initial reads,
633 * so the main cause of inaccuracy is the varying latency from
634 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
635 * rtcin(RTC_SEC) that returns a changed seconds count. The
636 * maximum inaccuracy from this cause is < 10 usec on 486's.
637 */
638 start_sec = sec;
639 for (;;) {
640 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
641 sec = rtcin(RTC_SEC);
642 count = getit();
643 if (count == 0 || count > timer0_max_count)
644 goto fail;
645 if (count > prev_count)
646 tot_count += prev_count - (count - timer0_max_count);
647 else
648 tot_count += prev_count - count;
649 prev_count = count;
650 if (sec != start_sec)
651 break;
652 if (--timeout == 0)
653 goto fail;
654 }
655
656 /*
657 * Read the cpu cycle counter. The timing considerations are
658 * similar to those for the i8254 clock.
659 */
660 if (tsc_present)
661 tsc_freq = rdtsc() - old_tsc;
662
663 if (bootverbose) {
664 if (tsc_present)
665 printf("TSC clock: %u Hz, ", tsc_freq);
666 printf("i8254 clock: %u Hz\n", tot_count);
667 }
668 return (tot_count);
669
670fail:
671 if (bootverbose)
672 printf("failed, using default i8254 clock of %u Hz\n",
673 timer_freq);
674 return (timer_freq);
675}
676
677static void
678set_timer_freq(u_int freq, int intr_freq)
679{
680 int new_timer0_max_count;
681
| 532 if (!beeping) {
533 /* enable counter2 output to speaker */
534 outb(IO_PPI, inb(IO_PPI) | 3);
535 beeping = period;
536 timeout(sysbeepstop, (void *)NULL, period);
537 }
538 splx(x);
539 return (0);
540}
541
542/*
543 * RTC support routines
544 */
545
546int
547rtcin(reg)
548 int reg;
549{
550 int s;
551 u_char val;
552
553 s = splhigh();
554 outb(IO_RTC, reg);
555 inb(0x84);
556 val = inb(IO_RTC + 1);
557 inb(0x84);
558 splx(s);
559 return (val);
560}
561
562static __inline void
563writertc(u_char reg, u_char val)
564{
565 int s;
566
567 s = splhigh();
568 inb(0x84);
569 outb(IO_RTC, reg);
570 inb(0x84);
571 outb(IO_RTC + 1, val);
572 inb(0x84); /* XXX work around wrong order in rtcin() */
573 splx(s);
574}
575
576static __inline int
577readrtc(int port)
578{
579 return(bcd2bin(rtcin(port)));
580}
581
582static u_int
583calibrate_clocks(void)
584{
585 u_int64_t old_tsc;
586 u_int count, prev_count, tot_count;
587 int sec, start_sec, timeout;
588
589 if (bootverbose)
590 printf("Calibrating clock(s) ... ");
591 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
592 goto fail;
593 timeout = 100000000;
594
595 /* Read the mc146818A seconds counter. */
596 for (;;) {
597 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
598 sec = rtcin(RTC_SEC);
599 break;
600 }
601 if (--timeout == 0)
602 goto fail;
603 }
604
605 /* Wait for the mC146818A seconds counter to change. */
606 start_sec = sec;
607 for (;;) {
608 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
609 sec = rtcin(RTC_SEC);
610 if (sec != start_sec)
611 break;
612 }
613 if (--timeout == 0)
614 goto fail;
615 }
616
617 /* Start keeping track of the i8254 counter. */
618 prev_count = getit();
619 if (prev_count == 0 || prev_count > timer0_max_count)
620 goto fail;
621 tot_count = 0;
622
623 if (tsc_present)
624 old_tsc = rdtsc();
625 else
626 old_tsc = 0; /* shut up gcc */
627
628 /*
629 * Wait for the mc146818A seconds counter to change. Read the i8254
630 * counter for each iteration since this is convenient and only
631 * costs a few usec of inaccuracy. The timing of the final reads
632 * of the counters almost matches the timing of the initial reads,
633 * so the main cause of inaccuracy is the varying latency from
634 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
635 * rtcin(RTC_SEC) that returns a changed seconds count. The
636 * maximum inaccuracy from this cause is < 10 usec on 486's.
637 */
638 start_sec = sec;
639 for (;;) {
640 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
641 sec = rtcin(RTC_SEC);
642 count = getit();
643 if (count == 0 || count > timer0_max_count)
644 goto fail;
645 if (count > prev_count)
646 tot_count += prev_count - (count - timer0_max_count);
647 else
648 tot_count += prev_count - count;
649 prev_count = count;
650 if (sec != start_sec)
651 break;
652 if (--timeout == 0)
653 goto fail;
654 }
655
656 /*
657 * Read the cpu cycle counter. The timing considerations are
658 * similar to those for the i8254 clock.
659 */
660 if (tsc_present)
661 tsc_freq = rdtsc() - old_tsc;
662
663 if (bootverbose) {
664 if (tsc_present)
665 printf("TSC clock: %u Hz, ", tsc_freq);
666 printf("i8254 clock: %u Hz\n", tot_count);
667 }
668 return (tot_count);
669
670fail:
671 if (bootverbose)
672 printf("failed, using default i8254 clock of %u Hz\n",
673 timer_freq);
674 return (timer_freq);
675}
676
677static void
678set_timer_freq(u_int freq, int intr_freq)
679{
680 int new_timer0_max_count;
681
|
682 mtx_enter(&clock_lock, MTX_SPIN);
| 682 mtx_lock_spin(&clock_lock);
|
683 timer_freq = freq;
684 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
685 if (new_timer0_max_count != timer0_max_count) {
686 timer0_max_count = new_timer0_max_count;
687 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
688 outb(TIMER_CNTR0, timer0_max_count & 0xff);
689 outb(TIMER_CNTR0, timer0_max_count >> 8);
690 }
| 683 timer_freq = freq;
684 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
685 if (new_timer0_max_count != timer0_max_count) {
686 timer0_max_count = new_timer0_max_count;
687 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
688 outb(TIMER_CNTR0, timer0_max_count & 0xff);
689 outb(TIMER_CNTR0, timer0_max_count >> 8);
690 }
|
691 mtx_exit(&clock_lock, MTX_SPIN);
| 691 mtx_unlock_spin(&clock_lock);
|
692}
693
694/*
695 * i8254_restore is called from apm_default_resume() to reload
696 * the countdown register.
697 * this should not be necessary but there are broken laptops that
698 * do not restore the countdown register on resume.
699 * when it happnes, it messes up the hardclock interval and system clock,
700 * which leads to the infamous "calcru: negative time" problem.
701 */
702void
703i8254_restore(void)
704{
705
| 692}
693
694/*
695 * i8254_restore is called from apm_default_resume() to reload
696 * the countdown register.
697 * this should not be necessary but there are broken laptops that
698 * do not restore the countdown register on resume.
699 * when it happnes, it messes up the hardclock interval and system clock,
700 * which leads to the infamous "calcru: negative time" problem.
701 */
702void
703i8254_restore(void)
704{
705
|
706 mtx_enter(&clock_lock, MTX_SPIN);
| 706 mtx_lock_spin(&clock_lock);
|
707 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
708 outb(TIMER_CNTR0, timer0_max_count & 0xff);
709 outb(TIMER_CNTR0, timer0_max_count >> 8);
| 707 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
708 outb(TIMER_CNTR0, timer0_max_count & 0xff);
709 outb(TIMER_CNTR0, timer0_max_count >> 8);
|
710 mtx_exit(&clock_lock, MTX_SPIN);
| 710 mtx_unlock_spin(&clock_lock);
|
711}
712
713/*
714 * Initialize 8254 timer 0 early so that it can be used in DELAY().
715 * XXX initialization of other timers is unintentionally left blank.
716 */
717void
718startrtclock()
719{
720 u_int delta, freq;
721
722 if (cpu_feature & CPUID_TSC)
723 tsc_present = 1;
724 else
725 tsc_present = 0;
726
727 writertc(RTC_STATUSA, rtc_statusa);
728 writertc(RTC_STATUSB, RTCSB_24HR);
729
730 set_timer_freq(timer_freq, hz);
731 freq = calibrate_clocks();
732#ifdef CLK_CALIBRATION_LOOP
733 if (bootverbose) {
734 printf(
735 "Press a key on the console to abort clock calibration\n");
736 while (cncheckc() == -1)
737 calibrate_clocks();
738 }
739#endif
740
741 /*
742 * Use the calibrated i8254 frequency if it seems reasonable.
743 * Otherwise use the default, and don't use the calibrated i586
744 * frequency.
745 */
746 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
747 if (delta < timer_freq / 100) {
748#ifndef CLK_USE_I8254_CALIBRATION
749 if (bootverbose)
750 printf(
751"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
752 freq = timer_freq;
753#endif
754 timer_freq = freq;
755 } else {
756 if (bootverbose)
757 printf(
758 "%d Hz differs from default of %d Hz by more than 1%%\n",
759 freq, timer_freq);
760 tsc_freq = 0;
761 }
762
763 set_timer_freq(timer_freq, hz);
764 i8254_timecounter.tc_frequency = timer_freq;
765 tc_init(&i8254_timecounter);
766
767#ifndef CLK_USE_TSC_CALIBRATION
768 if (tsc_freq != 0) {
769 if (bootverbose)
770 printf(
771"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
772 tsc_freq = 0;
773 }
774#endif
775 if (tsc_present && tsc_freq == 0) {
776 /*
777 * Calibration of the i586 clock relative to the mc146818A
778 * clock failed. Do a less accurate calibration relative
779 * to the i8254 clock.
780 */
781 u_int64_t old_tsc = rdtsc();
782
783 DELAY(1000000);
784 tsc_freq = rdtsc() - old_tsc;
785#ifdef CLK_USE_TSC_CALIBRATION
786 if (bootverbose)
787 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
788#endif
789 }
790
791#if !defined(SMP)
792 /*
793 * We can not use the TSC in SMP mode, until we figure out a
794 * cheap (impossible), reliable and precise (yeah right!) way
795 * to synchronize the TSCs of all the CPUs.
796 * Curse Intel for leaving the counter out of the I/O APIC.
797 */
798
799#ifdef DEV_APM
800 /*
801 * We can not use the TSC if we support APM. Precise timekeeping
802 * on an APM'ed machine is at best a fools pursuit, since
803 * any and all of the time spent in various SMM code can't
804 * be reliably accounted for. Reading the RTC is your only
805 * source of reliable time info. The i8254 looses too of course
806 * but we need to have some kind of time...
807 * We don't know at this point whether APM is going to be used
808 * or not, nor when it might be activated. Play it safe.
809 */
810 {
811 int disabled = 0;
812 resource_int_value("apm", 0, "disabled", &disabled);
813 if (disabled == 0)
814 return;
815 }
816#endif /* DEV_APM */
817
818 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
819 tsc_timecounter.tc_frequency = tsc_freq;
820 tc_init(&tsc_timecounter);
821 }
822
823#endif /* !defined(SMP) */
824}
825
826/*
827 * Initialize the time of day register, based on the time base which is, e.g.
828 * from a filesystem.
829 */
830void
831inittodr(time_t base)
832{
833 unsigned long sec, days;
834 int yd;
835 int year, month;
836 int y, m, s;
837 struct timespec ts;
838
839 if (base) {
840 s = splclock();
841 ts.tv_sec = base;
842 ts.tv_nsec = 0;
843 tc_setclock(&ts);
844 splx(s);
845 }
846
847 /* Look if we have a RTC present and the time is valid */
848 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
849 goto wrong_time;
850
851 /* wait for time update to complete */
852 /* If RTCSA_TUP is zero, we have at least 244us before next update */
853 s = splhigh();
854 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
855 splx(s);
856 s = splhigh();
857 }
858
859 days = 0;
860#ifdef USE_RTC_CENTURY
861 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
862#else
863 year = readrtc(RTC_YEAR) + 1900;
864 if (year < 1970)
865 year += 100;
866#endif
867 if (year < 1970) {
868 splx(s);
869 goto wrong_time;
870 }
871 month = readrtc(RTC_MONTH);
872 for (m = 1; m < month; m++)
873 days += daysinmonth[m-1];
874 if ((month > 2) && LEAPYEAR(year))
875 days ++;
876 days += readrtc(RTC_DAY) - 1;
877 yd = days;
878 for (y = 1970; y < year; y++)
879 days += DAYSPERYEAR + LEAPYEAR(y);
880 sec = ((( days * 24 +
881 readrtc(RTC_HRS)) * 60 +
882 readrtc(RTC_MIN)) * 60 +
883 readrtc(RTC_SEC));
884 /* sec now contains the number of seconds, since Jan 1 1970,
885 in the local time zone */
886
887 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
888
889 y = time_second - sec;
890 if (y <= -2 || y >= 2) {
891 /* badly off, adjust it */
892 ts.tv_sec = sec;
893 ts.tv_nsec = 0;
894 tc_setclock(&ts);
895 }
896 splx(s);
897 return;
898
899wrong_time:
900 printf("Invalid time in real time clock.\n");
901 printf("Check and reset the date immediately!\n");
902}
903
904/*
905 * Write system time back to RTC
906 */
907void
908resettodr()
909{
910 unsigned long tm;
911 int y, m, s;
912
913 if (disable_rtc_set)
914 return;
915
916 s = splclock();
917 tm = time_second;
918 splx(s);
919
920 /* Disable RTC updates and interrupts. */
921 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
922
923 /* Calculate local time to put in RTC */
924
925 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
926
927 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
928 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
929 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
930
931 /* We have now the days since 01-01-1970 in tm */
932 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
933 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
934 tm >= m;
935 y++, m = DAYSPERYEAR + LEAPYEAR(y))
936 tm -= m;
937
938 /* Now we have the years in y and the day-of-the-year in tm */
939 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
940#ifdef USE_RTC_CENTURY
941 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
942#endif
943 for (m = 0; ; m++) {
944 int ml;
945
946 ml = daysinmonth[m];
947 if (m == 1 && LEAPYEAR(y))
948 ml++;
949 if (tm < ml)
950 break;
951 tm -= ml;
952 }
953
954 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
955 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
956
957 /* Reenable RTC updates and interrupts. */
958 writertc(RTC_STATUSB, rtc_statusb);
959}
960
961
962/*
963 * Start both clocks running.
964 */
965void
966cpu_initclocks()
967{
968 int diag;
969#ifdef APIC_IO
970 int apic_8254_trial;
971 struct intrhand *clkdesc;
972#endif /* APIC_IO */
973
974 if (statclock_disable) {
975 /*
976 * The stat interrupt mask is different without the
977 * statistics clock. Also, don't set the interrupt
978 * flag which would normally cause the RTC to generate
979 * interrupts.
980 */
981 rtc_statusb = RTCSB_24HR;
982 } else {
983 /* Setting stathz to nonzero early helps avoid races. */
984 stathz = RTC_NOPROFRATE;
985 profhz = RTC_PROFRATE;
986 }
987
988 /* Finish initializing 8253 timer 0. */
989#ifdef APIC_IO
990
991 apic_8254_intr = isa_apic_irq(0);
992 apic_8254_trial = 0;
993 if (apic_8254_intr >= 0 ) {
994 if (apic_int_type(0, 0) == 3)
995 apic_8254_trial = 1;
996 } else {
997 /* look for ExtInt on pin 0 */
998 if (apic_int_type(0, 0) == 3) {
999 apic_8254_intr = apic_irq(0, 0);
1000 setup_8254_mixed_mode();
1001 } else
1002 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1003 }
1004
1005 clkdesc = inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr,
1006 NULL, PI_REALTIME, INTR_FAST);
1007 INTREN(1 << apic_8254_intr);
1008
1009#else /* APIC_IO */
1010
1011 /*
1012 * XXX Check the priority of this interrupt handler. I
1013 * couldn't find anything suitable in the BSD/OS code (grog,
1014 * 19 July 2000).
1015 */
1016 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL, PI_REALTIME,
1017 INTR_FAST);
1018 INTREN(IRQ0);
1019
1020#endif /* APIC_IO */
1021
1022 /* Initialize RTC. */
1023 writertc(RTC_STATUSA, rtc_statusa);
1024 writertc(RTC_STATUSB, RTCSB_24HR);
1025
1026 /* Don't bother enabling the statistics clock. */
1027 if (statclock_disable)
1028 return;
1029 diag = rtcin(RTC_DIAG);
1030 if (diag != 0)
1031 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1032
1033#ifdef APIC_IO
1034 if (isa_apic_irq(8) != 8)
1035 panic("APIC RTC != 8");
1036#endif /* APIC_IO */
1037
1038 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL, PI_REALTIME,
1039 INTR_FAST);
1040
1041#ifdef APIC_IO
1042 INTREN(APIC_IRQ8);
1043#else
1044 INTREN(IRQ8);
1045#endif /* APIC_IO */
1046
1047 writertc(RTC_STATUSB, rtc_statusb);
1048
1049#ifdef APIC_IO
1050 if (apic_8254_trial) {
1051
1052 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1053 while (read_intr_count(8) < 6)
1054 ; /* nothing */
1055 if (read_intr_count(apic_8254_intr) < 3) {
1056 /*
1057 * The MP table is broken.
1058 * The 8254 was not connected to the specified pin
1059 * on the IO APIC.
1060 * Workaround: Limited variant of mixed mode.
1061 */
1062 INTRDIS(1 << apic_8254_intr);
1063 inthand_remove(clkdesc);
1064 printf("APIC_IO: Broken MP table detected: "
1065 "8254 is not connected to "
1066 "IOAPIC #%d intpin %d\n",
1067 int_to_apicintpin[apic_8254_intr].ioapic,
1068 int_to_apicintpin[apic_8254_intr].int_pin);
1069 /*
1070 * Revoke current ISA IRQ 0 assignment and
1071 * configure a fallback interrupt routing from
1072 * the 8254 Timer via the 8259 PIC to the
1073 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1074 * We reuse the low level interrupt handler number.
1075 */
1076 if (apic_irq(0, 0) < 0) {
1077 revoke_apic_irq(apic_8254_intr);
1078 assign_apic_irq(0, 0, apic_8254_intr);
1079 }
1080 apic_8254_intr = apic_irq(0, 0);
1081 setup_8254_mixed_mode();
1082 inthand_add("clk", apic_8254_intr,
1083 (driver_intr_t *)clkintr, NULL,
1084 PI_REALTIME, INTR_FAST);
1085 INTREN(1 << apic_8254_intr);
1086 }
1087
1088 }
1089 if (apic_int_type(0, 0) != 3 ||
1090 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1091 int_to_apicintpin[apic_8254_intr].int_pin != 0)
1092 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1093 int_to_apicintpin[apic_8254_intr].ioapic,
1094 int_to_apicintpin[apic_8254_intr].int_pin);
1095 else
1096 printf("APIC_IO: "
1097 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1098#endif
1099
1100}
1101
1102#ifdef APIC_IO
1103static u_long
1104read_intr_count(int vec)
1105{
1106 u_long *up;
1107 up = intr_countp[vec];
1108 if (up)
1109 return *up;
1110 return 0UL;
1111}
1112
1113static void
1114setup_8254_mixed_mode()
1115{
1116 /*
1117 * Allow 8254 timer to INTerrupt 8259:
1118 * re-initialize master 8259:
1119 * reset; prog 4 bytes, single ICU, edge triggered
1120 */
1121 outb(IO_ICU1, 0x13);
1122 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1123 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1124 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1125 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1126
1127 /* program IO APIC for type 3 INT on INT0 */
1128 if (ext_int_setup(0, 0) < 0)
1129 panic("8254 redirect via APIC pin0 impossible!");
1130}
1131#endif
1132
1133void
1134setstatclockrate(int newhz)
1135{
1136 if (newhz == RTC_PROFRATE)
1137 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1138 else
1139 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1140 writertc(RTC_STATUSA, rtc_statusa);
1141}
1142
1143static int
1144sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1145{
1146 int error;
1147 u_int freq;
1148
1149 /*
1150 * Use `i8254' instead of `timer' in external names because `timer'
1151 * is is too generic. Should use it everywhere.
1152 */
1153 freq = timer_freq;
1154 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1155 if (error == 0 && req->newptr != NULL) {
1156 if (timer0_state != RELEASED)
1157 return (EBUSY); /* too much trouble to handle */
1158 set_timer_freq(freq, hz);
1159 i8254_timecounter.tc_frequency = freq;
1160 tc_update(&i8254_timecounter);
1161 }
1162 return (error);
1163}
1164
1165SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1166 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
1167
1168static int
1169sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1170{
1171 int error;
1172 u_int freq;
1173
1174 if (tsc_timecounter.tc_frequency == 0)
1175 return (EOPNOTSUPP);
1176 freq = tsc_freq;
1177 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1178 if (error == 0 && req->newptr != NULL) {
1179 tsc_freq = freq;
1180 tsc_timecounter.tc_frequency = tsc_freq;
1181 tc_update(&tsc_timecounter);
1182 }
1183 return (error);
1184}
1185
1186SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1187 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", "");
1188
1189static unsigned
1190i8254_get_timecount(struct timecounter *tc)
1191{
1192 u_int count;
1193 u_int high, low;
1194 u_int eflags;
1195
1196 eflags = read_eflags();
| 711}
712
713/*
714 * Initialize 8254 timer 0 early so that it can be used in DELAY().
715 * XXX initialization of other timers is unintentionally left blank.
716 */
717void
718startrtclock()
719{
720 u_int delta, freq;
721
722 if (cpu_feature & CPUID_TSC)
723 tsc_present = 1;
724 else
725 tsc_present = 0;
726
727 writertc(RTC_STATUSA, rtc_statusa);
728 writertc(RTC_STATUSB, RTCSB_24HR);
729
730 set_timer_freq(timer_freq, hz);
731 freq = calibrate_clocks();
732#ifdef CLK_CALIBRATION_LOOP
733 if (bootverbose) {
734 printf(
735 "Press a key on the console to abort clock calibration\n");
736 while (cncheckc() == -1)
737 calibrate_clocks();
738 }
739#endif
740
741 /*
742 * Use the calibrated i8254 frequency if it seems reasonable.
743 * Otherwise use the default, and don't use the calibrated i586
744 * frequency.
745 */
746 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
747 if (delta < timer_freq / 100) {
748#ifndef CLK_USE_I8254_CALIBRATION
749 if (bootverbose)
750 printf(
751"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
752 freq = timer_freq;
753#endif
754 timer_freq = freq;
755 } else {
756 if (bootverbose)
757 printf(
758 "%d Hz differs from default of %d Hz by more than 1%%\n",
759 freq, timer_freq);
760 tsc_freq = 0;
761 }
762
763 set_timer_freq(timer_freq, hz);
764 i8254_timecounter.tc_frequency = timer_freq;
765 tc_init(&i8254_timecounter);
766
767#ifndef CLK_USE_TSC_CALIBRATION
768 if (tsc_freq != 0) {
769 if (bootverbose)
770 printf(
771"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
772 tsc_freq = 0;
773 }
774#endif
775 if (tsc_present && tsc_freq == 0) {
776 /*
777 * Calibration of the i586 clock relative to the mc146818A
778 * clock failed. Do a less accurate calibration relative
779 * to the i8254 clock.
780 */
781 u_int64_t old_tsc = rdtsc();
782
783 DELAY(1000000);
784 tsc_freq = rdtsc() - old_tsc;
785#ifdef CLK_USE_TSC_CALIBRATION
786 if (bootverbose)
787 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
788#endif
789 }
790
791#if !defined(SMP)
792 /*
793 * We can not use the TSC in SMP mode, until we figure out a
794 * cheap (impossible), reliable and precise (yeah right!) way
795 * to synchronize the TSCs of all the CPUs.
796 * Curse Intel for leaving the counter out of the I/O APIC.
797 */
798
799#ifdef DEV_APM
800 /*
801 * We can not use the TSC if we support APM. Precise timekeeping
802 * on an APM'ed machine is at best a fools pursuit, since
803 * any and all of the time spent in various SMM code can't
804 * be reliably accounted for. Reading the RTC is your only
805 * source of reliable time info. The i8254 looses too of course
806 * but we need to have some kind of time...
807 * We don't know at this point whether APM is going to be used
808 * or not, nor when it might be activated. Play it safe.
809 */
810 {
811 int disabled = 0;
812 resource_int_value("apm", 0, "disabled", &disabled);
813 if (disabled == 0)
814 return;
815 }
816#endif /* DEV_APM */
817
818 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
819 tsc_timecounter.tc_frequency = tsc_freq;
820 tc_init(&tsc_timecounter);
821 }
822
823#endif /* !defined(SMP) */
824}
825
826/*
827 * Initialize the time of day register, based on the time base which is, e.g.
828 * from a filesystem.
829 */
830void
831inittodr(time_t base)
832{
833 unsigned long sec, days;
834 int yd;
835 int year, month;
836 int y, m, s;
837 struct timespec ts;
838
839 if (base) {
840 s = splclock();
841 ts.tv_sec = base;
842 ts.tv_nsec = 0;
843 tc_setclock(&ts);
844 splx(s);
845 }
846
847 /* Look if we have a RTC present and the time is valid */
848 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
849 goto wrong_time;
850
851 /* wait for time update to complete */
852 /* If RTCSA_TUP is zero, we have at least 244us before next update */
853 s = splhigh();
854 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
855 splx(s);
856 s = splhigh();
857 }
858
859 days = 0;
860#ifdef USE_RTC_CENTURY
861 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
862#else
863 year = readrtc(RTC_YEAR) + 1900;
864 if (year < 1970)
865 year += 100;
866#endif
867 if (year < 1970) {
868 splx(s);
869 goto wrong_time;
870 }
871 month = readrtc(RTC_MONTH);
872 for (m = 1; m < month; m++)
873 days += daysinmonth[m-1];
874 if ((month > 2) && LEAPYEAR(year))
875 days ++;
876 days += readrtc(RTC_DAY) - 1;
877 yd = days;
878 for (y = 1970; y < year; y++)
879 days += DAYSPERYEAR + LEAPYEAR(y);
880 sec = ((( days * 24 +
881 readrtc(RTC_HRS)) * 60 +
882 readrtc(RTC_MIN)) * 60 +
883 readrtc(RTC_SEC));
884 /* sec now contains the number of seconds, since Jan 1 1970,
885 in the local time zone */
886
887 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
888
889 y = time_second - sec;
890 if (y <= -2 || y >= 2) {
891 /* badly off, adjust it */
892 ts.tv_sec = sec;
893 ts.tv_nsec = 0;
894 tc_setclock(&ts);
895 }
896 splx(s);
897 return;
898
899wrong_time:
900 printf("Invalid time in real time clock.\n");
901 printf("Check and reset the date immediately!\n");
902}
903
904/*
905 * Write system time back to RTC
906 */
907void
908resettodr()
909{
910 unsigned long tm;
911 int y, m, s;
912
913 if (disable_rtc_set)
914 return;
915
916 s = splclock();
917 tm = time_second;
918 splx(s);
919
920 /* Disable RTC updates and interrupts. */
921 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
922
923 /* Calculate local time to put in RTC */
924
925 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
926
927 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
928 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
929 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
930
931 /* We have now the days since 01-01-1970 in tm */
932 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
933 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
934 tm >= m;
935 y++, m = DAYSPERYEAR + LEAPYEAR(y))
936 tm -= m;
937
938 /* Now we have the years in y and the day-of-the-year in tm */
939 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
940#ifdef USE_RTC_CENTURY
941 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
942#endif
943 for (m = 0; ; m++) {
944 int ml;
945
946 ml = daysinmonth[m];
947 if (m == 1 && LEAPYEAR(y))
948 ml++;
949 if (tm < ml)
950 break;
951 tm -= ml;
952 }
953
954 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
955 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
956
957 /* Reenable RTC updates and interrupts. */
958 writertc(RTC_STATUSB, rtc_statusb);
959}
960
961
962/*
963 * Start both clocks running.
964 */
965void
966cpu_initclocks()
967{
968 int diag;
969#ifdef APIC_IO
970 int apic_8254_trial;
971 struct intrhand *clkdesc;
972#endif /* APIC_IO */
973
974 if (statclock_disable) {
975 /*
976 * The stat interrupt mask is different without the
977 * statistics clock. Also, don't set the interrupt
978 * flag which would normally cause the RTC to generate
979 * interrupts.
980 */
981 rtc_statusb = RTCSB_24HR;
982 } else {
983 /* Setting stathz to nonzero early helps avoid races. */
984 stathz = RTC_NOPROFRATE;
985 profhz = RTC_PROFRATE;
986 }
987
988 /* Finish initializing 8253 timer 0. */
989#ifdef APIC_IO
990
991 apic_8254_intr = isa_apic_irq(0);
992 apic_8254_trial = 0;
993 if (apic_8254_intr >= 0 ) {
994 if (apic_int_type(0, 0) == 3)
995 apic_8254_trial = 1;
996 } else {
997 /* look for ExtInt on pin 0 */
998 if (apic_int_type(0, 0) == 3) {
999 apic_8254_intr = apic_irq(0, 0);
1000 setup_8254_mixed_mode();
1001 } else
1002 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1003 }
1004
1005 clkdesc = inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr,
1006 NULL, PI_REALTIME, INTR_FAST);
1007 INTREN(1 << apic_8254_intr);
1008
1009#else /* APIC_IO */
1010
1011 /*
1012 * XXX Check the priority of this interrupt handler. I
1013 * couldn't find anything suitable in the BSD/OS code (grog,
1014 * 19 July 2000).
1015 */
1016 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL, PI_REALTIME,
1017 INTR_FAST);
1018 INTREN(IRQ0);
1019
1020#endif /* APIC_IO */
1021
1022 /* Initialize RTC. */
1023 writertc(RTC_STATUSA, rtc_statusa);
1024 writertc(RTC_STATUSB, RTCSB_24HR);
1025
1026 /* Don't bother enabling the statistics clock. */
1027 if (statclock_disable)
1028 return;
1029 diag = rtcin(RTC_DIAG);
1030 if (diag != 0)
1031 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1032
1033#ifdef APIC_IO
1034 if (isa_apic_irq(8) != 8)
1035 panic("APIC RTC != 8");
1036#endif /* APIC_IO */
1037
1038 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL, PI_REALTIME,
1039 INTR_FAST);
1040
1041#ifdef APIC_IO
1042 INTREN(APIC_IRQ8);
1043#else
1044 INTREN(IRQ8);
1045#endif /* APIC_IO */
1046
1047 writertc(RTC_STATUSB, rtc_statusb);
1048
1049#ifdef APIC_IO
1050 if (apic_8254_trial) {
1051
1052 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1053 while (read_intr_count(8) < 6)
1054 ; /* nothing */
1055 if (read_intr_count(apic_8254_intr) < 3) {
1056 /*
1057 * The MP table is broken.
1058 * The 8254 was not connected to the specified pin
1059 * on the IO APIC.
1060 * Workaround: Limited variant of mixed mode.
1061 */
1062 INTRDIS(1 << apic_8254_intr);
1063 inthand_remove(clkdesc);
1064 printf("APIC_IO: Broken MP table detected: "
1065 "8254 is not connected to "
1066 "IOAPIC #%d intpin %d\n",
1067 int_to_apicintpin[apic_8254_intr].ioapic,
1068 int_to_apicintpin[apic_8254_intr].int_pin);
1069 /*
1070 * Revoke current ISA IRQ 0 assignment and
1071 * configure a fallback interrupt routing from
1072 * the 8254 Timer via the 8259 PIC to the
1073 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1074 * We reuse the low level interrupt handler number.
1075 */
1076 if (apic_irq(0, 0) < 0) {
1077 revoke_apic_irq(apic_8254_intr);
1078 assign_apic_irq(0, 0, apic_8254_intr);
1079 }
1080 apic_8254_intr = apic_irq(0, 0);
1081 setup_8254_mixed_mode();
1082 inthand_add("clk", apic_8254_intr,
1083 (driver_intr_t *)clkintr, NULL,
1084 PI_REALTIME, INTR_FAST);
1085 INTREN(1 << apic_8254_intr);
1086 }
1087
1088 }
1089 if (apic_int_type(0, 0) != 3 ||
1090 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1091 int_to_apicintpin[apic_8254_intr].int_pin != 0)
1092 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1093 int_to_apicintpin[apic_8254_intr].ioapic,
1094 int_to_apicintpin[apic_8254_intr].int_pin);
1095 else
1096 printf("APIC_IO: "
1097 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1098#endif
1099
1100}
1101
1102#ifdef APIC_IO
1103static u_long
1104read_intr_count(int vec)
1105{
1106 u_long *up;
1107 up = intr_countp[vec];
1108 if (up)
1109 return *up;
1110 return 0UL;
1111}
1112
1113static void
1114setup_8254_mixed_mode()
1115{
1116 /*
1117 * Allow 8254 timer to INTerrupt 8259:
1118 * re-initialize master 8259:
1119 * reset; prog 4 bytes, single ICU, edge triggered
1120 */
1121 outb(IO_ICU1, 0x13);
1122 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1123 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1124 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1125 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1126
1127 /* program IO APIC for type 3 INT on INT0 */
1128 if (ext_int_setup(0, 0) < 0)
1129 panic("8254 redirect via APIC pin0 impossible!");
1130}
1131#endif
1132
1133void
1134setstatclockrate(int newhz)
1135{
1136 if (newhz == RTC_PROFRATE)
1137 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1138 else
1139 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1140 writertc(RTC_STATUSA, rtc_statusa);
1141}
1142
1143static int
1144sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1145{
1146 int error;
1147 u_int freq;
1148
1149 /*
1150 * Use `i8254' instead of `timer' in external names because `timer'
1151 * is is too generic. Should use it everywhere.
1152 */
1153 freq = timer_freq;
1154 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1155 if (error == 0 && req->newptr != NULL) {
1156 if (timer0_state != RELEASED)
1157 return (EBUSY); /* too much trouble to handle */
1158 set_timer_freq(freq, hz);
1159 i8254_timecounter.tc_frequency = freq;
1160 tc_update(&i8254_timecounter);
1161 }
1162 return (error);
1163}
1164
1165SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1166 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
1167
1168static int
1169sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1170{
1171 int error;
1172 u_int freq;
1173
1174 if (tsc_timecounter.tc_frequency == 0)
1175 return (EOPNOTSUPP);
1176 freq = tsc_freq;
1177 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1178 if (error == 0 && req->newptr != NULL) {
1179 tsc_freq = freq;
1180 tsc_timecounter.tc_frequency = tsc_freq;
1181 tc_update(&tsc_timecounter);
1182 }
1183 return (error);
1184}
1185
1186SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1187 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", "");
1188
1189static unsigned
1190i8254_get_timecount(struct timecounter *tc)
1191{
1192 u_int count;
1193 u_int high, low;
1194 u_int eflags;
1195
1196 eflags = read_eflags();
|
1197 mtx_enter(&clock_lock, MTX_SPIN);
| 1197 mtx_lock_spin(&clock_lock);
|
1198
1199 /* Select timer0 and latch counter value. */
1200 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1201
1202 low = inb(TIMER_CNTR0);
1203 high = inb(TIMER_CNTR0);
1204 count = timer0_max_count - ((high << 8) | low);
1205 if (count < i8254_lastcount ||
1206 (!i8254_ticked && (clkintr_pending ||
1207 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
1208#ifdef APIC_IO
1209#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
1210 /* XXX this assumes that apic_8254_intr is < 24. */
1211 (lapic_irr1 & (1 << apic_8254_intr))))
1212#else
1213 (inb(IO_ICU1) & 1)))
1214#endif
1215 )) {
1216 i8254_ticked = 1;
1217 i8254_offset += timer0_max_count;
1218 }
1219 i8254_lastcount = count;
1220 count += i8254_offset;
| 1198
1199 /* Select timer0 and latch counter value. */
1200 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1201
1202 low = inb(TIMER_CNTR0);
1203 high = inb(TIMER_CNTR0);
1204 count = timer0_max_count - ((high << 8) | low);
1205 if (count < i8254_lastcount ||
1206 (!i8254_ticked && (clkintr_pending ||
1207 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
1208#ifdef APIC_IO
1209#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
1210 /* XXX this assumes that apic_8254_intr is < 24. */
1211 (lapic_irr1 & (1 << apic_8254_intr))))
1212#else
1213 (inb(IO_ICU1) & 1)))
1214#endif
1215 )) {
1216 i8254_ticked = 1;
1217 i8254_offset += timer0_max_count;
1218 }
1219 i8254_lastcount = count;
1220 count += i8254_offset;
|
1221 mtx_exit(&clock_lock, MTX_SPIN);
| 1221 mtx_unlock_spin(&clock_lock);
|
1222 return (count);
1223}
1224
1225static unsigned
1226tsc_get_timecount(struct timecounter *tc)
1227{
1228 return (rdtsc());
1229}
1230
1231/*
1232 * Attach to the ISA PnP descriptors for the timer and realtime clock.
1233 */
1234static struct isa_pnp_id attimer_ids[] = {
1235 { 0x0001d041 /* PNP0100 */, "AT timer" },
1236 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
1237 { 0 }
1238};
1239
1240static int
1241attimer_probe(device_t dev)
1242{
1243 int result;
1244
1245 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
1246 device_quiet(dev);
1247 return(result);
1248}
1249
1250static int
1251attimer_attach(device_t dev)
1252{
1253 return(0);
1254}
1255
1256static device_method_t attimer_methods[] = {
1257 /* Device interface */
1258 DEVMETHOD(device_probe, attimer_probe),
1259 DEVMETHOD(device_attach, attimer_attach),
1260 DEVMETHOD(device_detach, bus_generic_detach),
1261 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1262 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
1263 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
1264 { 0, 0 }
1265};
1266
1267static driver_t attimer_driver = {
1268 "attimer",
1269 attimer_methods,
1270 1, /* no softc */
1271};
1272
1273static devclass_t attimer_devclass;
1274
1275DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
| 1222 return (count);
1223}
1224
1225static unsigned
1226tsc_get_timecount(struct timecounter *tc)
1227{
1228 return (rdtsc());
1229}
1230
1231/*
1232 * Attach to the ISA PnP descriptors for the timer and realtime clock.
1233 */
1234static struct isa_pnp_id attimer_ids[] = {
1235 { 0x0001d041 /* PNP0100 */, "AT timer" },
1236 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
1237 { 0 }
1238};
1239
1240static int
1241attimer_probe(device_t dev)
1242{
1243 int result;
1244
1245 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
1246 device_quiet(dev);
1247 return(result);
1248}
1249
1250static int
1251attimer_attach(device_t dev)
1252{
1253 return(0);
1254}
1255
1256static device_method_t attimer_methods[] = {
1257 /* Device interface */
1258 DEVMETHOD(device_probe, attimer_probe),
1259 DEVMETHOD(device_attach, attimer_attach),
1260 DEVMETHOD(device_detach, bus_generic_detach),
1261 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1262 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
1263 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
1264 { 0, 0 }
1265};
1266
1267static driver_t attimer_driver = {
1268 "attimer",
1269 attimer_methods,
1270 1, /* no softc */
1271};
1272
1273static devclass_t attimer_devclass;
1274
1275DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
|