| specialreg.h (2497) | specialreg.h (5594) |
|---|---|
| 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
| 34 * $Id: specialreg.h,v 1.4 1994/09/04 19:59:24 pst Exp $ | 34 * $Id: specialreg.h,v 1.5 1994/09/04 23:10:27 davidg Exp $ |
| 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ | 35 */ 36 37#ifndef _MACHINE_SPECIALREG_H_ |
| 38#define _MACHINE_SPECIALREG_H_ 1 | 38#define _MACHINE_SPECIALREG_H_ |
| 39 40/* 41 * Bits in 386 special registers: 42 */ | 39 40/* 41 * Bits in 386 special registers: 42 */ |
| 43 | |
| 44#define CR0_PE 0x00000001 /* Protected mode Enable */ 45#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 46#ifdef notused 47#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 48#endif 49#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 50#ifdef notused 51#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 52#endif 53#define CR0_PG 0x80000000 /* PaGing enable */ 54 55/* 56 * Bits in 486 special registers: 57 */ | 43#define CR0_PE 0x00000001 /* Protected mode Enable */ 44#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 45#ifdef notused 46#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 47#endif 48#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 49#ifdef notused 50#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 51#endif 52#define CR0_PG 0x80000000 /* PaGing enable */ 53 54/* 55 * Bits in 486 special registers: 56 */ |
| 58 | |
| 59#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 60#define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ | 57#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 58#define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */ |
| 61#ifdef notyet | |
| 62#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ | 59#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ |
| 63#endif | |
| 64 65/* 66 * Cyrix 486 DLC special registers, accessable as IO ports. 67 */ 68#define CCR0 0xc0 /* configuration control register 0 */ 69#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is 70 non-cacheable */ 71#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ --- 37 unchanged lines hidden (view full) --- 109#define NCR_SIZE_1M 9 110#define NCR_SIZE_2M 10 111#define NCR_SIZE_4M 11 112#define NCR_SIZE_8M 12 113#define NCR_SIZE_16M 13 114#define NCR_SIZE_32M 14 115#define NCR_SIZE_4G 15 116 | 60 61/* 62 * Cyrix 486 DLC special registers, accessable as IO ports. 63 */ 64#define CCR0 0xc0 /* configuration control register 0 */ 65#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is 66 non-cacheable */ 67#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ --- 37 unchanged lines hidden (view full) --- 105#define NCR_SIZE_1M 9 106#define NCR_SIZE_2M 10 107#define NCR_SIZE_4M 11 108#define NCR_SIZE_8M 12 109#define NCR_SIZE_16M 13 110#define NCR_SIZE_32M 14 111#define NCR_SIZE_4G 15 112 |
| 117#endif /* _MACHINE_SPECIALREG_H_ */ | 113#endif /* !_MACHINE_SPECIALREG_H_ */ |