28#include "opt_cpu.h"
29#include "opt_kstack_pages.h"
30#include "opt_swtch.h"
31
32#ifdef SMP
33#include <machine/smptests.h>
34#else
35#error
36#endif
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/bus.h>
41#include <sys/cons.h> /* cngetc() */
42#ifdef GPROF
43#include <sys/gmon.h>
44#endif
45#include <sys/kernel.h>
46#include <sys/ktr.h>
47#include <sys/lock.h>
48#include <sys/malloc.h>
49#include <sys/memrange.h>
50#include <sys/mutex.h>
51#include <sys/pcpu.h>
52#include <sys/proc.h>
53#include <sys/smp.h>
54#include <sys/sysctl.h>
55#include <sys/user.h>
56
57#include <vm/vm.h>
58#include <vm/vm_param.h>
59#include <vm/pmap.h>
60#include <vm/vm_kern.h>
61#include <vm/vm_extern.h>
62#include <vm/vm_map.h>
63
64#include <machine/apic.h>
65#include <machine/atomic.h>
66#include <machine/clock.h>
67#include <machine/cpu.h>
68#include <machine/cpufunc.h>
69#include <machine/mpapic.h>
70#include <machine/psl.h>
71#include <machine/segments.h>
72#include <machine/smp.h>
73#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
74#include <machine/tss.h>
75#include <machine/specialreg.h>
76#include <machine/privatespace.h>
77
78#if defined(APIC_IO)
79#include <machine/md_var.h> /* setidt() */
80#include <i386/isa/icu.h> /* IPIs */
81#include <i386/isa/intr_machdep.h> /* IPIs */
82#endif /* APIC_IO */
83
84#if defined(TEST_DEFAULT_CONFIG)
85#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
86#else
87#define MPFPS_MPFB1 mpfps->mpfb1
88#endif /* TEST_DEFAULT_CONFIG */
89
90#define WARMBOOT_TARGET 0
91#define WARMBOOT_OFF (KERNBASE + 0x0467)
92#define WARMBOOT_SEG (KERNBASE + 0x0469)
93
94#ifdef PC98
95#define BIOS_BASE (0xe8000)
96#define BIOS_SIZE (0x18000)
97#else
98#define BIOS_BASE (0xf0000)
99#define BIOS_SIZE (0x10000)
100#endif
101#define BIOS_COUNT (BIOS_SIZE/4)
102
103#define CMOS_REG (0x70)
104#define CMOS_DATA (0x71)
105#define BIOS_RESET (0x0f)
106#define BIOS_WARM (0x0a)
107
108#define PROCENTRY_FLAG_EN 0x01
109#define PROCENTRY_FLAG_BP 0x02
110#define IOAPICENTRY_FLAG_EN 0x01
111
112
113/* MP Floating Pointer Structure */
114typedef struct MPFPS {
115 char signature[4];
116 void *pap;
117 u_char length;
118 u_char spec_rev;
119 u_char checksum;
120 u_char mpfb1;
121 u_char mpfb2;
122 u_char mpfb3;
123 u_char mpfb4;
124 u_char mpfb5;
125} *mpfps_t;
126
127/* MP Configuration Table Header */
128typedef struct MPCTH {
129 char signature[4];
130 u_short base_table_length;
131 u_char spec_rev;
132 u_char checksum;
133 u_char oem_id[8];
134 u_char product_id[12];
135 void *oem_table_pointer;
136 u_short oem_table_size;
137 u_short entry_count;
138 void *apic_address;
139 u_short extended_table_length;
140 u_char extended_table_checksum;
141 u_char reserved;
142} *mpcth_t;
143
144
145typedef struct PROCENTRY {
146 u_char type;
147 u_char apic_id;
148 u_char apic_version;
149 u_char cpu_flags;
150 u_long cpu_signature;
151 u_long feature_flags;
152 u_long reserved1;
153 u_long reserved2;
154} *proc_entry_ptr;
155
156typedef struct BUSENTRY {
157 u_char type;
158 u_char bus_id;
159 char bus_type[6];
160} *bus_entry_ptr;
161
162typedef struct IOAPICENTRY {
163 u_char type;
164 u_char apic_id;
165 u_char apic_version;
166 u_char apic_flags;
167 void *apic_address;
168} *io_apic_entry_ptr;
169
170typedef struct INTENTRY {
171 u_char type;
172 u_char int_type;
173 u_short int_flags;
174 u_char src_bus_id;
175 u_char src_bus_irq;
176 u_char dst_apic_id;
177 u_char dst_apic_int;
178} *int_entry_ptr;
179
180/* descriptions of MP basetable entries */
181typedef struct BASETABLE_ENTRY {
182 u_char type;
183 u_char length;
184 char name[16];
185} basetable_entry;
186
187/*
188 * this code MUST be enabled here and in mpboot.s.
189 * it follows the very early stages of AP boot by placing values in CMOS ram.
190 * it NORMALLY will never be needed and thus the primitive method for enabling.
191 *
192#define CHECK_POINTS
193 */
194
195#if defined(CHECK_POINTS) && !defined(PC98)
196#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
197#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
198
199#define CHECK_INIT(D); \
200 CHECK_WRITE(0x34, (D)); \
201 CHECK_WRITE(0x35, (D)); \
202 CHECK_WRITE(0x36, (D)); \
203 CHECK_WRITE(0x37, (D)); \
204 CHECK_WRITE(0x38, (D)); \
205 CHECK_WRITE(0x39, (D));
206
207#define CHECK_PRINT(S); \
208 printf("%s: %d, %d, %d, %d, %d, %d\n", \
209 (S), \
210 CHECK_READ(0x34), \
211 CHECK_READ(0x35), \
212 CHECK_READ(0x36), \
213 CHECK_READ(0x37), \
214 CHECK_READ(0x38), \
215 CHECK_READ(0x39));
216
217#else /* CHECK_POINTS */
218
219#define CHECK_INIT(D)
220#define CHECK_PRINT(S)
221
222#endif /* CHECK_POINTS */
223
224/*
225 * Values to send to the POST hardware.
226 */
227#define MP_BOOTADDRESS_POST 0x10
228#define MP_PROBE_POST 0x11
229#define MPTABLE_PASS1_POST 0x12
230
231#define MP_START_POST 0x13
232#define MP_ENABLE_POST 0x14
233#define MPTABLE_PASS2_POST 0x15
234
235#define START_ALL_APS_POST 0x16
236#define INSTALL_AP_TRAMP_POST 0x17
237#define START_AP_POST 0x18
238
239#define MP_ANNOUNCE_POST 0x19
240
241static int need_hyperthreading_fixup;
242static u_int logical_cpus;
243static u_int logical_cpus_mask;
244
245/* used to hold the AP's until we are ready to release them */
246static struct mtx ap_boot_mtx;
247
248/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
249int current_postcode;
250
251/** XXX FIXME: what system files declare these??? */
252extern struct region_descriptor r_gdt, r_idt;
253
254int bsp_apic_ready = 0; /* flags useability of BSP apic */
255int mp_naps; /* # of Applications processors */
256int mp_nbusses; /* # of busses */
257int mp_napics; /* # of IO APICs */
258int boot_cpu_id; /* designated BSP */
259vm_offset_t cpu_apic_address;
260vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
261extern int nkpt;
262
263u_int32_t cpu_apic_versions[MAXCPU];
264u_int32_t *io_apic_versions;
265
266#ifdef APIC_INTR_REORDER
267struct {
268 volatile int *location;
269 int bit;
270} apic_isrbit_location[32];
271#endif
272
273struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
274
275/*
276 * APIC ID logical/physical mapping structures.
277 * We oversize these to simplify boot-time config.
278 */
279int cpu_num_to_apic_id[NAPICID];
280int io_num_to_apic_id[NAPICID];
281int apic_id_to_logical[NAPICID];
282
283
284/* AP uses this during bootstrap. Do not staticize. */
285char *bootSTK;
286static int bootAP;
287
288/* Hotwire a 0->4MB V==P mapping */
289extern pt_entry_t *KPTphys;
290
291/* SMP page table page */
292extern pt_entry_t *SMPpt;
293
294struct pcb stoppcbs[MAXCPU];
295
296#ifdef APIC_IO
297/* Variables needed for SMP tlb shootdown. */
298vm_offset_t smp_tlb_addr1;
299vm_offset_t smp_tlb_addr2;
300volatile int smp_tlb_wait;
301static struct mtx smp_tlb_mtx;
302#endif
303
304/*
305 * Local data and functions.
306 */
307
308/* Set to 1 once we're ready to let the APs out of the pen. */
309static volatile int aps_ready = 0;
310
311static int mp_capable;
312static u_int boot_address;
313static u_int base_memory;
314
315static int picmode; /* 0: virtual wire mode, 1: PIC mode */
316static mpfps_t mpfps;
317static int search_for_sig(u_int32_t target, int count);
318static void mp_enable(u_int boot_addr);
319
320static void mptable_hyperthread_fixup(u_int id_mask);
321static void mptable_pass1(void);
322static int mptable_pass2(void);
323static void default_mp_table(int type);
324static void fix_mp_table(void);
325static void setup_apic_irq_mapping(void);
326static void init_locks(void);
327static int start_all_aps(u_int boot_addr);
328static void install_ap_tramp(u_int boot_addr);
329static int start_ap(int logicalCpu, u_int boot_addr);
330void ap_init(void);
331static int apic_int_is_bus_type(int intr, int bus_type);
332static void release_aps(void *dummy);
333
334/*
335 * initialize all the SMP locks
336 */
337
338/* lock region used by kernel profiling */
339int mcount_lock;
340
341#ifdef USE_COMLOCK
342/* locks com (tty) data/hardware accesses: a FASTINTR() */
343struct mtx com_mtx;
344#endif /* USE_COMLOCK */
345
346static void
347init_locks(void)
348{
349
350#ifdef USE_COMLOCK
351 mtx_init(&com_mtx, "com", NULL, MTX_SPIN);
352#endif /* USE_COMLOCK */
353#ifdef APIC_IO
354 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN);
355#endif
356}
357
358/*
359 * Calculate usable address in base memory for AP trampoline code.
360 */
361u_int
362mp_bootaddress(u_int basemem)
363{
364 POSTCODE(MP_BOOTADDRESS_POST);
365
366 base_memory = basemem * 1024; /* convert to bytes */
367
368 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
369 if ((base_memory - boot_address) < bootMP_size)
370 boot_address -= 4096; /* not enough, lower by 4k */
371
372 return boot_address;
373}
374
375
376/*
377 * Look for an Intel MP spec table (ie, SMP capable hardware).
378 */
379void
380i386_mp_probe(void)
381{
382 int x;
383 u_long segment;
384 u_int32_t target;
385
386 POSTCODE(MP_PROBE_POST);
387
388 /* see if EBDA exists */
389 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
390 /* search first 1K of EBDA */
391 target = (u_int32_t) (segment << 4);
392 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
393 goto found;
394 } else {
395 /* last 1K of base memory, effective 'top of base' passed in */
396 target = (u_int32_t) (base_memory - 0x400);
397 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
398 goto found;
399 }
400
401 /* search the BIOS */
402 target = (u_int32_t) BIOS_BASE;
403 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
404 goto found;
405
406 /* nothing found */
407 mpfps = (mpfps_t)0;
408 mp_capable = 0;
409 return;
410
411found:
412 /* calculate needed resources */
413 mpfps = (mpfps_t)x;
414 mptable_pass1();
415
416 /* flag fact that we are running multiple processors */
417 mp_capable = 1;
418}
419
420int
421cpu_mp_probe(void)
422{
423 /*
424 * Record BSP in CPU map
425 * This is done here so that MBUF init code works correctly.
426 */
427 all_cpus = 1;
428
429 return (mp_capable);
430}
431
432/*
433 * Initialize the SMP hardware and the APIC and start up the AP's.
434 */
435void
436cpu_mp_start(void)
437{
438 POSTCODE(MP_START_POST);
439
440 /* look for MP capable motherboard */
441 if (mp_capable)
442 mp_enable(boot_address);
443 else
444 panic("MP hardware not found!");
445
446 cpu_setregs();
447}
448
449
450/*
451 * Print various information about the SMP system hardware and setup.
452 */
453void
454cpu_mp_announce(void)
455{
456 int x;
457
458 POSTCODE(MP_ANNOUNCE_POST);
459
460 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
461 printf(", version: 0x%08x", cpu_apic_versions[0]);
462 printf(", at 0x%08x\n", cpu_apic_address);
463 for (x = 1; x <= mp_naps; ++x) {
464 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
465 printf(", version: 0x%08x", cpu_apic_versions[x]);
466 printf(", at 0x%08x\n", cpu_apic_address);
467 }
468
469#if defined(APIC_IO)
470 for (x = 0; x < mp_napics; ++x) {
471 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
472 printf(", version: 0x%08x", io_apic_versions[x]);
473 printf(", at 0x%08x\n", io_apic_address[x]);
474 }
475#else
476 printf(" Warning: APIC I/O disabled\n");
477#endif /* APIC_IO */
478}
479
480/*
481 * AP cpu's call this to sync up protected mode.
482 */
483void
484init_secondary(void)
485{
486 int gsel_tss;
487 int x, myid = bootAP;
488 u_int cr0;
489
490 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
491 gdt_segs[GPROC0_SEL].ssd_base =
492 (int) &SMP_prvspace[myid].pcpu.pc_common_tss;
493 SMP_prvspace[myid].pcpu.pc_prvspace =
494 &SMP_prvspace[myid].pcpu;
495
496 for (x = 0; x < NGDT; x++) {
497 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
498 }
499
500 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
501 r_gdt.rd_base = (int) &gdt[myid * NGDT];
502 lgdt(&r_gdt); /* does magic intra-segment return */
503
504 lidt(&r_idt);
505
506 lldt(_default_ldt);
507 PCPU_SET(currentldt, _default_ldt);
508
509 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
510 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
511 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
512 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
513 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
514 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
515 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
516 ltr(gsel_tss);
517
518 /*
519 * Set to a known state:
520 * Set by mpboot.s: CR0_PG, CR0_PE
521 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
522 */
523 cr0 = rcr0();
524 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
525 load_cr0(cr0);
526
527 pmap_set_opt();
528}
529
530
531#if defined(APIC_IO)
532/*
533 * Final configuration of the BSP's local APIC:
534 * - disable 'pic mode'.
535 * - disable 'virtual wire mode'.
536 * - enable NMI.
537 */
538void
539bsp_apic_configure(void)
540{
541 u_char byte;
542 u_int32_t temp;
543
544 /* leave 'pic mode' if necessary */
545 if (picmode) {
546 outb(0x22, 0x70); /* select IMCR */
547 byte = inb(0x23); /* current contents */
548 byte |= 0x01; /* mask external INTR */
549 outb(0x23, byte); /* disconnect 8259s/NMI */
550 }
551
552 /* mask lint0 (the 8259 'virtual wire' connection) */
553 temp = lapic.lvt_lint0;
554 temp |= APIC_LVT_M; /* set the mask */
555 lapic.lvt_lint0 = temp;
556
557 /* setup lint1 to handle NMI */
558 temp = lapic.lvt_lint1;
559 temp &= ~APIC_LVT_M; /* clear the mask */
560 lapic.lvt_lint1 = temp;
561
562 if (bootverbose)
563 apic_dump("bsp_apic_configure()");
564}
565#endif /* APIC_IO */
566
567
568/*******************************************************************
569 * local functions and data
570 */
571
572/*
573 * start the SMP system
574 */
575static void
576mp_enable(u_int boot_addr)
577{
578 int x;
579#if defined(APIC_IO)
580 int apic;
581 u_int ux;
582#endif /* APIC_IO */
583
584 POSTCODE(MP_ENABLE_POST);
585
586 /* turn on 4MB of V == P addressing so we can get to MP table */
587 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
588 invltlb();
589
590 /* examine the MP table for needed info, uses physical addresses */
591 x = mptable_pass2();
592
593 *(int *)PTD = 0;
594 invltlb();
595
596 /* can't process default configs till the CPU APIC is pmapped */
597 if (x)
598 default_mp_table(x);
599
600 /* post scan cleanup */
601 fix_mp_table();
602 setup_apic_irq_mapping();
603
604#if defined(APIC_IO)
605
606 /* fill the LOGICAL io_apic_versions table */
607 for (apic = 0; apic < mp_napics; ++apic) {
608 ux = io_apic_read(apic, IOAPIC_VER);
609 io_apic_versions[apic] = ux;
610 io_apic_set_id(apic, IO_TO_ID(apic));
611 }
612
613 /* program each IO APIC in the system */
614 for (apic = 0; apic < mp_napics; ++apic)
615 if (io_apic_setup(apic) < 0)
616 panic("IO APIC setup failure");
617
618 /* install a 'Spurious INTerrupt' vector */
619 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
620 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
621
622 /* install an inter-CPU IPI for TLB invalidation */
623 setidt(XINVLTLB_OFFSET, Xinvltlb,
624 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
625 setidt(XINVLPG_OFFSET, Xinvlpg,
626 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
627 setidt(XINVLRNG_OFFSET, Xinvlrng,
628 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
629
630 /* install an inter-CPU IPI for forwarding hardclock() */
631 setidt(XHARDCLOCK_OFFSET, Xhardclock,
632 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
633
634 /* install an inter-CPU IPI for forwarding statclock() */
635 setidt(XSTATCLOCK_OFFSET, Xstatclock,
636 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
637
638#ifdef LAZY_SWITCH
639 /* install an inter-CPU IPI for lazy pmap release */
640 setidt(XLAZYPMAP_OFFSET, Xlazypmap,
641 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
642#endif
643
644 /* install an inter-CPU IPI for all-CPU rendezvous */
645 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
646 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
647
648 /* install an inter-CPU IPI for forcing an additional software trap */
649 setidt(XCPUAST_OFFSET, Xcpuast,
650 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
651
652 /* install an inter-CPU IPI for CPU stop/restart */
653 setidt(XCPUSTOP_OFFSET, Xcpustop,
654 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
655
656#if defined(TEST_TEST1)
657 /* install a "fake hardware INTerrupt" vector */
658 setidt(XTEST1_OFFSET, Xtest1,
659 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
660#endif /** TEST_TEST1 */
661
662#endif /* APIC_IO */
663
664 /* initialize all SMP locks */
665 init_locks();
666
667 /* start each Application Processor */
668 start_all_aps(boot_addr);
669}
670
671
672/*
673 * look for the MP spec signature
674 */
675
676/* string defined by the Intel MP Spec as identifying the MP table */
677#define MP_SIG 0x5f504d5f /* _MP_ */
678#define NEXT(X) ((X) += 4)
679static int
680search_for_sig(u_int32_t target, int count)
681{
682 int x;
683 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
684
685 for (x = 0; x < count; NEXT(x))
686 if (addr[x] == MP_SIG)
687 /* make array index a byte index */
688 return (target + (x * sizeof(u_int32_t)));
689
690 return -1;
691}
692
693
694static basetable_entry basetable_entry_types[] =
695{
696 {0, 20, "Processor"},
697 {1, 8, "Bus"},
698 {2, 8, "I/O APIC"},
699 {3, 8, "I/O INT"},
700 {4, 8, "Local INT"}
701};
702
703typedef struct BUSDATA {
704 u_char bus_id;
705 enum busTypes bus_type;
706} bus_datum;
707
708typedef struct INTDATA {
709 u_char int_type;
710 u_short int_flags;
711 u_char src_bus_id;
712 u_char src_bus_irq;
713 u_char dst_apic_id;
714 u_char dst_apic_int;
715 u_char int_vector;
716} io_int, local_int;
717
718typedef struct BUSTYPENAME {
719 u_char type;
720 char name[7];
721} bus_type_name;
722
723static bus_type_name bus_type_table[] =
724{
725 {CBUS, "CBUS"},
726 {CBUSII, "CBUSII"},
727 {EISA, "EISA"},
728 {MCA, "MCA"},
729 {UNKNOWN_BUSTYPE, "---"},
730 {ISA, "ISA"},
731 {MCA, "MCA"},
732 {UNKNOWN_BUSTYPE, "---"},
733 {UNKNOWN_BUSTYPE, "---"},
734 {UNKNOWN_BUSTYPE, "---"},
735 {UNKNOWN_BUSTYPE, "---"},
736 {UNKNOWN_BUSTYPE, "---"},
737 {PCI, "PCI"},
738 {UNKNOWN_BUSTYPE, "---"},
739 {UNKNOWN_BUSTYPE, "---"},
740 {UNKNOWN_BUSTYPE, "---"},
741 {UNKNOWN_BUSTYPE, "---"},
742 {XPRESS, "XPRESS"},
743 {UNKNOWN_BUSTYPE, "---"}
744};
745/* from MP spec v1.4, table 5-1 */
746static int default_data[7][5] =
747{
748/* nbus, id0, type0, id1, type1 */
749 {1, 0, ISA, 255, 255},
750 {1, 0, EISA, 255, 255},
751 {1, 0, EISA, 255, 255},
752 {1, 0, MCA, 255, 255},
753 {2, 0, ISA, 1, PCI},
754 {2, 0, EISA, 1, PCI},
755 {2, 0, MCA, 1, PCI}
756};
757
758
759/* the bus data */
760static bus_datum *bus_data;
761
762/* the IO INT data, one entry per possible APIC INTerrupt */
763static io_int *io_apic_ints;
764
765static int nintrs;
766
767static int processor_entry(proc_entry_ptr entry, int cpu);
768static int bus_entry(bus_entry_ptr entry, int bus);
769static int io_apic_entry(io_apic_entry_ptr entry, int apic);
770static int int_entry(int_entry_ptr entry, int intr);
771static int lookup_bus_type(char *name);
772
773
774/*
775 * 1st pass on motherboard's Intel MP specification table.
776 *
777 * initializes:
778 * mp_ncpus = 1
779 *
780 * determines:
781 * cpu_apic_address (common to all CPUs)
782 * io_apic_address[N]
783 * mp_naps
784 * mp_nbusses
785 * mp_napics
786 * nintrs
787 */
788static void
789mptable_pass1(void)
790{
791 int x;
792 mpcth_t cth;
793 int totalSize;
794 void* position;
795 int count;
796 int type;
797 u_int id_mask;
798
799 POSTCODE(MPTABLE_PASS1_POST);
800
801 /* clear various tables */
802 for (x = 0; x < NAPICID; ++x) {
803 io_apic_address[x] = ~0; /* IO APIC address table */
804 }
805
806 /* init everything to empty */
807 mp_naps = 0;
808 mp_nbusses = 0;
809 mp_napics = 0;
810 nintrs = 0;
811 id_mask = 0;
812
813 /* check for use of 'default' configuration */
814 if (MPFPS_MPFB1 != 0) {
815 /* use default addresses */
816 cpu_apic_address = DEFAULT_APIC_BASE;
817 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
818
819 /* fill in with defaults */
820 mp_naps = 2; /* includes BSP */
821 mp_maxid = 1;
822 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
823#if defined(APIC_IO)
824 mp_napics = 1;
825 nintrs = 16;
826#endif /* APIC_IO */
827 }
828 else {
829 if ((cth = mpfps->pap) == 0)
830 panic("MP Configuration Table Header MISSING!");
831
832 cpu_apic_address = (vm_offset_t) cth->apic_address;
833
834 /* walk the table, recording info of interest */
835 totalSize = cth->base_table_length - sizeof(struct MPCTH);
836 position = (u_char *) cth + sizeof(struct MPCTH);
837 count = cth->entry_count;
838
839 while (count--) {
840 switch (type = *(u_char *) position) {
841 case 0: /* processor_entry */
842 if (((proc_entry_ptr)position)->cpu_flags
843 & PROCENTRY_FLAG_EN) {
844 ++mp_naps;
845 mp_maxid++;
846 id_mask |= 1 <<
847 ((proc_entry_ptr)position)->apic_id;
848 }
849 break;
850 case 1: /* bus_entry */
851 ++mp_nbusses;
852 break;
853 case 2: /* io_apic_entry */
854 if (((io_apic_entry_ptr)position)->apic_flags
855 & IOAPICENTRY_FLAG_EN)
856 io_apic_address[mp_napics++] =
857 (vm_offset_t)((io_apic_entry_ptr)
858 position)->apic_address;
859 break;
860 case 3: /* int_entry */
861 ++nintrs;
862 break;
863 case 4: /* int_entry */
864 break;
865 default:
866 panic("mpfps Base Table HOSED!");
867 /* NOTREACHED */
868 }
869
870 totalSize -= basetable_entry_types[type].length;
871 (u_char*)position += basetable_entry_types[type].length;
872 }
873 }
874
875 /* qualify the numbers */
876 if (mp_naps > MAXCPU) {
877 printf("Warning: only using %d of %d available CPUs!\n",
878 MAXCPU, mp_naps);
879 mp_naps = MAXCPU;
880 }
881
882 /* See if we need to fixup HT logical CPUs. */
883 mptable_hyperthread_fixup(id_mask);
884
885 /*
886 * Count the BSP.
887 * This is also used as a counter while starting the APs.
888 */
889 mp_ncpus = 1;
890
891 --mp_naps; /* subtract the BSP */
892}
893
894
895/*
896 * 2nd pass on motherboard's Intel MP specification table.
897 *
898 * sets:
899 * boot_cpu_id
900 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
901 * CPU_TO_ID(N), logical CPU to APIC ID table
902 * IO_TO_ID(N), logical IO to APIC ID table
903 * bus_data[N]
904 * io_apic_ints[N]
905 */
906static int
907mptable_pass2(void)
908{
909 struct PROCENTRY proc;
910 int x;
911 mpcth_t cth;
912 int totalSize;
913 void* position;
914 int count;
915 int type;
916 int apic, bus, cpu, intr;
917 int i, j;
918 int pgeflag;
919
920 POSTCODE(MPTABLE_PASS2_POST);
921
922 /* Initialize fake proc entry for use with HT fixup. */
923 bzero(&proc, sizeof(proc));
924 proc.type = 0;
925 proc.cpu_flags = PROCENTRY_FLAG_EN;
926
927 pgeflag = 0; /* XXX - Not used under SMP yet. */
928
929 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
930 M_DEVBUF, M_WAITOK);
931 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
932 M_DEVBUF, M_WAITOK);
933 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
934 M_DEVBUF, M_WAITOK);
935 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
936 M_DEVBUF, M_WAITOK);
937
938 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
939
940 for (i = 0; i < mp_napics; i++) {
941 for (j = 0; j < mp_napics; j++) {
942 /* same page frame as a previous IO apic? */
943 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
944 (io_apic_address[i] & PG_FRAME)) {
945 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
946 + (NPTEPG-2-j) * PAGE_SIZE
947 + (io_apic_address[i] & PAGE_MASK));
948 break;
949 }
950 /* use this slot if available */
951 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
952 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
953 pgeflag | (io_apic_address[i] & PG_FRAME));
954 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
955 + (NPTEPG-2-j) * PAGE_SIZE
956 + (io_apic_address[i] & PAGE_MASK));
957 break;
958 }
959 }
960 }
961
962 /* clear various tables */
963 for (x = 0; x < NAPICID; ++x) {
964 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
965 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
966 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
967 }
968
969 /* clear bus data table */
970 for (x = 0; x < mp_nbusses; ++x)
971 bus_data[x].bus_id = 0xff;
972
973 /* clear IO APIC INT table */
974 for (x = 0; x < (nintrs + 1); ++x) {
975 io_apic_ints[x].int_type = 0xff;
976 io_apic_ints[x].int_vector = 0xff;
977 }
978
979 /* setup the cpu/apic mapping arrays */
980 boot_cpu_id = -1;
981
982 /* record whether PIC or virtual-wire mode */
983 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
984
985 /* check for use of 'default' configuration */
986 if (MPFPS_MPFB1 != 0)
987 return MPFPS_MPFB1; /* return default configuration type */
988
989 if ((cth = mpfps->pap) == 0)
990 panic("MP Configuration Table Header MISSING!");
991
992 /* walk the table, recording info of interest */
993 totalSize = cth->base_table_length - sizeof(struct MPCTH);
994 position = (u_char *) cth + sizeof(struct MPCTH);
995 count = cth->entry_count;
996 apic = bus = intr = 0;
997 cpu = 1; /* pre-count the BSP */
998
999 while (count--) {
1000 switch (type = *(u_char *) position) {
1001 case 0:
1002 if (processor_entry(position, cpu)) {
1003 if (logical_cpus != 0 &&
1004 cpu % logical_cpus != 0)
1005 logical_cpus_mask |= (1 << cpu);
1006 ++cpu;
1007 }
1008 if (need_hyperthreading_fixup) {
1009 /*
1010 * Create fake mptable processor entries
1011 * and feed them to processor_entry() to
1012 * enumerate the logical CPUs.
1013 */
1014 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1015 for (i = 1; i < logical_cpus; i++) {
1016 proc.apic_id++;
1017 (void)processor_entry(&proc, cpu);
1018 logical_cpus_mask |= (1 << cpu);
1019 cpu++;
1020 }
1021 }
1022 break;
1023 case 1:
1024 if (bus_entry(position, bus))
1025 ++bus;
1026 break;
1027 case 2:
1028 if (io_apic_entry(position, apic))
1029 ++apic;
1030 break;
1031 case 3:
1032 if (int_entry(position, intr))
1033 ++intr;
1034 break;
1035 case 4:
1036 /* int_entry(position); */
1037 break;
1038 default:
1039 panic("mpfps Base Table HOSED!");
1040 /* NOTREACHED */
1041 }
1042
1043 totalSize -= basetable_entry_types[type].length;
1044 (u_char *) position += basetable_entry_types[type].length;
1045 }
1046
1047 if (boot_cpu_id == -1)
1048 panic("NO BSP found!");
1049
1050 /* report fact that its NOT a default configuration */
1051 return 0;
1052}
1053
1054/*
1055 * Check if we should perform a hyperthreading "fix-up" to
1056 * enumerate any logical CPU's that aren't already listed
1057 * in the table.
1058 *
1059 * XXX: We assume that all of the physical CPUs in the
1060 * system have the same number of logical CPUs.
1061 *
1062 * XXX: We assume that APIC ID's are allocated such that
1063 * the APIC ID's for a physical processor are aligned
1064 * with the number of logical CPU's in the processor.
1065 */
1066static void
1067mptable_hyperthread_fixup(u_int id_mask)
1068{
1069 u_int i, id;
1070
1071 /* Nothing to do if there is no HTT support. */
1072 if ((cpu_feature & CPUID_HTT) == 0)
1073 return;
1074 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1075 if (logical_cpus <= 1)
1076 return;
1077
1078 /*
1079 * For each APIC ID of a CPU that is set in the mask,
1080 * scan the other candidate APIC ID's for this
1081 * physical processor. If any of those ID's are
1082 * already in the table, then kill the fixup.
1083 */
1084 for (id = 0; id <= MAXCPU; id++) {
1085 if ((id_mask & 1 << id) == 0)
1086 continue;
1087 /* First, make sure we are on a logical_cpus boundary. */
1088 if (id % logical_cpus != 0)
1089 return;
1090 for (i = id + 1; i < id + logical_cpus; i++)
1091 if ((id_mask & 1 << i) != 0)
1092 return;
1093 }
1094
1095 /*
1096 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1097 * mp_naps and mp_maxid right now.
1098 */
1099 need_hyperthreading_fixup = 1;
1100 mp_maxid *= logical_cpus;
1101 mp_naps *= logical_cpus;
1102}
1103
1104void
1105assign_apic_irq(int apic, int intpin, int irq)
1106{
1107 int x;
1108
1109 if (int_to_apicintpin[irq].ioapic != -1)
1110 panic("assign_apic_irq: inconsistent table");
1111
1112 int_to_apicintpin[irq].ioapic = apic;
1113 int_to_apicintpin[irq].int_pin = intpin;
1114 int_to_apicintpin[irq].apic_address = ioapic[apic];
1115 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1116
1117 for (x = 0; x < nintrs; x++) {
1118 if ((io_apic_ints[x].int_type == 0 ||
1119 io_apic_ints[x].int_type == 3) &&
1120 io_apic_ints[x].int_vector == 0xff &&
1121 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1122 io_apic_ints[x].dst_apic_int == intpin)
1123 io_apic_ints[x].int_vector = irq;
1124 }
1125}
1126
1127void
1128revoke_apic_irq(int irq)
1129{
1130 int x;
1131 int oldapic;
1132 int oldintpin;
1133
1134 if (int_to_apicintpin[irq].ioapic == -1)
1135 panic("revoke_apic_irq: inconsistent table");
1136
1137 oldapic = int_to_apicintpin[irq].ioapic;
1138 oldintpin = int_to_apicintpin[irq].int_pin;
1139
1140 int_to_apicintpin[irq].ioapic = -1;
1141 int_to_apicintpin[irq].int_pin = 0;
1142 int_to_apicintpin[irq].apic_address = NULL;
1143 int_to_apicintpin[irq].redirindex = 0;
1144
1145 for (x = 0; x < nintrs; x++) {
1146 if ((io_apic_ints[x].int_type == 0 ||
1147 io_apic_ints[x].int_type == 3) &&
1148 io_apic_ints[x].int_vector != 0xff &&
1149 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1150 io_apic_ints[x].dst_apic_int == oldintpin)
1151 io_apic_ints[x].int_vector = 0xff;
1152 }
1153}
1154
1155
1156static void
1157allocate_apic_irq(int intr)
1158{
1159 int apic;
1160 int intpin;
1161 int irq;
1162
1163 if (io_apic_ints[intr].int_vector != 0xff)
1164 return; /* Interrupt handler already assigned */
1165
1166 if (io_apic_ints[intr].int_type != 0 &&
1167 (io_apic_ints[intr].int_type != 3 ||
1168 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1169 io_apic_ints[intr].dst_apic_int == 0)))
1170 return; /* Not INT or ExtInt on != (0, 0) */
1171
1172 irq = 0;
1173 while (irq < APIC_INTMAPSIZE &&
1174 int_to_apicintpin[irq].ioapic != -1)
1175 irq++;
1176
1177 if (irq >= APIC_INTMAPSIZE)
1178 return; /* No free interrupt handlers */
1179
1180 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1181 intpin = io_apic_ints[intr].dst_apic_int;
1182
1183 assign_apic_irq(apic, intpin, irq);
1184 io_apic_setup_intpin(apic, intpin);
1185}
1186
1187
1188static void
1189swap_apic_id(int apic, int oldid, int newid)
1190{
1191 int x;
1192 int oapic;
1193
1194
1195 if (oldid == newid)
1196 return; /* Nothing to do */
1197
1198 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1199 apic, oldid, newid);
1200
1201 /* Swap physical APIC IDs in interrupt entries */
1202 for (x = 0; x < nintrs; x++) {
1203 if (io_apic_ints[x].dst_apic_id == oldid)
1204 io_apic_ints[x].dst_apic_id = newid;
1205 else if (io_apic_ints[x].dst_apic_id == newid)
1206 io_apic_ints[x].dst_apic_id = oldid;
1207 }
1208
1209 /* Swap physical APIC IDs in IO_TO_ID mappings */
1210 for (oapic = 0; oapic < mp_napics; oapic++)
1211 if (IO_TO_ID(oapic) == newid)
1212 break;
1213
1214 if (oapic < mp_napics) {
1215 printf("Changing APIC ID for IO APIC #%d from "
1216 "%d to %d in MP table\n",
1217 oapic, newid, oldid);
1218 IO_TO_ID(oapic) = oldid;
1219 }
1220 IO_TO_ID(apic) = newid;
1221}
1222
1223
1224static void
1225fix_id_to_io_mapping(void)
1226{
1227 int x;
1228
1229 for (x = 0; x < NAPICID; x++)
1230 ID_TO_IO(x) = -1;
1231
1232 for (x = 0; x <= mp_naps; x++)
1233 if (CPU_TO_ID(x) < NAPICID)
1234 ID_TO_IO(CPU_TO_ID(x)) = x;
1235
1236 for (x = 0; x < mp_napics; x++)
1237 if (IO_TO_ID(x) < NAPICID)
1238 ID_TO_IO(IO_TO_ID(x)) = x;
1239}
1240
1241
1242static int
1243first_free_apic_id(void)
1244{
1245 int freeid, x;
1246
1247 for (freeid = 0; freeid < NAPICID; freeid++) {
1248 for (x = 0; x <= mp_naps; x++)
1249 if (CPU_TO_ID(x) == freeid)
1250 break;
1251 if (x <= mp_naps)
1252 continue;
1253 for (x = 0; x < mp_napics; x++)
1254 if (IO_TO_ID(x) == freeid)
1255 break;
1256 if (x < mp_napics)
1257 continue;
1258 return freeid;
1259 }
1260 return freeid;
1261}
1262
1263
1264static int
1265io_apic_id_acceptable(int apic, int id)
1266{
1267 int cpu; /* Logical CPU number */
1268 int oapic; /* Logical IO APIC number for other IO APIC */
1269
1270 if (id >= NAPICID)
1271 return 0; /* Out of range */
1272
1273 for (cpu = 0; cpu <= mp_naps; cpu++)
1274 if (CPU_TO_ID(cpu) == id)
1275 return 0; /* Conflict with CPU */
1276
1277 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1278 if (IO_TO_ID(oapic) == id)
1279 return 0; /* Conflict with other APIC */
1280
1281 return 1; /* ID is acceptable for IO APIC */
1282}
1283
1284
1285/*
1286 * parse an Intel MP specification table
1287 */
1288static void
1289fix_mp_table(void)
1290{
1291 int x;
1292 int id;
1293 int bus_0 = 0; /* Stop GCC warning */
1294 int bus_pci = 0; /* Stop GCC warning */
1295 int num_pci_bus;
1296 int apic; /* IO APIC unit number */
1297 int freeid; /* Free physical APIC ID */
1298 int physid; /* Current physical IO APIC ID */
1299
1300 /*
1301 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1302 * did it wrong. The MP spec says that when more than 1 PCI bus
1303 * exists the BIOS must begin with bus entries for the PCI bus and use
1304 * actual PCI bus numbering. This implies that when only 1 PCI bus
1305 * exists the BIOS can choose to ignore this ordering, and indeed many
1306 * MP motherboards do ignore it. This causes a problem when the PCI
1307 * sub-system makes requests of the MP sub-system based on PCI bus
1308 * numbers. So here we look for the situation and renumber the
1309 * busses and associated INTs in an effort to "make it right".
1310 */
1311
1312 /* find bus 0, PCI bus, count the number of PCI busses */
1313 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1314 if (bus_data[x].bus_id == 0) {
1315 bus_0 = x;
1316 }
1317 if (bus_data[x].bus_type == PCI) {
1318 ++num_pci_bus;
1319 bus_pci = x;
1320 }
1321 }
1322 /*
1323 * bus_0 == slot of bus with ID of 0
1324 * bus_pci == slot of last PCI bus encountered
1325 */
1326
1327 /* check the 1 PCI bus case for sanity */
1328 /* if it is number 0 all is well */
1329 if (num_pci_bus == 1 &&
1330 bus_data[bus_pci].bus_id != 0) {
1331
1332 /* mis-numbered, swap with whichever bus uses slot 0 */
1333
1334 /* swap the bus entry types */
1335 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1336 bus_data[bus_0].bus_type = PCI;
1337
1338 /* swap each relavant INTerrupt entry */
1339 id = bus_data[bus_pci].bus_id;
1340 for (x = 0; x < nintrs; ++x) {
1341 if (io_apic_ints[x].src_bus_id == id) {
1342 io_apic_ints[x].src_bus_id = 0;
1343 }
1344 else if (io_apic_ints[x].src_bus_id == 0) {
1345 io_apic_ints[x].src_bus_id = id;
1346 }
1347 }
1348 }
1349
1350 /* Assign IO APIC IDs.
1351 *
1352 * First try the existing ID. If a conflict is detected, try
1353 * the ID in the MP table. If a conflict is still detected, find
1354 * a free id.
1355 *
1356 * We cannot use the ID_TO_IO table before all conflicts has been
1357 * resolved and the table has been corrected.
1358 */
1359 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1360
1361 /* First try to use the value set by the BIOS */
1362 physid = io_apic_get_id(apic);
1363 if (io_apic_id_acceptable(apic, physid)) {
1364 if (IO_TO_ID(apic) != physid)
1365 swap_apic_id(apic, IO_TO_ID(apic), physid);
1366 continue;
1367 }
1368
1369 /* Then check if the value in the MP table is acceptable */
1370 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1371 continue;
1372
1373 /* Last resort, find a free APIC ID and use it */
1374 freeid = first_free_apic_id();
1375 if (freeid >= NAPICID)
1376 panic("No free physical APIC IDs found");
1377
1378 if (io_apic_id_acceptable(apic, freeid)) {
1379 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1380 continue;
1381 }
1382 panic("Free physical APIC ID not usable");
1383 }
1384 fix_id_to_io_mapping();
1385
1386 /* detect and fix broken Compaq MP table */
1387 if (apic_int_type(0, 0) == -1) {
1388 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1389 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1390 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1391 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1392 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1393 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1394 nintrs++;
1395 }
1396}
1397
1398
1399/* Assign low level interrupt handlers */
1400static void
1401setup_apic_irq_mapping(void)
1402{
1403 int x;
1404 int int_vector;
1405
1406 /* Clear array */
1407 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1408 int_to_apicintpin[x].ioapic = -1;
1409 int_to_apicintpin[x].int_pin = 0;
1410 int_to_apicintpin[x].apic_address = NULL;
1411 int_to_apicintpin[x].redirindex = 0;
1412 }
1413
1414 /* First assign ISA/EISA interrupts */
1415 for (x = 0; x < nintrs; x++) {
1416 int_vector = io_apic_ints[x].src_bus_irq;
1417 if (int_vector < APIC_INTMAPSIZE &&
1418 io_apic_ints[x].int_vector == 0xff &&
1419 int_to_apicintpin[int_vector].ioapic == -1 &&
1420 (apic_int_is_bus_type(x, ISA) ||
1421 apic_int_is_bus_type(x, EISA)) &&
1422 io_apic_ints[x].int_type == 0) {
1423 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1424 io_apic_ints[x].dst_apic_int,
1425 int_vector);
1426 }
1427 }
1428
1429 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1430 for (x = 0; x < nintrs; x++) {
1431 if (io_apic_ints[x].dst_apic_int == 0 &&
1432 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1433 io_apic_ints[x].int_vector == 0xff &&
1434 int_to_apicintpin[0].ioapic == -1 &&
1435 io_apic_ints[x].int_type == 3) {
1436 assign_apic_irq(0, 0, 0);
1437 break;
1438 }
1439 }
1440 /* PCI interrupt assignment is deferred */
1441}
1442
1443
1444static int
1445processor_entry(proc_entry_ptr entry, int cpu)
1446{
1447 /* check for usability */
1448 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1449 return 0;
1450
1451 if(entry->apic_id >= NAPICID)
1452 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1453 /* check for BSP flag */
1454 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1455 boot_cpu_id = entry->apic_id;
1456 CPU_TO_ID(0) = entry->apic_id;
1457 ID_TO_CPU(entry->apic_id) = 0;
1458 return 0; /* its already been counted */
1459 }
1460
1461 /* add another AP to list, if less than max number of CPUs */
1462 else if (cpu < MAXCPU) {
1463 CPU_TO_ID(cpu) = entry->apic_id;
1464 ID_TO_CPU(entry->apic_id) = cpu;
1465 return 1;
1466 }
1467
1468 return 0;
1469}
1470
1471
1472static int
1473bus_entry(bus_entry_ptr entry, int bus)
1474{
1475 int x;
1476 char c, name[8];
1477
1478 /* encode the name into an index */
1479 for (x = 0; x < 6; ++x) {
1480 if ((c = entry->bus_type[x]) == ' ')
1481 break;
1482 name[x] = c;
1483 }
1484 name[x] = '\0';
1485
1486 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1487 panic("unknown bus type: '%s'", name);
1488
1489 bus_data[bus].bus_id = entry->bus_id;
1490 bus_data[bus].bus_type = x;
1491
1492 return 1;
1493}
1494
1495
1496static int
1497io_apic_entry(io_apic_entry_ptr entry, int apic)
1498{
1499 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1500 return 0;
1501
1502 IO_TO_ID(apic) = entry->apic_id;
1503 if (entry->apic_id < NAPICID)
1504 ID_TO_IO(entry->apic_id) = apic;
1505
1506 return 1;
1507}
1508
1509
1510static int
1511lookup_bus_type(char *name)
1512{
1513 int x;
1514
1515 for (x = 0; x < MAX_BUSTYPE; ++x)
1516 if (strcmp(bus_type_table[x].name, name) == 0)
1517 return bus_type_table[x].type;
1518
1519 return UNKNOWN_BUSTYPE;
1520}
1521
1522
1523static int
1524int_entry(int_entry_ptr entry, int intr)
1525{
1526 int apic;
1527
1528 io_apic_ints[intr].int_type = entry->int_type;
1529 io_apic_ints[intr].int_flags = entry->int_flags;
1530 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1531 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1532 if (entry->dst_apic_id == 255) {
1533 /* This signal goes to all IO APICS. Select an IO APIC
1534 with sufficient number of interrupt pins */
1535 for (apic = 0; apic < mp_napics; apic++)
1536 if (((io_apic_read(apic, IOAPIC_VER) &
1537 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1538 entry->dst_apic_int)
1539 break;
1540 if (apic < mp_napics)
1541 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1542 else
1543 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1544 } else
1545 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1546 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1547
1548 return 1;
1549}
1550
1551
1552static int
1553apic_int_is_bus_type(int intr, int bus_type)
1554{
1555 int bus;
1556
1557 for (bus = 0; bus < mp_nbusses; ++bus)
1558 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1559 && ((int) bus_data[bus].bus_type == bus_type))
1560 return 1;
1561
1562 return 0;
1563}
1564
1565
1566/*
1567 * Given a traditional ISA INT mask, return an APIC mask.
1568 */
1569u_int
1570isa_apic_mask(u_int isa_mask)
1571{
1572 int isa_irq;
1573 int apic_pin;
1574
1575#if defined(SKIP_IRQ15_REDIRECT)
1576 if (isa_mask == (1 << 15)) {
1577 printf("skipping ISA IRQ15 redirect\n");
1578 return isa_mask;
1579 }
1580#endif /* SKIP_IRQ15_REDIRECT */
1581
1582 isa_irq = ffs(isa_mask); /* find its bit position */
1583 if (isa_irq == 0) /* doesn't exist */
1584 return 0;
1585 --isa_irq; /* make it zero based */
1586
1587 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1588 if (apic_pin == -1)
1589 return 0;
1590
1591 return (1 << apic_pin); /* convert pin# to a mask */
1592}
1593
1594
1595/*
1596 * Determine which APIC pin an ISA/EISA INT is attached to.
1597 */
1598#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1599#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1600#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1601#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1602
1603#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1604int
1605isa_apic_irq(int isa_irq)
1606{
1607 int intr;
1608
1609 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1610 if (INTTYPE(intr) == 0) { /* standard INT */
1611 if (SRCBUSIRQ(intr) == isa_irq) {
1612 if (apic_int_is_bus_type(intr, ISA) ||
1613 apic_int_is_bus_type(intr, EISA)) {
1614 if (INTIRQ(intr) == 0xff)
1615 return -1; /* unassigned */
1616 return INTIRQ(intr); /* found */
1617 }
1618 }
1619 }
1620 }
1621 return -1; /* NOT found */
1622}
1623
1624
1625/*
1626 * Determine which APIC pin a PCI INT is attached to.
1627 */
1628#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1629#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1630#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1631int
1632pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1633{
1634 int intr;
1635
1636 --pciInt; /* zero based */
1637
1638 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1639 if ((INTTYPE(intr) == 0) /* standard INT */
1640 && (SRCBUSID(intr) == pciBus)
1641 && (SRCBUSDEVICE(intr) == pciDevice)
1642 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1643 if (apic_int_is_bus_type(intr, PCI)) {
1644 if (INTIRQ(intr) == 0xff)
1645 allocate_apic_irq(intr);
1646 if (INTIRQ(intr) == 0xff)
1647 return -1; /* unassigned */
1648 return INTIRQ(intr); /* exact match */
1649 }
1650
1651 return -1; /* NOT found */
1652}
1653
1654int
1655next_apic_irq(int irq)
1656{
1657 int intr, ointr;
1658 int bus, bustype;
1659
1660 bus = 0;
1661 bustype = 0;
1662 for (intr = 0; intr < nintrs; intr++) {
1663 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1664 continue;
1665 bus = SRCBUSID(intr);
1666 bustype = apic_bus_type(bus);
1667 if (bustype != ISA &&
1668 bustype != EISA &&
1669 bustype != PCI)
1670 continue;
1671 break;
1672 }
1673 if (intr >= nintrs) {
1674 return -1;
1675 }
1676 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1677 if (INTTYPE(ointr) != 0)
1678 continue;
1679 if (bus != SRCBUSID(ointr))
1680 continue;
1681 if (bustype == PCI) {
1682 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1683 continue;
1684 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1685 continue;
1686 }
1687 if (bustype == ISA || bustype == EISA) {
1688 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1689 continue;
1690 }
1691 if (INTPIN(intr) == INTPIN(ointr))
1692 continue;
1693 break;
1694 }
1695 if (ointr >= nintrs) {
1696 return -1;
1697 }
1698 return INTIRQ(ointr);
1699}
1700#undef SRCBUSLINE
1701#undef SRCBUSDEVICE
1702#undef SRCBUSID
1703#undef SRCBUSIRQ
1704
1705#undef INTPIN
1706#undef INTIRQ
1707#undef INTAPIC
1708#undef INTTYPE
1709
1710
1711/*
1712 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1713 *
1714 * XXX FIXME:
1715 * Exactly what this means is unclear at this point. It is a solution
1716 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1717 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1718 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1719 * option.
1720 */
1721int
1722undirect_isa_irq(int rirq)
1723{
1724#if defined(READY)
1725 if (bootverbose)
1726 printf("Freeing redirected ISA irq %d.\n", rirq);
1727 /** FIXME: tickle the MB redirector chip */
1728 return -1;
1729#else
1730 if (bootverbose)
1731 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1732 return 0;
1733#endif /* READY */
1734}
1735
1736
1737/*
1738 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1739 */
1740int
1741undirect_pci_irq(int rirq)
1742{
1743#if defined(READY)
1744 if (bootverbose)
1745 printf("Freeing redirected PCI irq %d.\n", rirq);
1746
1747 /** FIXME: tickle the MB redirector chip */
1748 return -1;
1749#else
1750 if (bootverbose)
1751 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1752 rirq);
1753 return 0;
1754#endif /* READY */
1755}
1756
1757
1758/*
1759 * given a bus ID, return:
1760 * the bus type if found
1761 * -1 if NOT found
1762 */
1763int
1764apic_bus_type(int id)
1765{
1766 int x;
1767
1768 for (x = 0; x < mp_nbusses; ++x)
1769 if (bus_data[x].bus_id == id)
1770 return bus_data[x].bus_type;
1771
1772 return -1;
1773}
1774
1775
1776/*
1777 * given a LOGICAL APIC# and pin#, return:
1778 * the associated src bus ID if found
1779 * -1 if NOT found
1780 */
1781int
1782apic_src_bus_id(int apic, int pin)
1783{
1784 int x;
1785
1786 /* search each of the possible INTerrupt sources */
1787 for (x = 0; x < nintrs; ++x)
1788 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1789 (pin == io_apic_ints[x].dst_apic_int))
1790 return (io_apic_ints[x].src_bus_id);
1791
1792 return -1; /* NOT found */
1793}
1794
1795
1796/*
1797 * given a LOGICAL APIC# and pin#, return:
1798 * the associated src bus IRQ if found
1799 * -1 if NOT found
1800 */
1801int
1802apic_src_bus_irq(int apic, int pin)
1803{
1804 int x;
1805
1806 for (x = 0; x < nintrs; x++)
1807 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1808 (pin == io_apic_ints[x].dst_apic_int))
1809 return (io_apic_ints[x].src_bus_irq);
1810
1811 return -1; /* NOT found */
1812}
1813
1814
1815/*
1816 * given a LOGICAL APIC# and pin#, return:
1817 * the associated INTerrupt type if found
1818 * -1 if NOT found
1819 */
1820int
1821apic_int_type(int apic, int pin)
1822{
1823 int x;
1824
1825 /* search each of the possible INTerrupt sources */
1826 for (x = 0; x < nintrs; ++x)
1827 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1828 (pin == io_apic_ints[x].dst_apic_int))
1829 return (io_apic_ints[x].int_type);
1830
1831 return -1; /* NOT found */
1832}
1833
1834int
1835apic_irq(int apic, int pin)
1836{
1837 int x;
1838 int res;
1839
1840 for (x = 0; x < nintrs; ++x)
1841 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1842 (pin == io_apic_ints[x].dst_apic_int)) {
1843 res = io_apic_ints[x].int_vector;
1844 if (res == 0xff)
1845 return -1;
1846 if (apic != int_to_apicintpin[res].ioapic)
1847 panic("apic_irq: inconsistent table");
1848 if (pin != int_to_apicintpin[res].int_pin)
1849 panic("apic_irq inconsistent table (2)");
1850 return res;
1851 }
1852 return -1;
1853}
1854
1855
1856/*
1857 * given a LOGICAL APIC# and pin#, return:
1858 * the associated trigger mode if found
1859 * -1 if NOT found
1860 */
1861int
1862apic_trigger(int apic, int pin)
1863{
1864 int x;
1865
1866 /* search each of the possible INTerrupt sources */
1867 for (x = 0; x < nintrs; ++x)
1868 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1869 (pin == io_apic_ints[x].dst_apic_int))
1870 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1871
1872 return -1; /* NOT found */
1873}
1874
1875
1876/*
1877 * given a LOGICAL APIC# and pin#, return:
1878 * the associated 'active' level if found
1879 * -1 if NOT found
1880 */
1881int
1882apic_polarity(int apic, int pin)
1883{
1884 int x;
1885
1886 /* search each of the possible INTerrupt sources */
1887 for (x = 0; x < nintrs; ++x)
1888 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1889 (pin == io_apic_ints[x].dst_apic_int))
1890 return (io_apic_ints[x].int_flags & 0x03);
1891
1892 return -1; /* NOT found */
1893}
1894
1895
1896/*
1897 * set data according to MP defaults
1898 * FIXME: probably not complete yet...
1899 */
1900static void
1901default_mp_table(int type)
1902{
1903 int ap_cpu_id;
1904#if defined(APIC_IO)
1905 int io_apic_id;
1906 int pin;
1907#endif /* APIC_IO */
1908
1909#if 0
1910 printf(" MP default config type: %d\n", type);
1911 switch (type) {
1912 case 1:
1913 printf(" bus: ISA, APIC: 82489DX\n");
1914 break;
1915 case 2:
1916 printf(" bus: EISA, APIC: 82489DX\n");
1917 break;
1918 case 3:
1919 printf(" bus: EISA, APIC: 82489DX\n");
1920 break;
1921 case 4:
1922 printf(" bus: MCA, APIC: 82489DX\n");
1923 break;
1924 case 5:
1925 printf(" bus: ISA+PCI, APIC: Integrated\n");
1926 break;
1927 case 6:
1928 printf(" bus: EISA+PCI, APIC: Integrated\n");
1929 break;
1930 case 7:
1931 printf(" bus: MCA+PCI, APIC: Integrated\n");
1932 break;
1933 default:
1934 printf(" future type\n");
1935 break;
1936 /* NOTREACHED */
1937 }
1938#endif /* 0 */
1939
1940 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1941 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1942
1943 /* BSP */
1944 CPU_TO_ID(0) = boot_cpu_id;
1945 ID_TO_CPU(boot_cpu_id) = 0;
1946
1947 /* one and only AP */
1948 CPU_TO_ID(1) = ap_cpu_id;
1949 ID_TO_CPU(ap_cpu_id) = 1;
1950
1951#if defined(APIC_IO)
1952 /* one and only IO APIC */
1953 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1954
1955 /*
1956 * sanity check, refer to MP spec section 3.6.6, last paragraph
1957 * necessary as some hardware isn't properly setting up the IO APIC
1958 */
1959#if defined(REALLY_ANAL_IOAPICID_VALUE)
1960 if (io_apic_id != 2) {
1961#else
1962 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1963#endif /* REALLY_ANAL_IOAPICID_VALUE */
1964 io_apic_set_id(0, 2);
1965 io_apic_id = 2;
1966 }
1967 IO_TO_ID(0) = io_apic_id;
1968 ID_TO_IO(io_apic_id) = 0;
1969#endif /* APIC_IO */
1970
1971 /* fill out bus entries */
1972 switch (type) {
1973 case 1:
1974 case 2:
1975 case 3:
1976 case 4:
1977 case 5:
1978 case 6:
1979 case 7:
1980 bus_data[0].bus_id = default_data[type - 1][1];
1981 bus_data[0].bus_type = default_data[type - 1][2];
1982 bus_data[1].bus_id = default_data[type - 1][3];
1983 bus_data[1].bus_type = default_data[type - 1][4];
1984 break;
1985
1986 /* case 4: case 7: MCA NOT supported */
1987 default: /* illegal/reserved */
1988 panic("BAD default MP config: %d", type);
1989 /* NOTREACHED */
1990 }
1991
1992#if defined(APIC_IO)
1993 /* general cases from MP v1.4, table 5-2 */
1994 for (pin = 0; pin < 16; ++pin) {
1995 io_apic_ints[pin].int_type = 0;
1996 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1997 io_apic_ints[pin].src_bus_id = 0;
1998 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1999 io_apic_ints[pin].dst_apic_id = io_apic_id;
2000 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2001 }
2002
2003 /* special cases from MP v1.4, table 5-2 */
2004 if (type == 2) {
2005 io_apic_ints[2].int_type = 0xff; /* N/C */
2006 io_apic_ints[13].int_type = 0xff; /* N/C */
2007#if !defined(APIC_MIXED_MODE)
2008 /** FIXME: ??? */
2009 panic("sorry, can't support type 2 default yet");
2010#endif /* APIC_MIXED_MODE */
2011 }
2012 else
2013 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2014
2015 if (type == 7)
2016 io_apic_ints[0].int_type = 0xff; /* N/C */
2017 else
2018 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2019#endif /* APIC_IO */
2020}
2021
2022
2023/*
2024 * start each AP in our list
2025 */
2026static int
2027start_all_aps(u_int boot_addr)
2028{
2029 int x, i, pg;
2030#ifndef PC98
2031 u_char mpbiosreason;
2032#endif
2033 u_long mpbioswarmvec;
2034 struct pcpu *pc;
2035 char *stack;
2036 uintptr_t kptbase;
2037
2038 POSTCODE(START_ALL_APS_POST);
2039
2040 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
2041
2042 /* initialize BSP's local APIC */
2043 apic_initialize();
2044 bsp_apic_ready = 1;
2045
2046 /* install the AP 1st level boot code */
2047 install_ap_tramp(boot_addr);
2048
2049
2050 /* save the current value of the warm-start vector */
2051 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2052#ifndef PC98
2053 outb(CMOS_REG, BIOS_RESET);
2054 mpbiosreason = inb(CMOS_DATA);
2055#endif
2056
2057 /* set up temporary P==V mapping for AP boot */
2058 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2059 kptbase = (uintptr_t)(void *)KPTphys;
2060 for (x = 0; x < NKPT; x++)
2061 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2062 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2063 invltlb();
2064
2065 /* start each AP */
2066 for (x = 1; x <= mp_naps; ++x) {
2067
2068 /* This is a bit verbose, it will go away soon. */
2069
2070 /* first page of AP's private space */
2071 pg = x * i386_btop(sizeof(struct privatespace));
2072
2073 /* allocate a new private data page */
2074 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE);
2075
2076 /* wire it into the private page table page */
2077 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc));
2078
2079 /* allocate and set up an idle stack data page */
2080 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */
2081 for (i = 0; i < KSTACK_PAGES; i++)
2082 SMPpt[pg + 1 + i] = (pt_entry_t)
2083 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2084
2085 /* prime data page for it to use */
2086 pcpu_init(pc, x, sizeof(struct pcpu));
2087
2088 /* setup a vector to our boot code */
2089 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2090 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2091#ifndef PC98
2092 outb(CMOS_REG, BIOS_RESET);
2093 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2094#endif
2095
2096 bootSTK = &SMP_prvspace[x].idlekstack[KSTACK_PAGES * PAGE_SIZE];
2097 bootAP = x;
2098
2099 /* attempt to start the Application Processor */
2100 CHECK_INIT(99); /* setup checkpoints */
2101 if (!start_ap(x, boot_addr)) {
2102 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2103 CHECK_PRINT("trace"); /* show checkpoints */
2104 /* better panic as the AP may be running loose */
2105 printf("panic y/n? [y] ");
2106 if (cngetc() != 'n')
2107 panic("bye-bye");
2108 }
2109 CHECK_PRINT("trace"); /* show checkpoints */
2110
2111 /* record its version info */
2112 cpu_apic_versions[x] = cpu_apic_versions[0];
2113
2114 all_cpus |= (1 << x); /* record AP in CPU map */
2115 }
2116
2117 /* build our map of 'other' CPUs */
2118 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
2119
2120 /* fill in our (BSP) APIC version */
2121 cpu_apic_versions[0] = lapic.version;
2122
2123 /* restore the warmstart vector */
2124 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2125#ifndef PC98
2126 outb(CMOS_REG, BIOS_RESET);
2127 outb(CMOS_DATA, mpbiosreason);
2128#endif
2129
2130 /*
2131 * Set up the idle context for the BSP. Similar to above except
2132 * that some was done by locore, some by pmap.c and some is implicit
2133 * because the BSP is cpu#0 and the page is initially zero, and also
2134 * because we can refer to variables by name on the BSP..
2135 */
2136
2137 /* Allocate and setup BSP idle stack */
2138 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
2139 for (i = 0; i < KSTACK_PAGES; i++)
2140 SMPpt[1 + i] = (pt_entry_t)
2141 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2142
2143 for (x = 0; x < NKPT; x++)
2144 PTD[x] = 0;
2145 pmap_set_opt();
2146
2147 /* number of APs actually started */
2148 return mp_ncpus - 1;
2149}
2150
2151
2152/*
2153 * load the 1st level AP boot code into base memory.
2154 */
2155
2156/* targets for relocation */
2157extern void bigJump(void);
2158extern void bootCodeSeg(void);
2159extern void bootDataSeg(void);
2160extern void MPentry(void);
2161extern u_int MP_GDT;
2162extern u_int mp_gdtbase;
2163
2164static void
2165install_ap_tramp(u_int boot_addr)
2166{
2167 int x;
2168 int size = *(int *) ((u_long) & bootMP_size);
2169 u_char *src = (u_char *) ((u_long) bootMP);
2170 u_char *dst = (u_char *) boot_addr + KERNBASE;
2171 u_int boot_base = (u_int) bootMP;
2172 u_int8_t *dst8;
2173 u_int16_t *dst16;
2174 u_int32_t *dst32;
2175
2176 POSTCODE(INSTALL_AP_TRAMP_POST);
2177
2178 for (x = 0; x < size; ++x)
2179 *dst++ = *src++;
2180
2181 /*
2182 * modify addresses in code we just moved to basemem. unfortunately we
2183 * need fairly detailed info about mpboot.s for this to work. changes
2184 * to mpboot.s might require changes here.
2185 */
2186
2187 /* boot code is located in KERNEL space */
2188 dst = (u_char *) boot_addr + KERNBASE;
2189
2190 /* modify the lgdt arg */
2191 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2192 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2193
2194 /* modify the ljmp target for MPentry() */
2195 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2196 *dst32 = ((u_int) MPentry - KERNBASE);
2197
2198 /* modify the target for boot code segment */
2199 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2200 dst8 = (u_int8_t *) (dst16 + 1);
2201 *dst16 = (u_int) boot_addr & 0xffff;
2202 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2203
2204 /* modify the target for boot data segment */
2205 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2206 dst8 = (u_int8_t *) (dst16 + 1);
2207 *dst16 = (u_int) boot_addr & 0xffff;
2208 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2209}
2210
2211
2212/*
2213 * this function starts the AP (application processor) identified
2214 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2215 * to accomplish this. This is necessary because of the nuances
2216 * of the different hardware we might encounter. It ain't pretty,
2217 * but it seems to work.
2218 */
2219static int
2220start_ap(int logical_cpu, u_int boot_addr)
2221{
2222 int physical_cpu;
2223 int vector;
2224 int cpus;
2225 u_long icr_lo, icr_hi;
2226
2227 POSTCODE(START_AP_POST);
2228
2229 /* get the PHYSICAL APIC ID# */
2230 physical_cpu = CPU_TO_ID(logical_cpu);
2231
2232 /* calculate the vector */
2233 vector = (boot_addr >> 12) & 0xff;
2234
2235 /* used as a watchpoint to signal AP startup */
2236 cpus = mp_ncpus;
2237
2238 /*
2239 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2240 * and running the target CPU. OR this INIT IPI might be latched (P5
2241 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2242 * ignored.
2243 */
2244
2245 /* setup the address for the target AP */
2246 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2247 icr_hi |= (physical_cpu << 24);
2248 lapic.icr_hi = icr_hi;
2249
2250 /* do an INIT IPI: assert RESET */
2251 icr_lo = lapic.icr_lo & 0xfff00000;
2252 lapic.icr_lo = icr_lo | 0x0000c500;
2253
2254 /* wait for pending status end */
2255 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2256 /* spin */ ;
2257
2258 /* do an INIT IPI: deassert RESET */
2259 lapic.icr_lo = icr_lo | 0x00008500;
2260
2261 /* wait for pending status end */
2262 u_sleep(10000); /* wait ~10mS */
2263 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2264 /* spin */ ;
2265
2266 /*
2267 * next we do a STARTUP IPI: the previous INIT IPI might still be
2268 * latched, (P5 bug) this 1st STARTUP would then terminate
2269 * immediately, and the previously started INIT IPI would continue. OR
2270 * the previous INIT IPI has already run. and this STARTUP IPI will
2271 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2272 * will run.
2273 */
2274
2275 /* do a STARTUP IPI */
2276 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2277 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2278 /* spin */ ;
2279 u_sleep(200); /* wait ~200uS */
2280
2281 /*
2282 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2283 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2284 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2285 * recognized after hardware RESET or INIT IPI.
2286 */
2287
2288 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2289 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2290 /* spin */ ;
2291 u_sleep(200); /* wait ~200uS */
2292
2293 /* wait for it to start */
2294 set_apic_timer(5000000);/* == 5 seconds */
2295 while (read_apic_timer())
2296 if (mp_ncpus > cpus)
2297 return 1; /* return SUCCESS */
2298
2299 return 0; /* return FAILURE */
2300}
2301
2302#if defined(APIC_IO)
2303
2304#ifdef COUNT_XINVLTLB_HITS
2305u_int xhits_gbl[MAXCPU];
2306u_int xhits_pg[MAXCPU];
2307u_int xhits_rng[MAXCPU];
2308SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
2309SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
2310 sizeof(xhits_gbl), "IU", "");
2311SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
2312 sizeof(xhits_pg), "IU", "");
2313SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
2314 sizeof(xhits_rng), "IU", "");
2315
2316u_int ipi_global;
2317u_int ipi_page;
2318u_int ipi_range;
2319u_int ipi_range_size;
2320SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
2321SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
2322SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
2323SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
2324 0, "");
2325
2326u_int ipi_masked_global;
2327u_int ipi_masked_page;
2328u_int ipi_masked_range;
2329u_int ipi_masked_range_size;
2330SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
2331 &ipi_masked_global, 0, "");
2332SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
2333 &ipi_masked_page, 0, "");
2334SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
2335 &ipi_masked_range, 0, "");
2336SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
2337 &ipi_masked_range_size, 0, "");
2338#endif
2339
2340/*
2341 * Flush the TLB on all other CPU's
2342 */
2343static void
2344smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
2345{
2346 u_int ncpu;
2347 register_t eflags;
2348
2349 ncpu = mp_ncpus - 1; /* does not shootdown self */
2350 if (ncpu < 1)
2351 return; /* no other cpus */
2352 eflags = read_eflags();
2353 if ((eflags & PSL_I) == 0)
2354 panic("absolutely cannot call smp_ipi_shootdown with interrupts already disabled");
2355 mtx_lock_spin(&smp_tlb_mtx);
2356 smp_tlb_addr1 = addr1;
2357 smp_tlb_addr2 = addr2;
2358 atomic_store_rel_int(&smp_tlb_wait, 0);
2359 ipi_all_but_self(vector);
2360 while (smp_tlb_wait < ncpu)
2361 ia32_pause();
2362 mtx_unlock_spin(&smp_tlb_mtx);
2363}
2364
2365/*
2366 * This is about as magic as it gets. fortune(1) has got similar code
2367 * for reversing bits in a word. Who thinks up this stuff??
2368 *
2369 * Yes, it does appear to be consistently faster than:
2370 * while (i = ffs(m)) {
2371 * m >>= i;
2372 * bits++;
2373 * }
2374 * and
2375 * while (lsb = (m & -m)) { // This is magic too
2376 * m &= ~lsb; // or: m ^= lsb
2377 * bits++;
2378 * }
2379 * Both of these latter forms do some very strange things on gcc-3.1 with
2380 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2.
2381 * There is probably an SSE or MMX popcnt instruction.
2382 *
2383 * I wonder if this should be in libkern?
2384 *
2385 * XXX Stop the presses! Another one:
2386 * static __inline u_int32_t
2387 * popcnt1(u_int32_t v)
2388 * {
2389 * v -= ((v >> 1) & 0x55555555);
2390 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
2391 * v = (v + (v >> 4)) & 0x0F0F0F0F;
2392 * return (v * 0x01010101) >> 24;
2393 * }
2394 * The downside is that it has a multiply. With a pentium3 with
2395 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use
2396 * an imull, and in that case it is faster. In most other cases
2397 * it appears slightly slower.
2398 */
2399static __inline u_int32_t
2400popcnt(u_int32_t m)
2401{
2402
2403 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1);
2404 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2);
2405 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4);
2406 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8);
2407 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16);
2408 return m;
2409}
2410
2411static void
2412smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
2413{
2414 int ncpu, othercpus;
2415 register_t eflags;
2416
2417 othercpus = mp_ncpus - 1;
2418 if (mask == (u_int)-1) {
2419 ncpu = othercpus;
2420 if (ncpu < 1)
2421 return;
2422 } else {
2423 /* XXX there should be a pcpu self mask */
2424 mask &= ~(1 << PCPU_GET(cpuid));
2425 if (mask == 0)
2426 return;
2427 ncpu = popcnt(mask);
2428 if (ncpu > othercpus) {
2429 /* XXX this should be a panic offence */
2430 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
2431 ncpu, othercpus);
2432 ncpu = othercpus;
2433 }
2434 /* XXX should be a panic, implied by mask == 0 above */
2435 if (ncpu < 1)
2436 return;
2437 }
2438 eflags = read_eflags();
2439 if ((eflags & PSL_I) == 0)
2440 panic("absolutely cannot call smp_targeted_ipi_shootdown with interrupts already disabled");
2441 mtx_lock_spin(&smp_tlb_mtx);
2442 smp_tlb_addr1 = addr1;
2443 smp_tlb_addr2 = addr2;
2444 atomic_store_rel_int(&smp_tlb_wait, 0);
2445 if (mask == (u_int)-1)
2446 ipi_all_but_self(vector);
2447 else
2448 ipi_selected(mask, vector);
2449 while (smp_tlb_wait < ncpu)
2450 ia32_pause();
2451 mtx_unlock_spin(&smp_tlb_mtx);
2452}
2453#endif
2454
2455void
2456smp_invltlb(void)
2457{
2458#if defined(APIC_IO)
2459 if (smp_started) {
2460 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
2461#ifdef COUNT_XINVLTLB_HITS
2462 ipi_global++;
2463#endif
2464 }
2465#endif /* APIC_IO */
2466}
2467
2468void
2469smp_invlpg(vm_offset_t addr)
2470{
2471#if defined(APIC_IO)
2472 if (smp_started) {
2473 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
2474#ifdef COUNT_XINVLTLB_HITS
2475 ipi_page++;
2476#endif
2477 }
2478#endif /* APIC_IO */
2479}
2480
2481void
2482smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
2483{
2484#if defined(APIC_IO)
2485 if (smp_started) {
2486 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
2487#ifdef COUNT_XINVLTLB_HITS
2488 ipi_range++;
2489 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
2490#endif
2491 }
2492#endif /* APIC_IO */
2493}
2494
2495void
2496smp_masked_invltlb(u_int mask)
2497{
2498#if defined(APIC_IO)
2499 if (smp_started) {
2500 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
2501#ifdef COUNT_XINVLTLB_HITS
2502 ipi_masked_global++;
2503#endif
2504 }
2505#endif /* APIC_IO */
2506}
2507
2508void
2509smp_masked_invlpg(u_int mask, vm_offset_t addr)
2510{
2511#if defined(APIC_IO)
2512 if (smp_started) {
2513 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
2514#ifdef COUNT_XINVLTLB_HITS
2515 ipi_masked_page++;
2516#endif
2517 }
2518#endif /* APIC_IO */
2519}
2520
2521void
2522smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
2523{
2524#if defined(APIC_IO)
2525 if (smp_started) {
2526 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
2527#ifdef COUNT_XINVLTLB_HITS
2528 ipi_masked_range++;
2529 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
2530#endif
2531 }
2532#endif /* APIC_IO */
2533}
2534
2535
2536/*
2537 * This is called once the rest of the system is up and running and we're
2538 * ready to let the AP's out of the pen.
2539 */
2540void
2541ap_init(void)
2542{
2543 u_int apic_id;
2544
2545 /* spin until all the AP's are ready */
2546 while (!aps_ready)
2547 ia32_pause();
2548
2549 /* BSP may have changed PTD while we were waiting */
2550 invltlb();
2551
2552#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2553 lidt(&r_idt);
2554#endif
2555
2556 /* set up CPU registers and state */
2557 cpu_setregs();
2558
2559 /* set up FPU state on the AP */
2560 npxinit(__INITIAL_NPXCW__);
2561
2562 /* set up SSE registers */
2563 enable_sse();
2564
2565 /* A quick check from sanity claus */
2566 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2567 if (PCPU_GET(cpuid) != apic_id) {
2568 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
2569 printf("SMP: apic_id = %d\n", apic_id);
2570 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]);
2571 panic("cpuid mismatch! boom!!");
2572 }
2573
2574 /* Init local apic for irq's */
2575 apic_initialize();
2576
2577 /* Set memory range attributes for this CPU to match the BSP */
2578 mem_range_AP_init();
2579
2580 mtx_lock_spin(&ap_boot_mtx);
2581
2582 smp_cpus++;
2583
2584 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
2585 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
2586
2587 /* Build our map of 'other' CPUs. */
2588 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
2589
2590 if (bootverbose)
2591 apic_dump("ap_init()");
2592
2593 if (smp_cpus == mp_ncpus) {
2594 /* enable IPI's, tlb shootdown, freezes etc */
2595 atomic_store_rel_int(&smp_started, 1);
2596 smp_active = 1; /* historic */
2597 }
2598
2599 mtx_unlock_spin(&ap_boot_mtx);
2600
2601 /* wait until all the AP's are up */
2602 while (smp_started == 0)
2603 ia32_pause();
2604
2605 /* ok, now grab sched_lock and enter the scheduler */
2606 mtx_lock_spin(&sched_lock);
2607
2608 binuptime(PCPU_PTR(switchtime));
2609 PCPU_SET(switchticks, ticks);
2610
2611 cpu_throw(NULL, choosethread()); /* doesn't return */
2612
2613 panic("scheduler returned us to %s", __func__);
2614}
2615
2616/*
2617 * For statclock, we send an IPI to all CPU's to have them call this
2618 * function.
2619 *
2620 * WARNING! unpend() will call statclock() directly and skip this
2621 * routine.
2622 */
2623void
2624forwarded_statclock(struct clockframe frame)
2625{
2626
2627 if (profprocs != 0)
2628 profclock(&frame);
2629 if (pscnt == psdiv)
2630 statclock(&frame);
2631}
2632
2633void
2634forward_statclock(void)
2635{
2636 int map;
2637
2638 CTR0(KTR_SMP, "forward_statclock");
2639
2640 if (!smp_started || cold || panicstr)
2641 return;
2642
2643 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2644 if (map != 0)
2645 ipi_selected(map, IPI_STATCLOCK);
2646}
2647
2648/*
2649 * For each hardclock(), we send an IPI to all other CPU's to have them
2650 * execute this function. It would be nice to reduce contention on
2651 * sched_lock if we could simply peek at the CPU to determine the user/kernel
2652 * state and call hardclock_process() on the CPU receiving the clock interrupt
2653 * and then just use a simple IPI to handle any ast's if needed.
2654 *
2655 * WARNING! unpend() will call hardclock_process() directly and skip this
2656 * routine.
2657 */
2658void
2659forwarded_hardclock(struct clockframe frame)
2660{
2661
2662 hardclock_process(&frame);
2663}
2664
2665void
2666forward_hardclock(void)
2667{
2668 u_int map;
2669
2670 CTR0(KTR_SMP, "forward_hardclock");
2671
2672 if (!smp_started || cold || panicstr)
2673 return;
2674
2675 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2676 if (map != 0)
2677 ipi_selected(map, IPI_HARDCLOCK);
2678}
2679
2680#ifdef APIC_INTR_REORDER
2681/*
2682 * Maintain mapping from softintr vector to isr bit in local apic.
2683 */
2684void
2685set_lapic_isrloc(int intr, int vector)
2686{
2687 if (intr < 0 || intr > 32)
2688 panic("set_apic_isrloc: bad intr argument: %d",intr);
2689 if (vector < ICU_OFFSET || vector > 255)
2690 panic("set_apic_isrloc: bad vector argument: %d",vector);
2691 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2692 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2693}
2694#endif
2695
2696/*
2697 * send an IPI to a set of cpus.
2698 */
2699void
2700ipi_selected(u_int32_t cpus, u_int ipi)
2701{
2702
2703 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
2704 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED);
2705}
2706
2707/*
2708 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
2709 */
2710void
2711ipi_all(u_int ipi)
2712{
2713
2714 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
2715 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED);
2716}
2717
2718/*
2719 * send an IPI to all CPUs EXCEPT myself
2720 */
2721void
2722ipi_all_but_self(u_int ipi)
2723{
2724
2725 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
2726 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED);
2727}
2728
2729/*
2730 * send an IPI to myself
2731 */
2732void
2733ipi_self(u_int ipi)
2734{
2735
2736 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
2737 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED);
2738}
2739
2740static void
2741release_aps(void *dummy __unused)
2742{
2743
2744 if (mp_ncpus == 1)
2745 return;
2746 mtx_lock_spin(&sched_lock);
2747 atomic_store_rel_int(&aps_ready, 1);
2748 while (smp_started == 0)
2749 ia32_pause();
2750 mtx_unlock_spin(&sched_lock);
2751}
2752
2753SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
2754
2755static int hlt_cpus_mask;
2756static int hlt_logical_cpus = 1;
2757static struct sysctl_ctx_list logical_cpu_clist;
2758
2759static int
2760sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
2761{
2762 u_int mask;
2763 int error;
2764
2765 mask = hlt_cpus_mask;
2766 error = sysctl_handle_int(oidp, &mask, 0, req);
2767 if (error || !req->newptr)
2768 return (error);
2769
2770 if (logical_cpus_mask != 0 &&
2771 (mask & logical_cpus_mask) == logical_cpus_mask)
2772 hlt_logical_cpus = 1;
2773 else
2774 hlt_logical_cpus = 0;
2775
2776 if ((mask & all_cpus) == all_cpus)
2777 mask &= ~(1<<0);
2778 hlt_cpus_mask = mask;
2779 return (error);
2780}
2781SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
2782 0, 0, sysctl_hlt_cpus, "IU", "");
2783
2784static int
2785sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
2786{
2787 int disable, error;
2788
2789 disable = hlt_logical_cpus;
2790 error = sysctl_handle_int(oidp, &disable, 0, req);
2791 if (error || !req->newptr)
2792 return (error);
2793
2794 if (disable)
2795 hlt_cpus_mask |= logical_cpus_mask;
2796 else
2797 hlt_cpus_mask &= ~logical_cpus_mask;
2798
2799 if ((hlt_cpus_mask & all_cpus) == all_cpus)
2800 hlt_cpus_mask &= ~(1<<0);
2801
2802 hlt_logical_cpus = disable;
2803 return (error);
2804}
2805
2806static void
2807cpu_hlt_setup(void *dummy __unused)
2808{
2809
2810 if (logical_cpus_mask != 0) {
2811 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
2812 &hlt_logical_cpus);
2813 sysctl_ctx_init(&logical_cpu_clist);
2814 SYSCTL_ADD_PROC(&logical_cpu_clist,
2815 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
2816 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
2817 sysctl_hlt_logical_cpus, "IU", "");
2818 SYSCTL_ADD_UINT(&logical_cpu_clist,
2819 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
2820 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
2821 &logical_cpus_mask, 0, "");
2822
2823 if (hlt_logical_cpus)
2824 hlt_cpus_mask |= logical_cpus_mask;
2825 }
2826}
2827SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
2828
2829int
2830mp_grab_cpu_hlt(void)
2831{
2832 u_int mask = PCPU_GET(cpumask);
2833 int retval;
2834
2835 retval = mask & hlt_cpus_mask;
2836 while (mask & hlt_cpus_mask)
2837 __asm __volatile("sti; hlt" : : : "memory");
2838 return (retval);
2839}
| 30#include "opt_cpu.h"
31#include "opt_kstack_pages.h"
32#include "opt_swtch.h"
33
34#ifdef SMP
35#include <machine/smptests.h>
36#else
37#error
38#endif
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/bus.h>
43#include <sys/cons.h> /* cngetc() */
44#ifdef GPROF
45#include <sys/gmon.h>
46#endif
47#include <sys/kernel.h>
48#include <sys/ktr.h>
49#include <sys/lock.h>
50#include <sys/malloc.h>
51#include <sys/memrange.h>
52#include <sys/mutex.h>
53#include <sys/pcpu.h>
54#include <sys/proc.h>
55#include <sys/smp.h>
56#include <sys/sysctl.h>
57#include <sys/user.h>
58
59#include <vm/vm.h>
60#include <vm/vm_param.h>
61#include <vm/pmap.h>
62#include <vm/vm_kern.h>
63#include <vm/vm_extern.h>
64#include <vm/vm_map.h>
65
66#include <machine/apic.h>
67#include <machine/atomic.h>
68#include <machine/clock.h>
69#include <machine/cpu.h>
70#include <machine/cpufunc.h>
71#include <machine/mpapic.h>
72#include <machine/psl.h>
73#include <machine/segments.h>
74#include <machine/smp.h>
75#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
76#include <machine/tss.h>
77#include <machine/specialreg.h>
78#include <machine/privatespace.h>
79
80#if defined(APIC_IO)
81#include <machine/md_var.h> /* setidt() */
82#include <i386/isa/icu.h> /* IPIs */
83#include <i386/isa/intr_machdep.h> /* IPIs */
84#endif /* APIC_IO */
85
86#if defined(TEST_DEFAULT_CONFIG)
87#define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
88#else
89#define MPFPS_MPFB1 mpfps->mpfb1
90#endif /* TEST_DEFAULT_CONFIG */
91
92#define WARMBOOT_TARGET 0
93#define WARMBOOT_OFF (KERNBASE + 0x0467)
94#define WARMBOOT_SEG (KERNBASE + 0x0469)
95
96#ifdef PC98
97#define BIOS_BASE (0xe8000)
98#define BIOS_SIZE (0x18000)
99#else
100#define BIOS_BASE (0xf0000)
101#define BIOS_SIZE (0x10000)
102#endif
103#define BIOS_COUNT (BIOS_SIZE/4)
104
105#define CMOS_REG (0x70)
106#define CMOS_DATA (0x71)
107#define BIOS_RESET (0x0f)
108#define BIOS_WARM (0x0a)
109
110#define PROCENTRY_FLAG_EN 0x01
111#define PROCENTRY_FLAG_BP 0x02
112#define IOAPICENTRY_FLAG_EN 0x01
113
114
115/* MP Floating Pointer Structure */
116typedef struct MPFPS {
117 char signature[4];
118 void *pap;
119 u_char length;
120 u_char spec_rev;
121 u_char checksum;
122 u_char mpfb1;
123 u_char mpfb2;
124 u_char mpfb3;
125 u_char mpfb4;
126 u_char mpfb5;
127} *mpfps_t;
128
129/* MP Configuration Table Header */
130typedef struct MPCTH {
131 char signature[4];
132 u_short base_table_length;
133 u_char spec_rev;
134 u_char checksum;
135 u_char oem_id[8];
136 u_char product_id[12];
137 void *oem_table_pointer;
138 u_short oem_table_size;
139 u_short entry_count;
140 void *apic_address;
141 u_short extended_table_length;
142 u_char extended_table_checksum;
143 u_char reserved;
144} *mpcth_t;
145
146
147typedef struct PROCENTRY {
148 u_char type;
149 u_char apic_id;
150 u_char apic_version;
151 u_char cpu_flags;
152 u_long cpu_signature;
153 u_long feature_flags;
154 u_long reserved1;
155 u_long reserved2;
156} *proc_entry_ptr;
157
158typedef struct BUSENTRY {
159 u_char type;
160 u_char bus_id;
161 char bus_type[6];
162} *bus_entry_ptr;
163
164typedef struct IOAPICENTRY {
165 u_char type;
166 u_char apic_id;
167 u_char apic_version;
168 u_char apic_flags;
169 void *apic_address;
170} *io_apic_entry_ptr;
171
172typedef struct INTENTRY {
173 u_char type;
174 u_char int_type;
175 u_short int_flags;
176 u_char src_bus_id;
177 u_char src_bus_irq;
178 u_char dst_apic_id;
179 u_char dst_apic_int;
180} *int_entry_ptr;
181
182/* descriptions of MP basetable entries */
183typedef struct BASETABLE_ENTRY {
184 u_char type;
185 u_char length;
186 char name[16];
187} basetable_entry;
188
189/*
190 * this code MUST be enabled here and in mpboot.s.
191 * it follows the very early stages of AP boot by placing values in CMOS ram.
192 * it NORMALLY will never be needed and thus the primitive method for enabling.
193 *
194#define CHECK_POINTS
195 */
196
197#if defined(CHECK_POINTS) && !defined(PC98)
198#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
199#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
200
201#define CHECK_INIT(D); \
202 CHECK_WRITE(0x34, (D)); \
203 CHECK_WRITE(0x35, (D)); \
204 CHECK_WRITE(0x36, (D)); \
205 CHECK_WRITE(0x37, (D)); \
206 CHECK_WRITE(0x38, (D)); \
207 CHECK_WRITE(0x39, (D));
208
209#define CHECK_PRINT(S); \
210 printf("%s: %d, %d, %d, %d, %d, %d\n", \
211 (S), \
212 CHECK_READ(0x34), \
213 CHECK_READ(0x35), \
214 CHECK_READ(0x36), \
215 CHECK_READ(0x37), \
216 CHECK_READ(0x38), \
217 CHECK_READ(0x39));
218
219#else /* CHECK_POINTS */
220
221#define CHECK_INIT(D)
222#define CHECK_PRINT(S)
223
224#endif /* CHECK_POINTS */
225
226/*
227 * Values to send to the POST hardware.
228 */
229#define MP_BOOTADDRESS_POST 0x10
230#define MP_PROBE_POST 0x11
231#define MPTABLE_PASS1_POST 0x12
232
233#define MP_START_POST 0x13
234#define MP_ENABLE_POST 0x14
235#define MPTABLE_PASS2_POST 0x15
236
237#define START_ALL_APS_POST 0x16
238#define INSTALL_AP_TRAMP_POST 0x17
239#define START_AP_POST 0x18
240
241#define MP_ANNOUNCE_POST 0x19
242
243static int need_hyperthreading_fixup;
244static u_int logical_cpus;
245static u_int logical_cpus_mask;
246
247/* used to hold the AP's until we are ready to release them */
248static struct mtx ap_boot_mtx;
249
250/** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
251int current_postcode;
252
253/** XXX FIXME: what system files declare these??? */
254extern struct region_descriptor r_gdt, r_idt;
255
256int bsp_apic_ready = 0; /* flags useability of BSP apic */
257int mp_naps; /* # of Applications processors */
258int mp_nbusses; /* # of busses */
259int mp_napics; /* # of IO APICs */
260int boot_cpu_id; /* designated BSP */
261vm_offset_t cpu_apic_address;
262vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
263extern int nkpt;
264
265u_int32_t cpu_apic_versions[MAXCPU];
266u_int32_t *io_apic_versions;
267
268#ifdef APIC_INTR_REORDER
269struct {
270 volatile int *location;
271 int bit;
272} apic_isrbit_location[32];
273#endif
274
275struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
276
277/*
278 * APIC ID logical/physical mapping structures.
279 * We oversize these to simplify boot-time config.
280 */
281int cpu_num_to_apic_id[NAPICID];
282int io_num_to_apic_id[NAPICID];
283int apic_id_to_logical[NAPICID];
284
285
286/* AP uses this during bootstrap. Do not staticize. */
287char *bootSTK;
288static int bootAP;
289
290/* Hotwire a 0->4MB V==P mapping */
291extern pt_entry_t *KPTphys;
292
293/* SMP page table page */
294extern pt_entry_t *SMPpt;
295
296struct pcb stoppcbs[MAXCPU];
297
298#ifdef APIC_IO
299/* Variables needed for SMP tlb shootdown. */
300vm_offset_t smp_tlb_addr1;
301vm_offset_t smp_tlb_addr2;
302volatile int smp_tlb_wait;
303static struct mtx smp_tlb_mtx;
304#endif
305
306/*
307 * Local data and functions.
308 */
309
310/* Set to 1 once we're ready to let the APs out of the pen. */
311static volatile int aps_ready = 0;
312
313static int mp_capable;
314static u_int boot_address;
315static u_int base_memory;
316
317static int picmode; /* 0: virtual wire mode, 1: PIC mode */
318static mpfps_t mpfps;
319static int search_for_sig(u_int32_t target, int count);
320static void mp_enable(u_int boot_addr);
321
322static void mptable_hyperthread_fixup(u_int id_mask);
323static void mptable_pass1(void);
324static int mptable_pass2(void);
325static void default_mp_table(int type);
326static void fix_mp_table(void);
327static void setup_apic_irq_mapping(void);
328static void init_locks(void);
329static int start_all_aps(u_int boot_addr);
330static void install_ap_tramp(u_int boot_addr);
331static int start_ap(int logicalCpu, u_int boot_addr);
332void ap_init(void);
333static int apic_int_is_bus_type(int intr, int bus_type);
334static void release_aps(void *dummy);
335
336/*
337 * initialize all the SMP locks
338 */
339
340/* lock region used by kernel profiling */
341int mcount_lock;
342
343#ifdef USE_COMLOCK
344/* locks com (tty) data/hardware accesses: a FASTINTR() */
345struct mtx com_mtx;
346#endif /* USE_COMLOCK */
347
348static void
349init_locks(void)
350{
351
352#ifdef USE_COMLOCK
353 mtx_init(&com_mtx, "com", NULL, MTX_SPIN);
354#endif /* USE_COMLOCK */
355#ifdef APIC_IO
356 mtx_init(&smp_tlb_mtx, "tlb", NULL, MTX_SPIN);
357#endif
358}
359
360/*
361 * Calculate usable address in base memory for AP trampoline code.
362 */
363u_int
364mp_bootaddress(u_int basemem)
365{
366 POSTCODE(MP_BOOTADDRESS_POST);
367
368 base_memory = basemem * 1024; /* convert to bytes */
369
370 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
371 if ((base_memory - boot_address) < bootMP_size)
372 boot_address -= 4096; /* not enough, lower by 4k */
373
374 return boot_address;
375}
376
377
378/*
379 * Look for an Intel MP spec table (ie, SMP capable hardware).
380 */
381void
382i386_mp_probe(void)
383{
384 int x;
385 u_long segment;
386 u_int32_t target;
387
388 POSTCODE(MP_PROBE_POST);
389
390 /* see if EBDA exists */
391 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
392 /* search first 1K of EBDA */
393 target = (u_int32_t) (segment << 4);
394 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
395 goto found;
396 } else {
397 /* last 1K of base memory, effective 'top of base' passed in */
398 target = (u_int32_t) (base_memory - 0x400);
399 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
400 goto found;
401 }
402
403 /* search the BIOS */
404 target = (u_int32_t) BIOS_BASE;
405 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
406 goto found;
407
408 /* nothing found */
409 mpfps = (mpfps_t)0;
410 mp_capable = 0;
411 return;
412
413found:
414 /* calculate needed resources */
415 mpfps = (mpfps_t)x;
416 mptable_pass1();
417
418 /* flag fact that we are running multiple processors */
419 mp_capable = 1;
420}
421
422int
423cpu_mp_probe(void)
424{
425 /*
426 * Record BSP in CPU map
427 * This is done here so that MBUF init code works correctly.
428 */
429 all_cpus = 1;
430
431 return (mp_capable);
432}
433
434/*
435 * Initialize the SMP hardware and the APIC and start up the AP's.
436 */
437void
438cpu_mp_start(void)
439{
440 POSTCODE(MP_START_POST);
441
442 /* look for MP capable motherboard */
443 if (mp_capable)
444 mp_enable(boot_address);
445 else
446 panic("MP hardware not found!");
447
448 cpu_setregs();
449}
450
451
452/*
453 * Print various information about the SMP system hardware and setup.
454 */
455void
456cpu_mp_announce(void)
457{
458 int x;
459
460 POSTCODE(MP_ANNOUNCE_POST);
461
462 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
463 printf(", version: 0x%08x", cpu_apic_versions[0]);
464 printf(", at 0x%08x\n", cpu_apic_address);
465 for (x = 1; x <= mp_naps; ++x) {
466 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
467 printf(", version: 0x%08x", cpu_apic_versions[x]);
468 printf(", at 0x%08x\n", cpu_apic_address);
469 }
470
471#if defined(APIC_IO)
472 for (x = 0; x < mp_napics; ++x) {
473 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
474 printf(", version: 0x%08x", io_apic_versions[x]);
475 printf(", at 0x%08x\n", io_apic_address[x]);
476 }
477#else
478 printf(" Warning: APIC I/O disabled\n");
479#endif /* APIC_IO */
480}
481
482/*
483 * AP cpu's call this to sync up protected mode.
484 */
485void
486init_secondary(void)
487{
488 int gsel_tss;
489 int x, myid = bootAP;
490 u_int cr0;
491
492 gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
493 gdt_segs[GPROC0_SEL].ssd_base =
494 (int) &SMP_prvspace[myid].pcpu.pc_common_tss;
495 SMP_prvspace[myid].pcpu.pc_prvspace =
496 &SMP_prvspace[myid].pcpu;
497
498 for (x = 0; x < NGDT; x++) {
499 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
500 }
501
502 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
503 r_gdt.rd_base = (int) &gdt[myid * NGDT];
504 lgdt(&r_gdt); /* does magic intra-segment return */
505
506 lidt(&r_idt);
507
508 lldt(_default_ldt);
509 PCPU_SET(currentldt, _default_ldt);
510
511 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
512 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
513 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
514 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
515 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
516 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
517 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
518 ltr(gsel_tss);
519
520 /*
521 * Set to a known state:
522 * Set by mpboot.s: CR0_PG, CR0_PE
523 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
524 */
525 cr0 = rcr0();
526 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
527 load_cr0(cr0);
528
529 pmap_set_opt();
530}
531
532
533#if defined(APIC_IO)
534/*
535 * Final configuration of the BSP's local APIC:
536 * - disable 'pic mode'.
537 * - disable 'virtual wire mode'.
538 * - enable NMI.
539 */
540void
541bsp_apic_configure(void)
542{
543 u_char byte;
544 u_int32_t temp;
545
546 /* leave 'pic mode' if necessary */
547 if (picmode) {
548 outb(0x22, 0x70); /* select IMCR */
549 byte = inb(0x23); /* current contents */
550 byte |= 0x01; /* mask external INTR */
551 outb(0x23, byte); /* disconnect 8259s/NMI */
552 }
553
554 /* mask lint0 (the 8259 'virtual wire' connection) */
555 temp = lapic.lvt_lint0;
556 temp |= APIC_LVT_M; /* set the mask */
557 lapic.lvt_lint0 = temp;
558
559 /* setup lint1 to handle NMI */
560 temp = lapic.lvt_lint1;
561 temp &= ~APIC_LVT_M; /* clear the mask */
562 lapic.lvt_lint1 = temp;
563
564 if (bootverbose)
565 apic_dump("bsp_apic_configure()");
566}
567#endif /* APIC_IO */
568
569
570/*******************************************************************
571 * local functions and data
572 */
573
574/*
575 * start the SMP system
576 */
577static void
578mp_enable(u_int boot_addr)
579{
580 int x;
581#if defined(APIC_IO)
582 int apic;
583 u_int ux;
584#endif /* APIC_IO */
585
586 POSTCODE(MP_ENABLE_POST);
587
588 /* turn on 4MB of V == P addressing so we can get to MP table */
589 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
590 invltlb();
591
592 /* examine the MP table for needed info, uses physical addresses */
593 x = mptable_pass2();
594
595 *(int *)PTD = 0;
596 invltlb();
597
598 /* can't process default configs till the CPU APIC is pmapped */
599 if (x)
600 default_mp_table(x);
601
602 /* post scan cleanup */
603 fix_mp_table();
604 setup_apic_irq_mapping();
605
606#if defined(APIC_IO)
607
608 /* fill the LOGICAL io_apic_versions table */
609 for (apic = 0; apic < mp_napics; ++apic) {
610 ux = io_apic_read(apic, IOAPIC_VER);
611 io_apic_versions[apic] = ux;
612 io_apic_set_id(apic, IO_TO_ID(apic));
613 }
614
615 /* program each IO APIC in the system */
616 for (apic = 0; apic < mp_napics; ++apic)
617 if (io_apic_setup(apic) < 0)
618 panic("IO APIC setup failure");
619
620 /* install a 'Spurious INTerrupt' vector */
621 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
622 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
623
624 /* install an inter-CPU IPI for TLB invalidation */
625 setidt(XINVLTLB_OFFSET, Xinvltlb,
626 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
627 setidt(XINVLPG_OFFSET, Xinvlpg,
628 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
629 setidt(XINVLRNG_OFFSET, Xinvlrng,
630 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
631
632 /* install an inter-CPU IPI for forwarding hardclock() */
633 setidt(XHARDCLOCK_OFFSET, Xhardclock,
634 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
635
636 /* install an inter-CPU IPI for forwarding statclock() */
637 setidt(XSTATCLOCK_OFFSET, Xstatclock,
638 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
639
640#ifdef LAZY_SWITCH
641 /* install an inter-CPU IPI for lazy pmap release */
642 setidt(XLAZYPMAP_OFFSET, Xlazypmap,
643 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
644#endif
645
646 /* install an inter-CPU IPI for all-CPU rendezvous */
647 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
648 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
649
650 /* install an inter-CPU IPI for forcing an additional software trap */
651 setidt(XCPUAST_OFFSET, Xcpuast,
652 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
653
654 /* install an inter-CPU IPI for CPU stop/restart */
655 setidt(XCPUSTOP_OFFSET, Xcpustop,
656 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
657
658#if defined(TEST_TEST1)
659 /* install a "fake hardware INTerrupt" vector */
660 setidt(XTEST1_OFFSET, Xtest1,
661 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
662#endif /** TEST_TEST1 */
663
664#endif /* APIC_IO */
665
666 /* initialize all SMP locks */
667 init_locks();
668
669 /* start each Application Processor */
670 start_all_aps(boot_addr);
671}
672
673
674/*
675 * look for the MP spec signature
676 */
677
678/* string defined by the Intel MP Spec as identifying the MP table */
679#define MP_SIG 0x5f504d5f /* _MP_ */
680#define NEXT(X) ((X) += 4)
681static int
682search_for_sig(u_int32_t target, int count)
683{
684 int x;
685 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
686
687 for (x = 0; x < count; NEXT(x))
688 if (addr[x] == MP_SIG)
689 /* make array index a byte index */
690 return (target + (x * sizeof(u_int32_t)));
691
692 return -1;
693}
694
695
696static basetable_entry basetable_entry_types[] =
697{
698 {0, 20, "Processor"},
699 {1, 8, "Bus"},
700 {2, 8, "I/O APIC"},
701 {3, 8, "I/O INT"},
702 {4, 8, "Local INT"}
703};
704
705typedef struct BUSDATA {
706 u_char bus_id;
707 enum busTypes bus_type;
708} bus_datum;
709
710typedef struct INTDATA {
711 u_char int_type;
712 u_short int_flags;
713 u_char src_bus_id;
714 u_char src_bus_irq;
715 u_char dst_apic_id;
716 u_char dst_apic_int;
717 u_char int_vector;
718} io_int, local_int;
719
720typedef struct BUSTYPENAME {
721 u_char type;
722 char name[7];
723} bus_type_name;
724
725static bus_type_name bus_type_table[] =
726{
727 {CBUS, "CBUS"},
728 {CBUSII, "CBUSII"},
729 {EISA, "EISA"},
730 {MCA, "MCA"},
731 {UNKNOWN_BUSTYPE, "---"},
732 {ISA, "ISA"},
733 {MCA, "MCA"},
734 {UNKNOWN_BUSTYPE, "---"},
735 {UNKNOWN_BUSTYPE, "---"},
736 {UNKNOWN_BUSTYPE, "---"},
737 {UNKNOWN_BUSTYPE, "---"},
738 {UNKNOWN_BUSTYPE, "---"},
739 {PCI, "PCI"},
740 {UNKNOWN_BUSTYPE, "---"},
741 {UNKNOWN_BUSTYPE, "---"},
742 {UNKNOWN_BUSTYPE, "---"},
743 {UNKNOWN_BUSTYPE, "---"},
744 {XPRESS, "XPRESS"},
745 {UNKNOWN_BUSTYPE, "---"}
746};
747/* from MP spec v1.4, table 5-1 */
748static int default_data[7][5] =
749{
750/* nbus, id0, type0, id1, type1 */
751 {1, 0, ISA, 255, 255},
752 {1, 0, EISA, 255, 255},
753 {1, 0, EISA, 255, 255},
754 {1, 0, MCA, 255, 255},
755 {2, 0, ISA, 1, PCI},
756 {2, 0, EISA, 1, PCI},
757 {2, 0, MCA, 1, PCI}
758};
759
760
761/* the bus data */
762static bus_datum *bus_data;
763
764/* the IO INT data, one entry per possible APIC INTerrupt */
765static io_int *io_apic_ints;
766
767static int nintrs;
768
769static int processor_entry(proc_entry_ptr entry, int cpu);
770static int bus_entry(bus_entry_ptr entry, int bus);
771static int io_apic_entry(io_apic_entry_ptr entry, int apic);
772static int int_entry(int_entry_ptr entry, int intr);
773static int lookup_bus_type(char *name);
774
775
776/*
777 * 1st pass on motherboard's Intel MP specification table.
778 *
779 * initializes:
780 * mp_ncpus = 1
781 *
782 * determines:
783 * cpu_apic_address (common to all CPUs)
784 * io_apic_address[N]
785 * mp_naps
786 * mp_nbusses
787 * mp_napics
788 * nintrs
789 */
790static void
791mptable_pass1(void)
792{
793 int x;
794 mpcth_t cth;
795 int totalSize;
796 void* position;
797 int count;
798 int type;
799 u_int id_mask;
800
801 POSTCODE(MPTABLE_PASS1_POST);
802
803 /* clear various tables */
804 for (x = 0; x < NAPICID; ++x) {
805 io_apic_address[x] = ~0; /* IO APIC address table */
806 }
807
808 /* init everything to empty */
809 mp_naps = 0;
810 mp_nbusses = 0;
811 mp_napics = 0;
812 nintrs = 0;
813 id_mask = 0;
814
815 /* check for use of 'default' configuration */
816 if (MPFPS_MPFB1 != 0) {
817 /* use default addresses */
818 cpu_apic_address = DEFAULT_APIC_BASE;
819 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
820
821 /* fill in with defaults */
822 mp_naps = 2; /* includes BSP */
823 mp_maxid = 1;
824 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
825#if defined(APIC_IO)
826 mp_napics = 1;
827 nintrs = 16;
828#endif /* APIC_IO */
829 }
830 else {
831 if ((cth = mpfps->pap) == 0)
832 panic("MP Configuration Table Header MISSING!");
833
834 cpu_apic_address = (vm_offset_t) cth->apic_address;
835
836 /* walk the table, recording info of interest */
837 totalSize = cth->base_table_length - sizeof(struct MPCTH);
838 position = (u_char *) cth + sizeof(struct MPCTH);
839 count = cth->entry_count;
840
841 while (count--) {
842 switch (type = *(u_char *) position) {
843 case 0: /* processor_entry */
844 if (((proc_entry_ptr)position)->cpu_flags
845 & PROCENTRY_FLAG_EN) {
846 ++mp_naps;
847 mp_maxid++;
848 id_mask |= 1 <<
849 ((proc_entry_ptr)position)->apic_id;
850 }
851 break;
852 case 1: /* bus_entry */
853 ++mp_nbusses;
854 break;
855 case 2: /* io_apic_entry */
856 if (((io_apic_entry_ptr)position)->apic_flags
857 & IOAPICENTRY_FLAG_EN)
858 io_apic_address[mp_napics++] =
859 (vm_offset_t)((io_apic_entry_ptr)
860 position)->apic_address;
861 break;
862 case 3: /* int_entry */
863 ++nintrs;
864 break;
865 case 4: /* int_entry */
866 break;
867 default:
868 panic("mpfps Base Table HOSED!");
869 /* NOTREACHED */
870 }
871
872 totalSize -= basetable_entry_types[type].length;
873 (u_char*)position += basetable_entry_types[type].length;
874 }
875 }
876
877 /* qualify the numbers */
878 if (mp_naps > MAXCPU) {
879 printf("Warning: only using %d of %d available CPUs!\n",
880 MAXCPU, mp_naps);
881 mp_naps = MAXCPU;
882 }
883
884 /* See if we need to fixup HT logical CPUs. */
885 mptable_hyperthread_fixup(id_mask);
886
887 /*
888 * Count the BSP.
889 * This is also used as a counter while starting the APs.
890 */
891 mp_ncpus = 1;
892
893 --mp_naps; /* subtract the BSP */
894}
895
896
897/*
898 * 2nd pass on motherboard's Intel MP specification table.
899 *
900 * sets:
901 * boot_cpu_id
902 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
903 * CPU_TO_ID(N), logical CPU to APIC ID table
904 * IO_TO_ID(N), logical IO to APIC ID table
905 * bus_data[N]
906 * io_apic_ints[N]
907 */
908static int
909mptable_pass2(void)
910{
911 struct PROCENTRY proc;
912 int x;
913 mpcth_t cth;
914 int totalSize;
915 void* position;
916 int count;
917 int type;
918 int apic, bus, cpu, intr;
919 int i, j;
920 int pgeflag;
921
922 POSTCODE(MPTABLE_PASS2_POST);
923
924 /* Initialize fake proc entry for use with HT fixup. */
925 bzero(&proc, sizeof(proc));
926 proc.type = 0;
927 proc.cpu_flags = PROCENTRY_FLAG_EN;
928
929 pgeflag = 0; /* XXX - Not used under SMP yet. */
930
931 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
932 M_DEVBUF, M_WAITOK);
933 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
934 M_DEVBUF, M_WAITOK);
935 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
936 M_DEVBUF, M_WAITOK);
937 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
938 M_DEVBUF, M_WAITOK);
939
940 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
941
942 for (i = 0; i < mp_napics; i++) {
943 for (j = 0; j < mp_napics; j++) {
944 /* same page frame as a previous IO apic? */
945 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
946 (io_apic_address[i] & PG_FRAME)) {
947 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
948 + (NPTEPG-2-j) * PAGE_SIZE
949 + (io_apic_address[i] & PAGE_MASK));
950 break;
951 }
952 /* use this slot if available */
953 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
954 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
955 pgeflag | (io_apic_address[i] & PG_FRAME));
956 ioapic[i] = (ioapic_t *)((u_int)SMP_prvspace
957 + (NPTEPG-2-j) * PAGE_SIZE
958 + (io_apic_address[i] & PAGE_MASK));
959 break;
960 }
961 }
962 }
963
964 /* clear various tables */
965 for (x = 0; x < NAPICID; ++x) {
966 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
967 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
968 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
969 }
970
971 /* clear bus data table */
972 for (x = 0; x < mp_nbusses; ++x)
973 bus_data[x].bus_id = 0xff;
974
975 /* clear IO APIC INT table */
976 for (x = 0; x < (nintrs + 1); ++x) {
977 io_apic_ints[x].int_type = 0xff;
978 io_apic_ints[x].int_vector = 0xff;
979 }
980
981 /* setup the cpu/apic mapping arrays */
982 boot_cpu_id = -1;
983
984 /* record whether PIC or virtual-wire mode */
985 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
986
987 /* check for use of 'default' configuration */
988 if (MPFPS_MPFB1 != 0)
989 return MPFPS_MPFB1; /* return default configuration type */
990
991 if ((cth = mpfps->pap) == 0)
992 panic("MP Configuration Table Header MISSING!");
993
994 /* walk the table, recording info of interest */
995 totalSize = cth->base_table_length - sizeof(struct MPCTH);
996 position = (u_char *) cth + sizeof(struct MPCTH);
997 count = cth->entry_count;
998 apic = bus = intr = 0;
999 cpu = 1; /* pre-count the BSP */
1000
1001 while (count--) {
1002 switch (type = *(u_char *) position) {
1003 case 0:
1004 if (processor_entry(position, cpu)) {
1005 if (logical_cpus != 0 &&
1006 cpu % logical_cpus != 0)
1007 logical_cpus_mask |= (1 << cpu);
1008 ++cpu;
1009 }
1010 if (need_hyperthreading_fixup) {
1011 /*
1012 * Create fake mptable processor entries
1013 * and feed them to processor_entry() to
1014 * enumerate the logical CPUs.
1015 */
1016 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1017 for (i = 1; i < logical_cpus; i++) {
1018 proc.apic_id++;
1019 (void)processor_entry(&proc, cpu);
1020 logical_cpus_mask |= (1 << cpu);
1021 cpu++;
1022 }
1023 }
1024 break;
1025 case 1:
1026 if (bus_entry(position, bus))
1027 ++bus;
1028 break;
1029 case 2:
1030 if (io_apic_entry(position, apic))
1031 ++apic;
1032 break;
1033 case 3:
1034 if (int_entry(position, intr))
1035 ++intr;
1036 break;
1037 case 4:
1038 /* int_entry(position); */
1039 break;
1040 default:
1041 panic("mpfps Base Table HOSED!");
1042 /* NOTREACHED */
1043 }
1044
1045 totalSize -= basetable_entry_types[type].length;
1046 (u_char *) position += basetable_entry_types[type].length;
1047 }
1048
1049 if (boot_cpu_id == -1)
1050 panic("NO BSP found!");
1051
1052 /* report fact that its NOT a default configuration */
1053 return 0;
1054}
1055
1056/*
1057 * Check if we should perform a hyperthreading "fix-up" to
1058 * enumerate any logical CPU's that aren't already listed
1059 * in the table.
1060 *
1061 * XXX: We assume that all of the physical CPUs in the
1062 * system have the same number of logical CPUs.
1063 *
1064 * XXX: We assume that APIC ID's are allocated such that
1065 * the APIC ID's for a physical processor are aligned
1066 * with the number of logical CPU's in the processor.
1067 */
1068static void
1069mptable_hyperthread_fixup(u_int id_mask)
1070{
1071 u_int i, id;
1072
1073 /* Nothing to do if there is no HTT support. */
1074 if ((cpu_feature & CPUID_HTT) == 0)
1075 return;
1076 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1077 if (logical_cpus <= 1)
1078 return;
1079
1080 /*
1081 * For each APIC ID of a CPU that is set in the mask,
1082 * scan the other candidate APIC ID's for this
1083 * physical processor. If any of those ID's are
1084 * already in the table, then kill the fixup.
1085 */
1086 for (id = 0; id <= MAXCPU; id++) {
1087 if ((id_mask & 1 << id) == 0)
1088 continue;
1089 /* First, make sure we are on a logical_cpus boundary. */
1090 if (id % logical_cpus != 0)
1091 return;
1092 for (i = id + 1; i < id + logical_cpus; i++)
1093 if ((id_mask & 1 << i) != 0)
1094 return;
1095 }
1096
1097 /*
1098 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1099 * mp_naps and mp_maxid right now.
1100 */
1101 need_hyperthreading_fixup = 1;
1102 mp_maxid *= logical_cpus;
1103 mp_naps *= logical_cpus;
1104}
1105
1106void
1107assign_apic_irq(int apic, int intpin, int irq)
1108{
1109 int x;
1110
1111 if (int_to_apicintpin[irq].ioapic != -1)
1112 panic("assign_apic_irq: inconsistent table");
1113
1114 int_to_apicintpin[irq].ioapic = apic;
1115 int_to_apicintpin[irq].int_pin = intpin;
1116 int_to_apicintpin[irq].apic_address = ioapic[apic];
1117 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1118
1119 for (x = 0; x < nintrs; x++) {
1120 if ((io_apic_ints[x].int_type == 0 ||
1121 io_apic_ints[x].int_type == 3) &&
1122 io_apic_ints[x].int_vector == 0xff &&
1123 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1124 io_apic_ints[x].dst_apic_int == intpin)
1125 io_apic_ints[x].int_vector = irq;
1126 }
1127}
1128
1129void
1130revoke_apic_irq(int irq)
1131{
1132 int x;
1133 int oldapic;
1134 int oldintpin;
1135
1136 if (int_to_apicintpin[irq].ioapic == -1)
1137 panic("revoke_apic_irq: inconsistent table");
1138
1139 oldapic = int_to_apicintpin[irq].ioapic;
1140 oldintpin = int_to_apicintpin[irq].int_pin;
1141
1142 int_to_apicintpin[irq].ioapic = -1;
1143 int_to_apicintpin[irq].int_pin = 0;
1144 int_to_apicintpin[irq].apic_address = NULL;
1145 int_to_apicintpin[irq].redirindex = 0;
1146
1147 for (x = 0; x < nintrs; x++) {
1148 if ((io_apic_ints[x].int_type == 0 ||
1149 io_apic_ints[x].int_type == 3) &&
1150 io_apic_ints[x].int_vector != 0xff &&
1151 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1152 io_apic_ints[x].dst_apic_int == oldintpin)
1153 io_apic_ints[x].int_vector = 0xff;
1154 }
1155}
1156
1157
1158static void
1159allocate_apic_irq(int intr)
1160{
1161 int apic;
1162 int intpin;
1163 int irq;
1164
1165 if (io_apic_ints[intr].int_vector != 0xff)
1166 return; /* Interrupt handler already assigned */
1167
1168 if (io_apic_ints[intr].int_type != 0 &&
1169 (io_apic_ints[intr].int_type != 3 ||
1170 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1171 io_apic_ints[intr].dst_apic_int == 0)))
1172 return; /* Not INT or ExtInt on != (0, 0) */
1173
1174 irq = 0;
1175 while (irq < APIC_INTMAPSIZE &&
1176 int_to_apicintpin[irq].ioapic != -1)
1177 irq++;
1178
1179 if (irq >= APIC_INTMAPSIZE)
1180 return; /* No free interrupt handlers */
1181
1182 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1183 intpin = io_apic_ints[intr].dst_apic_int;
1184
1185 assign_apic_irq(apic, intpin, irq);
1186 io_apic_setup_intpin(apic, intpin);
1187}
1188
1189
1190static void
1191swap_apic_id(int apic, int oldid, int newid)
1192{
1193 int x;
1194 int oapic;
1195
1196
1197 if (oldid == newid)
1198 return; /* Nothing to do */
1199
1200 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1201 apic, oldid, newid);
1202
1203 /* Swap physical APIC IDs in interrupt entries */
1204 for (x = 0; x < nintrs; x++) {
1205 if (io_apic_ints[x].dst_apic_id == oldid)
1206 io_apic_ints[x].dst_apic_id = newid;
1207 else if (io_apic_ints[x].dst_apic_id == newid)
1208 io_apic_ints[x].dst_apic_id = oldid;
1209 }
1210
1211 /* Swap physical APIC IDs in IO_TO_ID mappings */
1212 for (oapic = 0; oapic < mp_napics; oapic++)
1213 if (IO_TO_ID(oapic) == newid)
1214 break;
1215
1216 if (oapic < mp_napics) {
1217 printf("Changing APIC ID for IO APIC #%d from "
1218 "%d to %d in MP table\n",
1219 oapic, newid, oldid);
1220 IO_TO_ID(oapic) = oldid;
1221 }
1222 IO_TO_ID(apic) = newid;
1223}
1224
1225
1226static void
1227fix_id_to_io_mapping(void)
1228{
1229 int x;
1230
1231 for (x = 0; x < NAPICID; x++)
1232 ID_TO_IO(x) = -1;
1233
1234 for (x = 0; x <= mp_naps; x++)
1235 if (CPU_TO_ID(x) < NAPICID)
1236 ID_TO_IO(CPU_TO_ID(x)) = x;
1237
1238 for (x = 0; x < mp_napics; x++)
1239 if (IO_TO_ID(x) < NAPICID)
1240 ID_TO_IO(IO_TO_ID(x)) = x;
1241}
1242
1243
1244static int
1245first_free_apic_id(void)
1246{
1247 int freeid, x;
1248
1249 for (freeid = 0; freeid < NAPICID; freeid++) {
1250 for (x = 0; x <= mp_naps; x++)
1251 if (CPU_TO_ID(x) == freeid)
1252 break;
1253 if (x <= mp_naps)
1254 continue;
1255 for (x = 0; x < mp_napics; x++)
1256 if (IO_TO_ID(x) == freeid)
1257 break;
1258 if (x < mp_napics)
1259 continue;
1260 return freeid;
1261 }
1262 return freeid;
1263}
1264
1265
1266static int
1267io_apic_id_acceptable(int apic, int id)
1268{
1269 int cpu; /* Logical CPU number */
1270 int oapic; /* Logical IO APIC number for other IO APIC */
1271
1272 if (id >= NAPICID)
1273 return 0; /* Out of range */
1274
1275 for (cpu = 0; cpu <= mp_naps; cpu++)
1276 if (CPU_TO_ID(cpu) == id)
1277 return 0; /* Conflict with CPU */
1278
1279 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1280 if (IO_TO_ID(oapic) == id)
1281 return 0; /* Conflict with other APIC */
1282
1283 return 1; /* ID is acceptable for IO APIC */
1284}
1285
1286
1287/*
1288 * parse an Intel MP specification table
1289 */
1290static void
1291fix_mp_table(void)
1292{
1293 int x;
1294 int id;
1295 int bus_0 = 0; /* Stop GCC warning */
1296 int bus_pci = 0; /* Stop GCC warning */
1297 int num_pci_bus;
1298 int apic; /* IO APIC unit number */
1299 int freeid; /* Free physical APIC ID */
1300 int physid; /* Current physical IO APIC ID */
1301
1302 /*
1303 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1304 * did it wrong. The MP spec says that when more than 1 PCI bus
1305 * exists the BIOS must begin with bus entries for the PCI bus and use
1306 * actual PCI bus numbering. This implies that when only 1 PCI bus
1307 * exists the BIOS can choose to ignore this ordering, and indeed many
1308 * MP motherboards do ignore it. This causes a problem when the PCI
1309 * sub-system makes requests of the MP sub-system based on PCI bus
1310 * numbers. So here we look for the situation and renumber the
1311 * busses and associated INTs in an effort to "make it right".
1312 */
1313
1314 /* find bus 0, PCI bus, count the number of PCI busses */
1315 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1316 if (bus_data[x].bus_id == 0) {
1317 bus_0 = x;
1318 }
1319 if (bus_data[x].bus_type == PCI) {
1320 ++num_pci_bus;
1321 bus_pci = x;
1322 }
1323 }
1324 /*
1325 * bus_0 == slot of bus with ID of 0
1326 * bus_pci == slot of last PCI bus encountered
1327 */
1328
1329 /* check the 1 PCI bus case for sanity */
1330 /* if it is number 0 all is well */
1331 if (num_pci_bus == 1 &&
1332 bus_data[bus_pci].bus_id != 0) {
1333
1334 /* mis-numbered, swap with whichever bus uses slot 0 */
1335
1336 /* swap the bus entry types */
1337 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1338 bus_data[bus_0].bus_type = PCI;
1339
1340 /* swap each relavant INTerrupt entry */
1341 id = bus_data[bus_pci].bus_id;
1342 for (x = 0; x < nintrs; ++x) {
1343 if (io_apic_ints[x].src_bus_id == id) {
1344 io_apic_ints[x].src_bus_id = 0;
1345 }
1346 else if (io_apic_ints[x].src_bus_id == 0) {
1347 io_apic_ints[x].src_bus_id = id;
1348 }
1349 }
1350 }
1351
1352 /* Assign IO APIC IDs.
1353 *
1354 * First try the existing ID. If a conflict is detected, try
1355 * the ID in the MP table. If a conflict is still detected, find
1356 * a free id.
1357 *
1358 * We cannot use the ID_TO_IO table before all conflicts has been
1359 * resolved and the table has been corrected.
1360 */
1361 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1362
1363 /* First try to use the value set by the BIOS */
1364 physid = io_apic_get_id(apic);
1365 if (io_apic_id_acceptable(apic, physid)) {
1366 if (IO_TO_ID(apic) != physid)
1367 swap_apic_id(apic, IO_TO_ID(apic), physid);
1368 continue;
1369 }
1370
1371 /* Then check if the value in the MP table is acceptable */
1372 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1373 continue;
1374
1375 /* Last resort, find a free APIC ID and use it */
1376 freeid = first_free_apic_id();
1377 if (freeid >= NAPICID)
1378 panic("No free physical APIC IDs found");
1379
1380 if (io_apic_id_acceptable(apic, freeid)) {
1381 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1382 continue;
1383 }
1384 panic("Free physical APIC ID not usable");
1385 }
1386 fix_id_to_io_mapping();
1387
1388 /* detect and fix broken Compaq MP table */
1389 if (apic_int_type(0, 0) == -1) {
1390 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1391 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1392 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1393 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1394 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1395 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1396 nintrs++;
1397 }
1398}
1399
1400
1401/* Assign low level interrupt handlers */
1402static void
1403setup_apic_irq_mapping(void)
1404{
1405 int x;
1406 int int_vector;
1407
1408 /* Clear array */
1409 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1410 int_to_apicintpin[x].ioapic = -1;
1411 int_to_apicintpin[x].int_pin = 0;
1412 int_to_apicintpin[x].apic_address = NULL;
1413 int_to_apicintpin[x].redirindex = 0;
1414 }
1415
1416 /* First assign ISA/EISA interrupts */
1417 for (x = 0; x < nintrs; x++) {
1418 int_vector = io_apic_ints[x].src_bus_irq;
1419 if (int_vector < APIC_INTMAPSIZE &&
1420 io_apic_ints[x].int_vector == 0xff &&
1421 int_to_apicintpin[int_vector].ioapic == -1 &&
1422 (apic_int_is_bus_type(x, ISA) ||
1423 apic_int_is_bus_type(x, EISA)) &&
1424 io_apic_ints[x].int_type == 0) {
1425 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1426 io_apic_ints[x].dst_apic_int,
1427 int_vector);
1428 }
1429 }
1430
1431 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1432 for (x = 0; x < nintrs; x++) {
1433 if (io_apic_ints[x].dst_apic_int == 0 &&
1434 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1435 io_apic_ints[x].int_vector == 0xff &&
1436 int_to_apicintpin[0].ioapic == -1 &&
1437 io_apic_ints[x].int_type == 3) {
1438 assign_apic_irq(0, 0, 0);
1439 break;
1440 }
1441 }
1442 /* PCI interrupt assignment is deferred */
1443}
1444
1445
1446static int
1447processor_entry(proc_entry_ptr entry, int cpu)
1448{
1449 /* check for usability */
1450 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1451 return 0;
1452
1453 if(entry->apic_id >= NAPICID)
1454 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1455 /* check for BSP flag */
1456 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1457 boot_cpu_id = entry->apic_id;
1458 CPU_TO_ID(0) = entry->apic_id;
1459 ID_TO_CPU(entry->apic_id) = 0;
1460 return 0; /* its already been counted */
1461 }
1462
1463 /* add another AP to list, if less than max number of CPUs */
1464 else if (cpu < MAXCPU) {
1465 CPU_TO_ID(cpu) = entry->apic_id;
1466 ID_TO_CPU(entry->apic_id) = cpu;
1467 return 1;
1468 }
1469
1470 return 0;
1471}
1472
1473
1474static int
1475bus_entry(bus_entry_ptr entry, int bus)
1476{
1477 int x;
1478 char c, name[8];
1479
1480 /* encode the name into an index */
1481 for (x = 0; x < 6; ++x) {
1482 if ((c = entry->bus_type[x]) == ' ')
1483 break;
1484 name[x] = c;
1485 }
1486 name[x] = '\0';
1487
1488 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1489 panic("unknown bus type: '%s'", name);
1490
1491 bus_data[bus].bus_id = entry->bus_id;
1492 bus_data[bus].bus_type = x;
1493
1494 return 1;
1495}
1496
1497
1498static int
1499io_apic_entry(io_apic_entry_ptr entry, int apic)
1500{
1501 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1502 return 0;
1503
1504 IO_TO_ID(apic) = entry->apic_id;
1505 if (entry->apic_id < NAPICID)
1506 ID_TO_IO(entry->apic_id) = apic;
1507
1508 return 1;
1509}
1510
1511
1512static int
1513lookup_bus_type(char *name)
1514{
1515 int x;
1516
1517 for (x = 0; x < MAX_BUSTYPE; ++x)
1518 if (strcmp(bus_type_table[x].name, name) == 0)
1519 return bus_type_table[x].type;
1520
1521 return UNKNOWN_BUSTYPE;
1522}
1523
1524
1525static int
1526int_entry(int_entry_ptr entry, int intr)
1527{
1528 int apic;
1529
1530 io_apic_ints[intr].int_type = entry->int_type;
1531 io_apic_ints[intr].int_flags = entry->int_flags;
1532 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1533 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1534 if (entry->dst_apic_id == 255) {
1535 /* This signal goes to all IO APICS. Select an IO APIC
1536 with sufficient number of interrupt pins */
1537 for (apic = 0; apic < mp_napics; apic++)
1538 if (((io_apic_read(apic, IOAPIC_VER) &
1539 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1540 entry->dst_apic_int)
1541 break;
1542 if (apic < mp_napics)
1543 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1544 else
1545 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1546 } else
1547 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1548 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1549
1550 return 1;
1551}
1552
1553
1554static int
1555apic_int_is_bus_type(int intr, int bus_type)
1556{
1557 int bus;
1558
1559 for (bus = 0; bus < mp_nbusses; ++bus)
1560 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1561 && ((int) bus_data[bus].bus_type == bus_type))
1562 return 1;
1563
1564 return 0;
1565}
1566
1567
1568/*
1569 * Given a traditional ISA INT mask, return an APIC mask.
1570 */
1571u_int
1572isa_apic_mask(u_int isa_mask)
1573{
1574 int isa_irq;
1575 int apic_pin;
1576
1577#if defined(SKIP_IRQ15_REDIRECT)
1578 if (isa_mask == (1 << 15)) {
1579 printf("skipping ISA IRQ15 redirect\n");
1580 return isa_mask;
1581 }
1582#endif /* SKIP_IRQ15_REDIRECT */
1583
1584 isa_irq = ffs(isa_mask); /* find its bit position */
1585 if (isa_irq == 0) /* doesn't exist */
1586 return 0;
1587 --isa_irq; /* make it zero based */
1588
1589 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1590 if (apic_pin == -1)
1591 return 0;
1592
1593 return (1 << apic_pin); /* convert pin# to a mask */
1594}
1595
1596
1597/*
1598 * Determine which APIC pin an ISA/EISA INT is attached to.
1599 */
1600#define INTTYPE(I) (io_apic_ints[(I)].int_type)
1601#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1602#define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1603#define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1604
1605#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1606int
1607isa_apic_irq(int isa_irq)
1608{
1609 int intr;
1610
1611 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1612 if (INTTYPE(intr) == 0) { /* standard INT */
1613 if (SRCBUSIRQ(intr) == isa_irq) {
1614 if (apic_int_is_bus_type(intr, ISA) ||
1615 apic_int_is_bus_type(intr, EISA)) {
1616 if (INTIRQ(intr) == 0xff)
1617 return -1; /* unassigned */
1618 return INTIRQ(intr); /* found */
1619 }
1620 }
1621 }
1622 }
1623 return -1; /* NOT found */
1624}
1625
1626
1627/*
1628 * Determine which APIC pin a PCI INT is attached to.
1629 */
1630#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1631#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1632#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1633int
1634pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1635{
1636 int intr;
1637
1638 --pciInt; /* zero based */
1639
1640 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1641 if ((INTTYPE(intr) == 0) /* standard INT */
1642 && (SRCBUSID(intr) == pciBus)
1643 && (SRCBUSDEVICE(intr) == pciDevice)
1644 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1645 if (apic_int_is_bus_type(intr, PCI)) {
1646 if (INTIRQ(intr) == 0xff)
1647 allocate_apic_irq(intr);
1648 if (INTIRQ(intr) == 0xff)
1649 return -1; /* unassigned */
1650 return INTIRQ(intr); /* exact match */
1651 }
1652
1653 return -1; /* NOT found */
1654}
1655
1656int
1657next_apic_irq(int irq)
1658{
1659 int intr, ointr;
1660 int bus, bustype;
1661
1662 bus = 0;
1663 bustype = 0;
1664 for (intr = 0; intr < nintrs; intr++) {
1665 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1666 continue;
1667 bus = SRCBUSID(intr);
1668 bustype = apic_bus_type(bus);
1669 if (bustype != ISA &&
1670 bustype != EISA &&
1671 bustype != PCI)
1672 continue;
1673 break;
1674 }
1675 if (intr >= nintrs) {
1676 return -1;
1677 }
1678 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1679 if (INTTYPE(ointr) != 0)
1680 continue;
1681 if (bus != SRCBUSID(ointr))
1682 continue;
1683 if (bustype == PCI) {
1684 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1685 continue;
1686 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1687 continue;
1688 }
1689 if (bustype == ISA || bustype == EISA) {
1690 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1691 continue;
1692 }
1693 if (INTPIN(intr) == INTPIN(ointr))
1694 continue;
1695 break;
1696 }
1697 if (ointr >= nintrs) {
1698 return -1;
1699 }
1700 return INTIRQ(ointr);
1701}
1702#undef SRCBUSLINE
1703#undef SRCBUSDEVICE
1704#undef SRCBUSID
1705#undef SRCBUSIRQ
1706
1707#undef INTPIN
1708#undef INTIRQ
1709#undef INTAPIC
1710#undef INTTYPE
1711
1712
1713/*
1714 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1715 *
1716 * XXX FIXME:
1717 * Exactly what this means is unclear at this point. It is a solution
1718 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1719 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1720 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1721 * option.
1722 */
1723int
1724undirect_isa_irq(int rirq)
1725{
1726#if defined(READY)
1727 if (bootverbose)
1728 printf("Freeing redirected ISA irq %d.\n", rirq);
1729 /** FIXME: tickle the MB redirector chip */
1730 return -1;
1731#else
1732 if (bootverbose)
1733 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1734 return 0;
1735#endif /* READY */
1736}
1737
1738
1739/*
1740 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1741 */
1742int
1743undirect_pci_irq(int rirq)
1744{
1745#if defined(READY)
1746 if (bootverbose)
1747 printf("Freeing redirected PCI irq %d.\n", rirq);
1748
1749 /** FIXME: tickle the MB redirector chip */
1750 return -1;
1751#else
1752 if (bootverbose)
1753 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1754 rirq);
1755 return 0;
1756#endif /* READY */
1757}
1758
1759
1760/*
1761 * given a bus ID, return:
1762 * the bus type if found
1763 * -1 if NOT found
1764 */
1765int
1766apic_bus_type(int id)
1767{
1768 int x;
1769
1770 for (x = 0; x < mp_nbusses; ++x)
1771 if (bus_data[x].bus_id == id)
1772 return bus_data[x].bus_type;
1773
1774 return -1;
1775}
1776
1777
1778/*
1779 * given a LOGICAL APIC# and pin#, return:
1780 * the associated src bus ID if found
1781 * -1 if NOT found
1782 */
1783int
1784apic_src_bus_id(int apic, int pin)
1785{
1786 int x;
1787
1788 /* search each of the possible INTerrupt sources */
1789 for (x = 0; x < nintrs; ++x)
1790 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1791 (pin == io_apic_ints[x].dst_apic_int))
1792 return (io_apic_ints[x].src_bus_id);
1793
1794 return -1; /* NOT found */
1795}
1796
1797
1798/*
1799 * given a LOGICAL APIC# and pin#, return:
1800 * the associated src bus IRQ if found
1801 * -1 if NOT found
1802 */
1803int
1804apic_src_bus_irq(int apic, int pin)
1805{
1806 int x;
1807
1808 for (x = 0; x < nintrs; x++)
1809 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1810 (pin == io_apic_ints[x].dst_apic_int))
1811 return (io_apic_ints[x].src_bus_irq);
1812
1813 return -1; /* NOT found */
1814}
1815
1816
1817/*
1818 * given a LOGICAL APIC# and pin#, return:
1819 * the associated INTerrupt type if found
1820 * -1 if NOT found
1821 */
1822int
1823apic_int_type(int apic, int pin)
1824{
1825 int x;
1826
1827 /* search each of the possible INTerrupt sources */
1828 for (x = 0; x < nintrs; ++x)
1829 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1830 (pin == io_apic_ints[x].dst_apic_int))
1831 return (io_apic_ints[x].int_type);
1832
1833 return -1; /* NOT found */
1834}
1835
1836int
1837apic_irq(int apic, int pin)
1838{
1839 int x;
1840 int res;
1841
1842 for (x = 0; x < nintrs; ++x)
1843 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1844 (pin == io_apic_ints[x].dst_apic_int)) {
1845 res = io_apic_ints[x].int_vector;
1846 if (res == 0xff)
1847 return -1;
1848 if (apic != int_to_apicintpin[res].ioapic)
1849 panic("apic_irq: inconsistent table");
1850 if (pin != int_to_apicintpin[res].int_pin)
1851 panic("apic_irq inconsistent table (2)");
1852 return res;
1853 }
1854 return -1;
1855}
1856
1857
1858/*
1859 * given a LOGICAL APIC# and pin#, return:
1860 * the associated trigger mode if found
1861 * -1 if NOT found
1862 */
1863int
1864apic_trigger(int apic, int pin)
1865{
1866 int x;
1867
1868 /* search each of the possible INTerrupt sources */
1869 for (x = 0; x < nintrs; ++x)
1870 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1871 (pin == io_apic_ints[x].dst_apic_int))
1872 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1873
1874 return -1; /* NOT found */
1875}
1876
1877
1878/*
1879 * given a LOGICAL APIC# and pin#, return:
1880 * the associated 'active' level if found
1881 * -1 if NOT found
1882 */
1883int
1884apic_polarity(int apic, int pin)
1885{
1886 int x;
1887
1888 /* search each of the possible INTerrupt sources */
1889 for (x = 0; x < nintrs; ++x)
1890 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1891 (pin == io_apic_ints[x].dst_apic_int))
1892 return (io_apic_ints[x].int_flags & 0x03);
1893
1894 return -1; /* NOT found */
1895}
1896
1897
1898/*
1899 * set data according to MP defaults
1900 * FIXME: probably not complete yet...
1901 */
1902static void
1903default_mp_table(int type)
1904{
1905 int ap_cpu_id;
1906#if defined(APIC_IO)
1907 int io_apic_id;
1908 int pin;
1909#endif /* APIC_IO */
1910
1911#if 0
1912 printf(" MP default config type: %d\n", type);
1913 switch (type) {
1914 case 1:
1915 printf(" bus: ISA, APIC: 82489DX\n");
1916 break;
1917 case 2:
1918 printf(" bus: EISA, APIC: 82489DX\n");
1919 break;
1920 case 3:
1921 printf(" bus: EISA, APIC: 82489DX\n");
1922 break;
1923 case 4:
1924 printf(" bus: MCA, APIC: 82489DX\n");
1925 break;
1926 case 5:
1927 printf(" bus: ISA+PCI, APIC: Integrated\n");
1928 break;
1929 case 6:
1930 printf(" bus: EISA+PCI, APIC: Integrated\n");
1931 break;
1932 case 7:
1933 printf(" bus: MCA+PCI, APIC: Integrated\n");
1934 break;
1935 default:
1936 printf(" future type\n");
1937 break;
1938 /* NOTREACHED */
1939 }
1940#endif /* 0 */
1941
1942 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1943 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1944
1945 /* BSP */
1946 CPU_TO_ID(0) = boot_cpu_id;
1947 ID_TO_CPU(boot_cpu_id) = 0;
1948
1949 /* one and only AP */
1950 CPU_TO_ID(1) = ap_cpu_id;
1951 ID_TO_CPU(ap_cpu_id) = 1;
1952
1953#if defined(APIC_IO)
1954 /* one and only IO APIC */
1955 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1956
1957 /*
1958 * sanity check, refer to MP spec section 3.6.6, last paragraph
1959 * necessary as some hardware isn't properly setting up the IO APIC
1960 */
1961#if defined(REALLY_ANAL_IOAPICID_VALUE)
1962 if (io_apic_id != 2) {
1963#else
1964 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1965#endif /* REALLY_ANAL_IOAPICID_VALUE */
1966 io_apic_set_id(0, 2);
1967 io_apic_id = 2;
1968 }
1969 IO_TO_ID(0) = io_apic_id;
1970 ID_TO_IO(io_apic_id) = 0;
1971#endif /* APIC_IO */
1972
1973 /* fill out bus entries */
1974 switch (type) {
1975 case 1:
1976 case 2:
1977 case 3:
1978 case 4:
1979 case 5:
1980 case 6:
1981 case 7:
1982 bus_data[0].bus_id = default_data[type - 1][1];
1983 bus_data[0].bus_type = default_data[type - 1][2];
1984 bus_data[1].bus_id = default_data[type - 1][3];
1985 bus_data[1].bus_type = default_data[type - 1][4];
1986 break;
1987
1988 /* case 4: case 7: MCA NOT supported */
1989 default: /* illegal/reserved */
1990 panic("BAD default MP config: %d", type);
1991 /* NOTREACHED */
1992 }
1993
1994#if defined(APIC_IO)
1995 /* general cases from MP v1.4, table 5-2 */
1996 for (pin = 0; pin < 16; ++pin) {
1997 io_apic_ints[pin].int_type = 0;
1998 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1999 io_apic_ints[pin].src_bus_id = 0;
2000 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2001 io_apic_ints[pin].dst_apic_id = io_apic_id;
2002 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2003 }
2004
2005 /* special cases from MP v1.4, table 5-2 */
2006 if (type == 2) {
2007 io_apic_ints[2].int_type = 0xff; /* N/C */
2008 io_apic_ints[13].int_type = 0xff; /* N/C */
2009#if !defined(APIC_MIXED_MODE)
2010 /** FIXME: ??? */
2011 panic("sorry, can't support type 2 default yet");
2012#endif /* APIC_MIXED_MODE */
2013 }
2014 else
2015 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2016
2017 if (type == 7)
2018 io_apic_ints[0].int_type = 0xff; /* N/C */
2019 else
2020 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2021#endif /* APIC_IO */
2022}
2023
2024
2025/*
2026 * start each AP in our list
2027 */
2028static int
2029start_all_aps(u_int boot_addr)
2030{
2031 int x, i, pg;
2032#ifndef PC98
2033 u_char mpbiosreason;
2034#endif
2035 u_long mpbioswarmvec;
2036 struct pcpu *pc;
2037 char *stack;
2038 uintptr_t kptbase;
2039
2040 POSTCODE(START_ALL_APS_POST);
2041
2042 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
2043
2044 /* initialize BSP's local APIC */
2045 apic_initialize();
2046 bsp_apic_ready = 1;
2047
2048 /* install the AP 1st level boot code */
2049 install_ap_tramp(boot_addr);
2050
2051
2052 /* save the current value of the warm-start vector */
2053 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2054#ifndef PC98
2055 outb(CMOS_REG, BIOS_RESET);
2056 mpbiosreason = inb(CMOS_DATA);
2057#endif
2058
2059 /* set up temporary P==V mapping for AP boot */
2060 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2061 kptbase = (uintptr_t)(void *)KPTphys;
2062 for (x = 0; x < NKPT; x++)
2063 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2064 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2065 invltlb();
2066
2067 /* start each AP */
2068 for (x = 1; x <= mp_naps; ++x) {
2069
2070 /* This is a bit verbose, it will go away soon. */
2071
2072 /* first page of AP's private space */
2073 pg = x * i386_btop(sizeof(struct privatespace));
2074
2075 /* allocate a new private data page */
2076 pc = (struct pcpu *)kmem_alloc(kernel_map, PAGE_SIZE);
2077
2078 /* wire it into the private page table page */
2079 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys(pc));
2080
2081 /* allocate and set up an idle stack data page */
2082 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); /* XXXKSE */
2083 for (i = 0; i < KSTACK_PAGES; i++)
2084 SMPpt[pg + 1 + i] = (pt_entry_t)
2085 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2086
2087 /* prime data page for it to use */
2088 pcpu_init(pc, x, sizeof(struct pcpu));
2089
2090 /* setup a vector to our boot code */
2091 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2092 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2093#ifndef PC98
2094 outb(CMOS_REG, BIOS_RESET);
2095 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2096#endif
2097
2098 bootSTK = &SMP_prvspace[x].idlekstack[KSTACK_PAGES * PAGE_SIZE];
2099 bootAP = x;
2100
2101 /* attempt to start the Application Processor */
2102 CHECK_INIT(99); /* setup checkpoints */
2103 if (!start_ap(x, boot_addr)) {
2104 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2105 CHECK_PRINT("trace"); /* show checkpoints */
2106 /* better panic as the AP may be running loose */
2107 printf("panic y/n? [y] ");
2108 if (cngetc() != 'n')
2109 panic("bye-bye");
2110 }
2111 CHECK_PRINT("trace"); /* show checkpoints */
2112
2113 /* record its version info */
2114 cpu_apic_versions[x] = cpu_apic_versions[0];
2115
2116 all_cpus |= (1 << x); /* record AP in CPU map */
2117 }
2118
2119 /* build our map of 'other' CPUs */
2120 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
2121
2122 /* fill in our (BSP) APIC version */
2123 cpu_apic_versions[0] = lapic.version;
2124
2125 /* restore the warmstart vector */
2126 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2127#ifndef PC98
2128 outb(CMOS_REG, BIOS_RESET);
2129 outb(CMOS_DATA, mpbiosreason);
2130#endif
2131
2132 /*
2133 * Set up the idle context for the BSP. Similar to above except
2134 * that some was done by locore, some by pmap.c and some is implicit
2135 * because the BSP is cpu#0 and the page is initially zero, and also
2136 * because we can refer to variables by name on the BSP..
2137 */
2138
2139 /* Allocate and setup BSP idle stack */
2140 stack = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
2141 for (i = 0; i < KSTACK_PAGES; i++)
2142 SMPpt[1 + i] = (pt_entry_t)
2143 (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
2144
2145 for (x = 0; x < NKPT; x++)
2146 PTD[x] = 0;
2147 pmap_set_opt();
2148
2149 /* number of APs actually started */
2150 return mp_ncpus - 1;
2151}
2152
2153
2154/*
2155 * load the 1st level AP boot code into base memory.
2156 */
2157
2158/* targets for relocation */
2159extern void bigJump(void);
2160extern void bootCodeSeg(void);
2161extern void bootDataSeg(void);
2162extern void MPentry(void);
2163extern u_int MP_GDT;
2164extern u_int mp_gdtbase;
2165
2166static void
2167install_ap_tramp(u_int boot_addr)
2168{
2169 int x;
2170 int size = *(int *) ((u_long) & bootMP_size);
2171 u_char *src = (u_char *) ((u_long) bootMP);
2172 u_char *dst = (u_char *) boot_addr + KERNBASE;
2173 u_int boot_base = (u_int) bootMP;
2174 u_int8_t *dst8;
2175 u_int16_t *dst16;
2176 u_int32_t *dst32;
2177
2178 POSTCODE(INSTALL_AP_TRAMP_POST);
2179
2180 for (x = 0; x < size; ++x)
2181 *dst++ = *src++;
2182
2183 /*
2184 * modify addresses in code we just moved to basemem. unfortunately we
2185 * need fairly detailed info about mpboot.s for this to work. changes
2186 * to mpboot.s might require changes here.
2187 */
2188
2189 /* boot code is located in KERNEL space */
2190 dst = (u_char *) boot_addr + KERNBASE;
2191
2192 /* modify the lgdt arg */
2193 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2194 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2195
2196 /* modify the ljmp target for MPentry() */
2197 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2198 *dst32 = ((u_int) MPentry - KERNBASE);
2199
2200 /* modify the target for boot code segment */
2201 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2202 dst8 = (u_int8_t *) (dst16 + 1);
2203 *dst16 = (u_int) boot_addr & 0xffff;
2204 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2205
2206 /* modify the target for boot data segment */
2207 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2208 dst8 = (u_int8_t *) (dst16 + 1);
2209 *dst16 = (u_int) boot_addr & 0xffff;
2210 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2211}
2212
2213
2214/*
2215 * this function starts the AP (application processor) identified
2216 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2217 * to accomplish this. This is necessary because of the nuances
2218 * of the different hardware we might encounter. It ain't pretty,
2219 * but it seems to work.
2220 */
2221static int
2222start_ap(int logical_cpu, u_int boot_addr)
2223{
2224 int physical_cpu;
2225 int vector;
2226 int cpus;
2227 u_long icr_lo, icr_hi;
2228
2229 POSTCODE(START_AP_POST);
2230
2231 /* get the PHYSICAL APIC ID# */
2232 physical_cpu = CPU_TO_ID(logical_cpu);
2233
2234 /* calculate the vector */
2235 vector = (boot_addr >> 12) & 0xff;
2236
2237 /* used as a watchpoint to signal AP startup */
2238 cpus = mp_ncpus;
2239
2240 /*
2241 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2242 * and running the target CPU. OR this INIT IPI might be latched (P5
2243 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2244 * ignored.
2245 */
2246
2247 /* setup the address for the target AP */
2248 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2249 icr_hi |= (physical_cpu << 24);
2250 lapic.icr_hi = icr_hi;
2251
2252 /* do an INIT IPI: assert RESET */
2253 icr_lo = lapic.icr_lo & 0xfff00000;
2254 lapic.icr_lo = icr_lo | 0x0000c500;
2255
2256 /* wait for pending status end */
2257 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2258 /* spin */ ;
2259
2260 /* do an INIT IPI: deassert RESET */
2261 lapic.icr_lo = icr_lo | 0x00008500;
2262
2263 /* wait for pending status end */
2264 u_sleep(10000); /* wait ~10mS */
2265 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2266 /* spin */ ;
2267
2268 /*
2269 * next we do a STARTUP IPI: the previous INIT IPI might still be
2270 * latched, (P5 bug) this 1st STARTUP would then terminate
2271 * immediately, and the previously started INIT IPI would continue. OR
2272 * the previous INIT IPI has already run. and this STARTUP IPI will
2273 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2274 * will run.
2275 */
2276
2277 /* do a STARTUP IPI */
2278 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2279 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2280 /* spin */ ;
2281 u_sleep(200); /* wait ~200uS */
2282
2283 /*
2284 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2285 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2286 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2287 * recognized after hardware RESET or INIT IPI.
2288 */
2289
2290 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2291 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2292 /* spin */ ;
2293 u_sleep(200); /* wait ~200uS */
2294
2295 /* wait for it to start */
2296 set_apic_timer(5000000);/* == 5 seconds */
2297 while (read_apic_timer())
2298 if (mp_ncpus > cpus)
2299 return 1; /* return SUCCESS */
2300
2301 return 0; /* return FAILURE */
2302}
2303
2304#if defined(APIC_IO)
2305
2306#ifdef COUNT_XINVLTLB_HITS
2307u_int xhits_gbl[MAXCPU];
2308u_int xhits_pg[MAXCPU];
2309u_int xhits_rng[MAXCPU];
2310SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
2311SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
2312 sizeof(xhits_gbl), "IU", "");
2313SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
2314 sizeof(xhits_pg), "IU", "");
2315SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
2316 sizeof(xhits_rng), "IU", "");
2317
2318u_int ipi_global;
2319u_int ipi_page;
2320u_int ipi_range;
2321u_int ipi_range_size;
2322SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
2323SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
2324SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
2325SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
2326 0, "");
2327
2328u_int ipi_masked_global;
2329u_int ipi_masked_page;
2330u_int ipi_masked_range;
2331u_int ipi_masked_range_size;
2332SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
2333 &ipi_masked_global, 0, "");
2334SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
2335 &ipi_masked_page, 0, "");
2336SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
2337 &ipi_masked_range, 0, "");
2338SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
2339 &ipi_masked_range_size, 0, "");
2340#endif
2341
2342/*
2343 * Flush the TLB on all other CPU's
2344 */
2345static void
2346smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
2347{
2348 u_int ncpu;
2349 register_t eflags;
2350
2351 ncpu = mp_ncpus - 1; /* does not shootdown self */
2352 if (ncpu < 1)
2353 return; /* no other cpus */
2354 eflags = read_eflags();
2355 if ((eflags & PSL_I) == 0)
2356 panic("absolutely cannot call smp_ipi_shootdown with interrupts already disabled");
2357 mtx_lock_spin(&smp_tlb_mtx);
2358 smp_tlb_addr1 = addr1;
2359 smp_tlb_addr2 = addr2;
2360 atomic_store_rel_int(&smp_tlb_wait, 0);
2361 ipi_all_but_self(vector);
2362 while (smp_tlb_wait < ncpu)
2363 ia32_pause();
2364 mtx_unlock_spin(&smp_tlb_mtx);
2365}
2366
2367/*
2368 * This is about as magic as it gets. fortune(1) has got similar code
2369 * for reversing bits in a word. Who thinks up this stuff??
2370 *
2371 * Yes, it does appear to be consistently faster than:
2372 * while (i = ffs(m)) {
2373 * m >>= i;
2374 * bits++;
2375 * }
2376 * and
2377 * while (lsb = (m & -m)) { // This is magic too
2378 * m &= ~lsb; // or: m ^= lsb
2379 * bits++;
2380 * }
2381 * Both of these latter forms do some very strange things on gcc-3.1 with
2382 * -mcpu=pentiumpro and/or -march=pentiumpro and/or -O or -O2.
2383 * There is probably an SSE or MMX popcnt instruction.
2384 *
2385 * I wonder if this should be in libkern?
2386 *
2387 * XXX Stop the presses! Another one:
2388 * static __inline u_int32_t
2389 * popcnt1(u_int32_t v)
2390 * {
2391 * v -= ((v >> 1) & 0x55555555);
2392 * v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
2393 * v = (v + (v >> 4)) & 0x0F0F0F0F;
2394 * return (v * 0x01010101) >> 24;
2395 * }
2396 * The downside is that it has a multiply. With a pentium3 with
2397 * -mcpu=pentiumpro and -march=pentiumpro then gcc-3.1 will use
2398 * an imull, and in that case it is faster. In most other cases
2399 * it appears slightly slower.
2400 */
2401static __inline u_int32_t
2402popcnt(u_int32_t m)
2403{
2404
2405 m = (m & 0x55555555) + ((m & 0xaaaaaaaa) >> 1);
2406 m = (m & 0x33333333) + ((m & 0xcccccccc) >> 2);
2407 m = (m & 0x0f0f0f0f) + ((m & 0xf0f0f0f0) >> 4);
2408 m = (m & 0x00ff00ff) + ((m & 0xff00ff00) >> 8);
2409 m = (m & 0x0000ffff) + ((m & 0xffff0000) >> 16);
2410 return m;
2411}
2412
2413static void
2414smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
2415{
2416 int ncpu, othercpus;
2417 register_t eflags;
2418
2419 othercpus = mp_ncpus - 1;
2420 if (mask == (u_int)-1) {
2421 ncpu = othercpus;
2422 if (ncpu < 1)
2423 return;
2424 } else {
2425 /* XXX there should be a pcpu self mask */
2426 mask &= ~(1 << PCPU_GET(cpuid));
2427 if (mask == 0)
2428 return;
2429 ncpu = popcnt(mask);
2430 if (ncpu > othercpus) {
2431 /* XXX this should be a panic offence */
2432 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
2433 ncpu, othercpus);
2434 ncpu = othercpus;
2435 }
2436 /* XXX should be a panic, implied by mask == 0 above */
2437 if (ncpu < 1)
2438 return;
2439 }
2440 eflags = read_eflags();
2441 if ((eflags & PSL_I) == 0)
2442 panic("absolutely cannot call smp_targeted_ipi_shootdown with interrupts already disabled");
2443 mtx_lock_spin(&smp_tlb_mtx);
2444 smp_tlb_addr1 = addr1;
2445 smp_tlb_addr2 = addr2;
2446 atomic_store_rel_int(&smp_tlb_wait, 0);
2447 if (mask == (u_int)-1)
2448 ipi_all_but_self(vector);
2449 else
2450 ipi_selected(mask, vector);
2451 while (smp_tlb_wait < ncpu)
2452 ia32_pause();
2453 mtx_unlock_spin(&smp_tlb_mtx);
2454}
2455#endif
2456
2457void
2458smp_invltlb(void)
2459{
2460#if defined(APIC_IO)
2461 if (smp_started) {
2462 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
2463#ifdef COUNT_XINVLTLB_HITS
2464 ipi_global++;
2465#endif
2466 }
2467#endif /* APIC_IO */
2468}
2469
2470void
2471smp_invlpg(vm_offset_t addr)
2472{
2473#if defined(APIC_IO)
2474 if (smp_started) {
2475 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
2476#ifdef COUNT_XINVLTLB_HITS
2477 ipi_page++;
2478#endif
2479 }
2480#endif /* APIC_IO */
2481}
2482
2483void
2484smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
2485{
2486#if defined(APIC_IO)
2487 if (smp_started) {
2488 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
2489#ifdef COUNT_XINVLTLB_HITS
2490 ipi_range++;
2491 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
2492#endif
2493 }
2494#endif /* APIC_IO */
2495}
2496
2497void
2498smp_masked_invltlb(u_int mask)
2499{
2500#if defined(APIC_IO)
2501 if (smp_started) {
2502 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
2503#ifdef COUNT_XINVLTLB_HITS
2504 ipi_masked_global++;
2505#endif
2506 }
2507#endif /* APIC_IO */
2508}
2509
2510void
2511smp_masked_invlpg(u_int mask, vm_offset_t addr)
2512{
2513#if defined(APIC_IO)
2514 if (smp_started) {
2515 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
2516#ifdef COUNT_XINVLTLB_HITS
2517 ipi_masked_page++;
2518#endif
2519 }
2520#endif /* APIC_IO */
2521}
2522
2523void
2524smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
2525{
2526#if defined(APIC_IO)
2527 if (smp_started) {
2528 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
2529#ifdef COUNT_XINVLTLB_HITS
2530 ipi_masked_range++;
2531 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
2532#endif
2533 }
2534#endif /* APIC_IO */
2535}
2536
2537
2538/*
2539 * This is called once the rest of the system is up and running and we're
2540 * ready to let the AP's out of the pen.
2541 */
2542void
2543ap_init(void)
2544{
2545 u_int apic_id;
2546
2547 /* spin until all the AP's are ready */
2548 while (!aps_ready)
2549 ia32_pause();
2550
2551 /* BSP may have changed PTD while we were waiting */
2552 invltlb();
2553
2554#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2555 lidt(&r_idt);
2556#endif
2557
2558 /* set up CPU registers and state */
2559 cpu_setregs();
2560
2561 /* set up FPU state on the AP */
2562 npxinit(__INITIAL_NPXCW__);
2563
2564 /* set up SSE registers */
2565 enable_sse();
2566
2567 /* A quick check from sanity claus */
2568 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2569 if (PCPU_GET(cpuid) != apic_id) {
2570 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
2571 printf("SMP: apic_id = %d\n", apic_id);
2572 printf("PTD[MPPTDI] = %#jx\n", (uintmax_t)PTD[MPPTDI]);
2573 panic("cpuid mismatch! boom!!");
2574 }
2575
2576 /* Init local apic for irq's */
2577 apic_initialize();
2578
2579 /* Set memory range attributes for this CPU to match the BSP */
2580 mem_range_AP_init();
2581
2582 mtx_lock_spin(&ap_boot_mtx);
2583
2584 smp_cpus++;
2585
2586 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
2587 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
2588
2589 /* Build our map of 'other' CPUs. */
2590 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
2591
2592 if (bootverbose)
2593 apic_dump("ap_init()");
2594
2595 if (smp_cpus == mp_ncpus) {
2596 /* enable IPI's, tlb shootdown, freezes etc */
2597 atomic_store_rel_int(&smp_started, 1);
2598 smp_active = 1; /* historic */
2599 }
2600
2601 mtx_unlock_spin(&ap_boot_mtx);
2602
2603 /* wait until all the AP's are up */
2604 while (smp_started == 0)
2605 ia32_pause();
2606
2607 /* ok, now grab sched_lock and enter the scheduler */
2608 mtx_lock_spin(&sched_lock);
2609
2610 binuptime(PCPU_PTR(switchtime));
2611 PCPU_SET(switchticks, ticks);
2612
2613 cpu_throw(NULL, choosethread()); /* doesn't return */
2614
2615 panic("scheduler returned us to %s", __func__);
2616}
2617
2618/*
2619 * For statclock, we send an IPI to all CPU's to have them call this
2620 * function.
2621 *
2622 * WARNING! unpend() will call statclock() directly and skip this
2623 * routine.
2624 */
2625void
2626forwarded_statclock(struct clockframe frame)
2627{
2628
2629 if (profprocs != 0)
2630 profclock(&frame);
2631 if (pscnt == psdiv)
2632 statclock(&frame);
2633}
2634
2635void
2636forward_statclock(void)
2637{
2638 int map;
2639
2640 CTR0(KTR_SMP, "forward_statclock");
2641
2642 if (!smp_started || cold || panicstr)
2643 return;
2644
2645 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2646 if (map != 0)
2647 ipi_selected(map, IPI_STATCLOCK);
2648}
2649
2650/*
2651 * For each hardclock(), we send an IPI to all other CPU's to have them
2652 * execute this function. It would be nice to reduce contention on
2653 * sched_lock if we could simply peek at the CPU to determine the user/kernel
2654 * state and call hardclock_process() on the CPU receiving the clock interrupt
2655 * and then just use a simple IPI to handle any ast's if needed.
2656 *
2657 * WARNING! unpend() will call hardclock_process() directly and skip this
2658 * routine.
2659 */
2660void
2661forwarded_hardclock(struct clockframe frame)
2662{
2663
2664 hardclock_process(&frame);
2665}
2666
2667void
2668forward_hardclock(void)
2669{
2670 u_int map;
2671
2672 CTR0(KTR_SMP, "forward_hardclock");
2673
2674 if (!smp_started || cold || panicstr)
2675 return;
2676
2677 map = PCPU_GET(other_cpus) & ~stopped_cpus ;
2678 if (map != 0)
2679 ipi_selected(map, IPI_HARDCLOCK);
2680}
2681
2682#ifdef APIC_INTR_REORDER
2683/*
2684 * Maintain mapping from softintr vector to isr bit in local apic.
2685 */
2686void
2687set_lapic_isrloc(int intr, int vector)
2688{
2689 if (intr < 0 || intr > 32)
2690 panic("set_apic_isrloc: bad intr argument: %d",intr);
2691 if (vector < ICU_OFFSET || vector > 255)
2692 panic("set_apic_isrloc: bad vector argument: %d",vector);
2693 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2694 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2695}
2696#endif
2697
2698/*
2699 * send an IPI to a set of cpus.
2700 */
2701void
2702ipi_selected(u_int32_t cpus, u_int ipi)
2703{
2704
2705 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
2706 selected_apic_ipi(cpus, ipi, APIC_DELMODE_FIXED);
2707}
2708
2709/*
2710 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
2711 */
2712void
2713ipi_all(u_int ipi)
2714{
2715
2716 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
2717 apic_ipi(APIC_DEST_ALLISELF, ipi, APIC_DELMODE_FIXED);
2718}
2719
2720/*
2721 * send an IPI to all CPUs EXCEPT myself
2722 */
2723void
2724ipi_all_but_self(u_int ipi)
2725{
2726
2727 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
2728 apic_ipi(APIC_DEST_ALLESELF, ipi, APIC_DELMODE_FIXED);
2729}
2730
2731/*
2732 * send an IPI to myself
2733 */
2734void
2735ipi_self(u_int ipi)
2736{
2737
2738 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
2739 apic_ipi(APIC_DEST_SELF, ipi, APIC_DELMODE_FIXED);
2740}
2741
2742static void
2743release_aps(void *dummy __unused)
2744{
2745
2746 if (mp_ncpus == 1)
2747 return;
2748 mtx_lock_spin(&sched_lock);
2749 atomic_store_rel_int(&aps_ready, 1);
2750 while (smp_started == 0)
2751 ia32_pause();
2752 mtx_unlock_spin(&sched_lock);
2753}
2754
2755SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
2756
2757static int hlt_cpus_mask;
2758static int hlt_logical_cpus = 1;
2759static struct sysctl_ctx_list logical_cpu_clist;
2760
2761static int
2762sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
2763{
2764 u_int mask;
2765 int error;
2766
2767 mask = hlt_cpus_mask;
2768 error = sysctl_handle_int(oidp, &mask, 0, req);
2769 if (error || !req->newptr)
2770 return (error);
2771
2772 if (logical_cpus_mask != 0 &&
2773 (mask & logical_cpus_mask) == logical_cpus_mask)
2774 hlt_logical_cpus = 1;
2775 else
2776 hlt_logical_cpus = 0;
2777
2778 if ((mask & all_cpus) == all_cpus)
2779 mask &= ~(1<<0);
2780 hlt_cpus_mask = mask;
2781 return (error);
2782}
2783SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
2784 0, 0, sysctl_hlt_cpus, "IU", "");
2785
2786static int
2787sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
2788{
2789 int disable, error;
2790
2791 disable = hlt_logical_cpus;
2792 error = sysctl_handle_int(oidp, &disable, 0, req);
2793 if (error || !req->newptr)
2794 return (error);
2795
2796 if (disable)
2797 hlt_cpus_mask |= logical_cpus_mask;
2798 else
2799 hlt_cpus_mask &= ~logical_cpus_mask;
2800
2801 if ((hlt_cpus_mask & all_cpus) == all_cpus)
2802 hlt_cpus_mask &= ~(1<<0);
2803
2804 hlt_logical_cpus = disable;
2805 return (error);
2806}
2807
2808static void
2809cpu_hlt_setup(void *dummy __unused)
2810{
2811
2812 if (logical_cpus_mask != 0) {
2813 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
2814 &hlt_logical_cpus);
2815 sysctl_ctx_init(&logical_cpu_clist);
2816 SYSCTL_ADD_PROC(&logical_cpu_clist,
2817 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
2818 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
2819 sysctl_hlt_logical_cpus, "IU", "");
2820 SYSCTL_ADD_UINT(&logical_cpu_clist,
2821 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
2822 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
2823 &logical_cpus_mask, 0, "");
2824
2825 if (hlt_logical_cpus)
2826 hlt_cpus_mask |= logical_cpus_mask;
2827 }
2828}
2829SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
2830
2831int
2832mp_grab_cpu_hlt(void)
2833{
2834 u_int mask = PCPU_GET(cpumask);
2835 int retval;
2836
2837 retval = mask & hlt_cpus_mask;
2838 while (mask & hlt_cpus_mask)
2839 __asm __volatile("sti; hlt" : : : "memory");
2840 return (retval);
2841}
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