1/*-
2 * Copyright (c) 2004 Colin Percival
3 * Copyright (c) 2005 Nate Lawson
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted providing that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 182908 2008-09-10 17:41:41Z jhb $");
30
31#include <sys/param.h>
32#include <sys/bus.h>
33#include <sys/cpu.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/smp.h>
38#include <sys/systm.h>
39
40#include "cpufreq_if.h"
41#include <machine/clock.h>
42#include <machine/md_var.h>
43#include <machine/specialreg.h>
44
45#include <contrib/dev/acpica/acpi.h>
46#include <dev/acpica/acpivar.h>
47#include "acpi_if.h"
48
49/* Status/control registers (from the IA-32 System Programming Guide). */
50#define MSR_PERF_STATUS 0x198
51#define MSR_PERF_CTL 0x199
52
53/* Register and bit for enabling SpeedStep. */
54#define MSR_MISC_ENABLE 0x1a0
55#define MSR_SS_ENABLE (1<<16)
56
57/* Frequency and MSR control values. */
58typedef struct {
59 uint16_t freq;
60 uint16_t volts;
61 uint16_t id16;
62 int power;
63} freq_info;
64
65/* Identifying characteristics of a processor and supported frequencies. */
66typedef struct {
67 const char *vendor;
68 uint32_t id32;
69 freq_info *freqtab;
70} cpu_info;
71
72struct est_softc {
73 device_t dev;
74 int acpi_settings;
75 int msr_settings;
76 freq_info *freq_list;
77};
78
79/* Convert MHz and mV into IDs for passing to the MSR. */
80#define ID16(MHz, mV, bus_clk) \
81 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
82#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
83 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
84
85/* Format for storing IDs in our table. */
86#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \
87 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
88#define FREQ_INFO(MHz, mV, bus_clk) \
89 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
90#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
91 { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
92#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
93 { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
94
95const char intel_id[] = "GenuineIntel";
96const char centaur_id[] = "CentaurHauls";
97static int msr_info_enabled = 0;
98TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
99
100/* Default bus clock value for Centrino processors. */
101#define INTEL_BUS_CLK 100
102
103/* XXX Update this if new CPUs have more settings. */
104#define EST_MAX_SETTINGS 10
105CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
106
107/* Estimate in microseconds of latency for performing a transition. */
108#define EST_TRANS_LAT 1000
109
110/*
111 * Frequency (MHz) and voltage (mV) settings. Data from the
112 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
113 *
114 * Dothan processors have multiple VID#s with different settings for
115 * each VID#. Since we can't uniquely identify this info
116 * without undisclosed methods from Intel, we can't support newer
117 * processors with this table method. If ACPI Px states are supported,
118 * we get info from them.
119 */
120static freq_info PM17_130[] = {
121 /* 130nm 1.70GHz Pentium M */
122 FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
123 FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
124 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
125 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
126 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
127 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
128 FREQ_INFO( 0, 0, 1),
129};
130static freq_info PM16_130[] = {
131 /* 130nm 1.60GHz Pentium M */
132 FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
133 FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
134 FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
135 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
136 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
137 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
138 FREQ_INFO( 0, 0, 1),
139};
140static freq_info PM15_130[] = {
141 /* 130nm 1.50GHz Pentium M */
142 FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
143 FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
144 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
145 FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
146 FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
147 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
148 FREQ_INFO( 0, 0, 1),
149};
150static freq_info PM14_130[] = {
151 /* 130nm 1.40GHz Pentium M */
152 FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
153 FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
154 FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
155 FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
156 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
157 FREQ_INFO( 0, 0, 1),
158};
159static freq_info PM13_130[] = {
160 /* 130nm 1.30GHz Pentium M */
161 FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
162 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
163 FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
164 FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
165 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
166 FREQ_INFO( 0, 0, 1),
167};
168static freq_info PM13_LV_130[] = {
169 /* 130nm 1.30GHz Low Voltage Pentium M */
170 FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
171 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
172 FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
173 FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
174 FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
175 FREQ_INFO( 800, 988, INTEL_BUS_CLK),
176 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
177 FREQ_INFO( 0, 0, 1),
178};
179static freq_info PM12_LV_130[] = {
180 /* 130 nm 1.20GHz Low Voltage Pentium M */
181 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
182 FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
183 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
184 FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
185 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
186 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
187 FREQ_INFO( 0, 0, 1),
188};
189static freq_info PM11_LV_130[] = {
190 /* 130 nm 1.10GHz Low Voltage Pentium M */
191 FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
192 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
193 FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
194 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
195 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
196 FREQ_INFO( 0, 0, 1),
197};
198static freq_info PM11_ULV_130[] = {
199 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
200 FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
201 FREQ_INFO(1000, 988, INTEL_BUS_CLK),
202 FREQ_INFO( 900, 972, INTEL_BUS_CLK),
203 FREQ_INFO( 800, 956, INTEL_BUS_CLK),
204 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
205 FREQ_INFO( 0, 0, 1),
206};
207static freq_info PM10_ULV_130[] = {
208 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
209 FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
210 FREQ_INFO( 900, 988, INTEL_BUS_CLK),
211 FREQ_INFO( 800, 972, INTEL_BUS_CLK),
212 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
213 FREQ_INFO( 0, 0, 1),
214};
215
216/*
217 * Data from "Intel Pentium M Processor on 90nm Process with
218 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
219 */
220static freq_info PM_765A_90[] = {
221 /* 90 nm 2.10GHz Pentium M, VID #A */
222 FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
223 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
224 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
225 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
226 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
227 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
228 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
229 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
230 FREQ_INFO( 0, 0, 1),
231};
232static freq_info PM_765B_90[] = {
233 /* 90 nm 2.10GHz Pentium M, VID #B */
234 FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
235 FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
236 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
237 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
238 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
239 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
240 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
241 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
242 FREQ_INFO( 0, 0, 1),
243};
244static freq_info PM_765C_90[] = {
245 /* 90 nm 2.10GHz Pentium M, VID #C */
246 FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
247 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
248 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
249 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
250 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
251 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
252 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
253 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
254 FREQ_INFO( 0, 0, 1),
255};
256static freq_info PM_765E_90[] = {
257 /* 90 nm 2.10GHz Pentium M, VID #E */
258 FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
259 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
260 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
261 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
262 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
263 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
264 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
265 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
266 FREQ_INFO( 0, 0, 1),
267};
268static freq_info PM_755A_90[] = {
269 /* 90 nm 2.00GHz Pentium M, VID #A */
270 FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
271 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
272 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
273 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
274 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
275 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
276 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
277 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
278 FREQ_INFO( 0, 0, 1),
279};
280static freq_info PM_755B_90[] = {
281 /* 90 nm 2.00GHz Pentium M, VID #B */
282 FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
283 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
284 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
285 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
286 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
287 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
288 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
289 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
290 FREQ_INFO( 0, 0, 1),
291};
292static freq_info PM_755C_90[] = {
293 /* 90 nm 2.00GHz Pentium M, VID #C */
294 FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
295 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
296 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
297 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
298 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
299 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
300 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
301 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
302 FREQ_INFO( 0, 0, 1),
303};
304static freq_info PM_755D_90[] = {
305 /* 90 nm 2.00GHz Pentium M, VID #D */
306 FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
307 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
308 FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
309 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
310 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
311 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
312 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
313 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
314 FREQ_INFO( 0, 0, 1),
315};
316static freq_info PM_745A_90[] = {
317 /* 90 nm 1.80GHz Pentium M, VID #A */
318 FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
319 FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
320 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
321 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
322 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
323 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
324 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
325 FREQ_INFO( 0, 0, 1),
326};
327static freq_info PM_745B_90[] = {
328 /* 90 nm 1.80GHz Pentium M, VID #B */
329 FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
330 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
331 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
332 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
333 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
334 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
335 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
336 FREQ_INFO( 0, 0, 1),
337};
338static freq_info PM_745C_90[] = {
339 /* 90 nm 1.80GHz Pentium M, VID #C */
340 FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
341 FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
342 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
343 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
344 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
345 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
346 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
347 FREQ_INFO( 0, 0, 1),
348};
349static freq_info PM_745D_90[] = {
350 /* 90 nm 1.80GHz Pentium M, VID #D */
351 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
352 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
353 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
354 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
355 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
356 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
357 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
358 FREQ_INFO( 0, 0, 1),
359};
360static freq_info PM_735A_90[] = {
361 /* 90 nm 1.70GHz Pentium M, VID #A */
362 FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
363 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
364 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
365 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
366 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
367 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
368 FREQ_INFO( 0, 0, 1),
369};
370static freq_info PM_735B_90[] = {
371 /* 90 nm 1.70GHz Pentium M, VID #B */
372 FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
373 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
374 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
375 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
376 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
377 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
378 FREQ_INFO( 0, 0, 1),
379};
380static freq_info PM_735C_90[] = {
381 /* 90 nm 1.70GHz Pentium M, VID #C */
382 FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
383 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
384 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
385 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
386 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
387 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
388 FREQ_INFO( 0, 0, 1),
389};
390static freq_info PM_735D_90[] = {
391 /* 90 nm 1.70GHz Pentium M, VID #D */
392 FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
393 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
394 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
395 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
396 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
397 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
398 FREQ_INFO( 0, 0, 1),
399};
400static freq_info PM_725A_90[] = {
401 /* 90 nm 1.60GHz Pentium M, VID #A */
402 FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
403 FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
404 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
405 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
406 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
407 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
408 FREQ_INFO( 0, 0, 1),
409};
410static freq_info PM_725B_90[] = {
411 /* 90 nm 1.60GHz Pentium M, VID #B */
412 FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
413 FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
414 FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
415 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
416 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
417 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
418 FREQ_INFO( 0, 0, 1),
419};
420static freq_info PM_725C_90[] = {
421 /* 90 nm 1.60GHz Pentium M, VID #C */
422 FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
423 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
424 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
425 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
426 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
427 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
428 FREQ_INFO( 0, 0, 1),
429};
430static freq_info PM_725D_90[] = {
431 /* 90 nm 1.60GHz Pentium M, VID #D */
432 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
433 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
434 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
435 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
436 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
437 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
438 FREQ_INFO( 0, 0, 1),
439};
440static freq_info PM_715A_90[] = {
441 /* 90 nm 1.50GHz Pentium M, VID #A */
442 FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
443 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
444 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
445 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
446 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
447 FREQ_INFO( 0, 0, 1),
448};
449static freq_info PM_715B_90[] = {
450 /* 90 nm 1.50GHz Pentium M, VID #B */
451 FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
452 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
453 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
454 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
455 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
456 FREQ_INFO( 0, 0, 1),
457};
458static freq_info PM_715C_90[] = {
459 /* 90 nm 1.50GHz Pentium M, VID #C */
460 FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
461 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
462 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
463 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
464 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
465 FREQ_INFO( 0, 0, 1),
466};
467static freq_info PM_715D_90[] = {
468 /* 90 nm 1.50GHz Pentium M, VID #D */
469 FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
470 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
471 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
472 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
473 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
474 FREQ_INFO( 0, 0, 1),
475};
476static freq_info PM_778_90[] = {
477 /* 90 nm 1.60GHz Low Voltage Pentium M */
478 FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
479 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
480 FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
481 FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
482 FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
483 FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
484 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
485 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
486 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
487 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
488 FREQ_INFO( 0, 0, 1),
489};
490static freq_info PM_758_90[] = {
491 /* 90 nm 1.50GHz Low Voltage Pentium M */
492 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
493 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
494 FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
495 FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
496 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
497 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
498 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
499 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
500 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
501 FREQ_INFO( 0, 0, 1),
502};
503static freq_info PM_738_90[] = {
504 /* 90 nm 1.40GHz Low Voltage Pentium M */
505 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
506 FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
507 FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
508 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
509 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
510 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
511 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
512 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
513 FREQ_INFO( 0, 0, 1),
514};
515static freq_info PM_773G_90[] = {
516 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
517 FREQ_INFO(1300, 956, INTEL_BUS_CLK),
518 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
519 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
520 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
521 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
522 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
523 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
524};
525static freq_info PM_773H_90[] = {
526 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
527 FREQ_INFO(1300, 940, INTEL_BUS_CLK),
528 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
529 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
530 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
531 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
532 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
533 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
534};
535static freq_info PM_773I_90[] = {
536 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
537 FREQ_INFO(1300, 924, INTEL_BUS_CLK),
538 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
539 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
540 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
541 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
542 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
543 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
544};
545static freq_info PM_773J_90[] = {
546 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
547 FREQ_INFO(1300, 908, INTEL_BUS_CLK),
548 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
549 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
550 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
551 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
552 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
553 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
554};
555static freq_info PM_773K_90[] = {
556 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
557 FREQ_INFO(1300, 892, INTEL_BUS_CLK),
558 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
559 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
560 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
561 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
562 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
563 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
564};
565static freq_info PM_773L_90[] = {
566 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
567 FREQ_INFO(1300, 876, INTEL_BUS_CLK),
568 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
569 FREQ_INFO(1100, 860, INTEL_BUS_CLK),
570 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
571 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
572 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
573 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
574};
575static freq_info PM_753G_90[] = {
576 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
577 FREQ_INFO(1200, 956, INTEL_BUS_CLK),
578 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
579 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
580 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
581 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
582 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
583};
584static freq_info PM_753H_90[] = {
585 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
586 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
587 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
588 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
589 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
590 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
591 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
592};
593static freq_info PM_753I_90[] = {
594 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
595 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
596 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
597 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
598 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
599 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
600 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
601};
602static freq_info PM_753J_90[] = {
603 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
604 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
605 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
606 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
607 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
608 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
609 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
610};
611static freq_info PM_753K_90[] = {
612 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
613 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
614 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
615 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
616 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
617 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
618 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
619};
620static freq_info PM_753L_90[] = {
621 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
622 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
623 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
624 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
625 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
626 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
627 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
628};
629
630static freq_info PM_733JG_90[] = {
631 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
632 FREQ_INFO(1100, 956, INTEL_BUS_CLK),
633 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
634 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
635 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
636 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
637};
638static freq_info PM_733JH_90[] = {
639 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
640 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
641 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
642 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
643 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
644 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
645};
646static freq_info PM_733JI_90[] = {
647 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
648 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
649 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
650 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
651 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
652 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
653};
654static freq_info PM_733JJ_90[] = {
655 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
656 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
657 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
658 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
659 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
660 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
661};
662static freq_info PM_733JK_90[] = {
663 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
664 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
665 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
666 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
667 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
668 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
669};
670static freq_info PM_733JL_90[] = {
671 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
672 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
673 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
674 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
675 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
676 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
677};
678static freq_info PM_733_90[] = {
679 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
680 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
681 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
682 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
683 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
684 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
685 FREQ_INFO( 0, 0, 1),
686};
687static freq_info PM_723_90[] = {
688 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
689 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
690 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
691 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
692 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
693 FREQ_INFO( 0, 0, 1),
694};
695
696/*
697 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
698 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
699 */
700static freq_info C7M_795[] = {
701 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
702 FREQ_INFO_PWR(2000, 1148, 133, 20000),
703 FREQ_INFO_PWR(1867, 1132, 133, 18000),
704 FREQ_INFO_PWR(1600, 1100, 133, 15000),
705 FREQ_INFO_PWR(1467, 1052, 133, 13000),
706 FREQ_INFO_PWR(1200, 1004, 133, 10000),
707 FREQ_INFO_PWR( 800, 844, 133, 7000),
708 FREQ_INFO_PWR( 667, 844, 133, 6000),
709 FREQ_INFO_PWR( 533, 844, 133, 5000),
710 FREQ_INFO(0, 0, 1),
711};
712static freq_info C7M_785[] = {
713 /* 1.80GHz Centaur C7-M 533 Mhz FSB */
714 FREQ_INFO_PWR(1867, 1148, 133, 18000),
715 FREQ_INFO_PWR(1600, 1100, 133, 15000),
716 FREQ_INFO_PWR(1467, 1052, 133, 13000),
717 FREQ_INFO_PWR(1200, 1004, 133, 10000),
718 FREQ_INFO_PWR( 800, 844, 133, 7000),
719 FREQ_INFO_PWR( 667, 844, 133, 6000),
720 FREQ_INFO_PWR( 533, 844, 133, 5000),
721 FREQ_INFO(0, 0, 1),
722};
723static freq_info C7M_765[] = {
724 /* 1.60GHz Centaur C7-M 533 Mhz FSB */
725 FREQ_INFO_PWR(1600, 1084, 133, 15000),
726 FREQ_INFO_PWR(1467, 1052, 133, 13000),
727 FREQ_INFO_PWR(1200, 1004, 133, 10000),
728 FREQ_INFO_PWR( 800, 844, 133, 7000),
729 FREQ_INFO_PWR( 667, 844, 133, 6000),
730 FREQ_INFO_PWR( 533, 844, 133, 5000),
731 FREQ_INFO(0, 0, 1),
732};
733
734static freq_info C7M_794[] = {
735 /* 2.00GHz Centaur C7-M 400 Mhz FSB */
736 FREQ_INFO_PWR(2000, 1148, 100, 20000),
737 FREQ_INFO_PWR(1800, 1132, 100, 18000),
738 FREQ_INFO_PWR(1600, 1100, 100, 15000),
739 FREQ_INFO_PWR(1400, 1052, 100, 13000),
740 FREQ_INFO_PWR(1000, 1004, 100, 10000),
741 FREQ_INFO_PWR( 800, 844, 100, 7000),
742 FREQ_INFO_PWR( 600, 844, 100, 6000),
743 FREQ_INFO_PWR( 400, 844, 100, 5000),
744 FREQ_INFO(0, 0, 1),
745};
746static freq_info C7M_784[] = {
747 /* 1.80GHz Centaur C7-M 400 Mhz FSB */
748 FREQ_INFO_PWR(1800, 1148, 100, 18000),
749 FREQ_INFO_PWR(1600, 1100, 100, 15000),
750 FREQ_INFO_PWR(1400, 1052, 100, 13000),
751 FREQ_INFO_PWR(1000, 1004, 100, 10000),
752 FREQ_INFO_PWR( 800, 844, 100, 7000),
753 FREQ_INFO_PWR( 600, 844, 100, 6000),
754 FREQ_INFO_PWR( 400, 844, 100, 5000),
755 FREQ_INFO(0, 0, 1),
756};
757static freq_info C7M_764[] = {
758 /* 1.60GHz Centaur C7-M 400 Mhz FSB */
759 FREQ_INFO_PWR(1600, 1084, 100, 15000),
760 FREQ_INFO_PWR(1400, 1052, 100, 13000),
761 FREQ_INFO_PWR(1000, 1004, 100, 10000),
762 FREQ_INFO_PWR( 800, 844, 100, 7000),
763 FREQ_INFO_PWR( 600, 844, 100, 6000),
764 FREQ_INFO_PWR( 400, 844, 100, 5000),
765 FREQ_INFO(0, 0, 1),
766};
767static freq_info C7M_754[] = {
768 /* 1.50GHz Centaur C7-M 400 Mhz FSB */
769 FREQ_INFO_PWR(1500, 1004, 100, 12000),
770 FREQ_INFO_PWR(1400, 988, 100, 11000),
771 FREQ_INFO_PWR(1000, 940, 100, 9000),
772 FREQ_INFO_PWR( 800, 844, 100, 7000),
773 FREQ_INFO_PWR( 600, 844, 100, 6000),
774 FREQ_INFO_PWR( 400, 844, 100, 5000),
775 FREQ_INFO(0, 0, 1),
776};
777static freq_info C7M_771[] = {
778 /* 1.20GHz Centaur C7-M 400 Mhz FSB */
779 FREQ_INFO_PWR(1200, 860, 100, 7000),
780 FREQ_INFO_PWR(1000, 860, 100, 6000),
781 FREQ_INFO_PWR( 800, 844, 100, 5500),
782 FREQ_INFO_PWR( 600, 844, 100, 5000),
783 FREQ_INFO_PWR( 400, 844, 100, 4000),
784 FREQ_INFO(0, 0, 1),
785};
786
787static freq_info C7M_775_ULV[] = {
788 /* 1.50GHz Centaur C7-M ULV */
789 FREQ_INFO_PWR(1500, 956, 100, 7500),
790 FREQ_INFO_PWR(1400, 940, 100, 6000),
791 FREQ_INFO_PWR(1000, 860, 100, 5000),
792 FREQ_INFO_PWR( 800, 828, 100, 2800),
793 FREQ_INFO_PWR( 600, 796, 100, 2500),
794 FREQ_INFO_PWR( 400, 796, 100, 2000),
795 FREQ_INFO(0, 0, 1),
796};
797static freq_info C7M_772_ULV[] = {
798 /* 1.20GHz Centaur C7-M ULV */
799 FREQ_INFO_PWR(1200, 844, 100, 5000),
800 FREQ_INFO_PWR(1000, 844, 100, 4000),
801 FREQ_INFO_PWR( 800, 828, 100, 2800),
802 FREQ_INFO_PWR( 600, 796, 100, 2500),
803 FREQ_INFO_PWR( 400, 796, 100, 2000),
804 FREQ_INFO(0, 0, 1),
805};
806static freq_info C7M_779_ULV[] = {
807 /* 1.00GHz Centaur C7-M ULV */
808 FREQ_INFO_PWR(1000, 796, 100, 3500),
809 FREQ_INFO_PWR( 800, 796, 100, 2800),
810 FREQ_INFO_PWR( 600, 796, 100, 2500),
811 FREQ_INFO_PWR( 400, 796, 100, 2000),
812 FREQ_INFO(0, 0, 1),
813};
814static freq_info C7M_770_ULV[] = {
815 /* 1.00GHz Centaur C7-M ULV */
816 FREQ_INFO_PWR(1000, 844, 100, 5000),
817 FREQ_INFO_PWR( 800, 796, 100, 2800),
818 FREQ_INFO_PWR( 600, 796, 100, 2500),
819 FREQ_INFO_PWR( 400, 796, 100, 2000),
820 FREQ_INFO(0, 0, 1),
821};
822
823static cpu_info ESTprocs[] = {
824 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
825 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
826 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
827 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
828 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
829 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
830 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),
831 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK),
832 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK),
833 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK),
834 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK),
835 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK),
836 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK),
837 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK),
838 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK),
839 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK),
840 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK),
841 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK),
842 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK),
843 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK),
844 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK),
845 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK),
846 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK),
847 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK),
848 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK),
849 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK),
850 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK),
851 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK),
852 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK),
853 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK),
854 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK),
855 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK),
856 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK),
857 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK),
858 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK),
859 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK),
860 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK),
861 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK),
862 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK),
863 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK),
864 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK),
865 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK),
866 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK),
867 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK),
868 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK),
869 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK),
870 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK),
871 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK),
872 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK),
873 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
874 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
875 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
876 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
877 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
878 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
879 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
880 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
881
882 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133),
883 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
884 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133),
885 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
886 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133),
887 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
888 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
889 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
890 CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
891 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
892 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
893 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
894 { NULL, 0, NULL },
895};
896
897static void est_identify(driver_t *driver, device_t parent);
898static int est_features(driver_t *driver, u_int *features);
899static int est_probe(device_t parent);
900static int est_attach(device_t parent);
901static int est_detach(device_t parent);
902static int est_get_info(device_t dev);
903static int est_acpi_info(device_t dev, freq_info **freqs);
904static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
905static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
906static freq_info *est_get_current(freq_info *freq_list);
907static int est_settings(device_t dev, struct cf_setting *sets, int *count);
908static int est_set(device_t dev, const struct cf_setting *set);
909static int est_get(device_t dev, struct cf_setting *set);
910static int est_type(device_t dev, int *type);
911static int est_set_id16(device_t dev, uint16_t id16, int need_check);
912static void est_get_id16(uint16_t *id16_p);
913
914static device_method_t est_methods[] = {
915 /* Device interface */
916 DEVMETHOD(device_identify, est_identify),
917 DEVMETHOD(device_probe, est_probe),
918 DEVMETHOD(device_attach, est_attach),
919 DEVMETHOD(device_detach, est_detach),
920
921 /* cpufreq interface */
922 DEVMETHOD(cpufreq_drv_set, est_set),
923 DEVMETHOD(cpufreq_drv_get, est_get),
924 DEVMETHOD(cpufreq_drv_type, est_type),
925 DEVMETHOD(cpufreq_drv_settings, est_settings),
926
927 /* ACPI interface */
928 DEVMETHOD(acpi_get_features, est_features),
929
930 {0, 0}
931};
932
933static driver_t est_driver = {
934 "est",
935 est_methods,
936 sizeof(struct est_softc),
937};
938
939static devclass_t est_devclass;
940DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
941
942static int
943est_features(driver_t *driver, u_int *features)
944{
945
946 /* Notify the ACPI CPU that we support direct access to MSRs */
947 *features = ACPI_CAP_PERF_MSRS;
948 return (0);
949}
950
951static void
952est_identify(driver_t *driver, device_t parent)
953{
954 device_t child;
955
956 /* Make sure we're not being doubly invoked. */
957 if (device_find_child(parent, "est", -1) != NULL)
958 return;
959
960 /* Check that CPUID is supported and the vendor is Intel.*/
961 if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 &&
962 strcmp(cpu_vendor, centaur_id) != 0))
963 return;
964
965 /*
966 * Check if the CPU supports EST.
967 */
968 if (!(cpu_feature2 & CPUID2_EST))
969 return;
970
971 /*
972 * We add a child for each CPU since settings must be performed
973 * on each CPU in the SMP case.
974 */
975 child = BUS_ADD_CHILD(parent, 10, "est", -1);
976 if (child == NULL)
977 device_printf(parent, "add est child failed\n");
978}
979
980static int
981est_probe(device_t dev)
982{
983 device_t perf_dev;
984 uint64_t msr;
985 int error, type;
986
987 if (resource_disabled("est", 0))
988 return (ENXIO);
989
990 /*
991 * If the ACPI perf driver has attached and is not just offering
992 * info, let it manage things.
993 */
994 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
995 if (perf_dev && device_is_attached(perf_dev)) {
996 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
997 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
998 return (ENXIO);
999 }
1000
1001 /* Attempt to enable SpeedStep if not currently enabled. */
1002 msr = rdmsr(MSR_MISC_ENABLE);
1003 if ((msr & MSR_SS_ENABLE) == 0) {
1004 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
1005 if (bootverbose)
1006 device_printf(dev, "enabling SpeedStep\n");
1007
1008 /* Check if the enable failed. */
1009 msr = rdmsr(MSR_MISC_ENABLE);
1010 if ((msr & MSR_SS_ENABLE) == 0) {
1011 device_printf(dev, "failed to enable SpeedStep\n");
1012 return (ENXIO);
1013 }
1014 }
1015
1016 device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
1017 return (0);
1018}
1019
1020static int
1021est_attach(device_t dev)
1022{
1023 struct est_softc *sc;
1024
1025 sc = device_get_softc(dev);
1026 sc->dev = dev;
1027
1028 /* Check CPU for supported settings. */
1029 if (est_get_info(dev))
1030 return (ENXIO);
1031
1032 cpufreq_register(dev);
1033 return (0);
1034}
1035
1036static int
1037est_detach(device_t dev)
1038{
1039 struct est_softc *sc;
1040 int error;
1041
1042 error = cpufreq_unregister(dev);
1043 if (error)
1044 return (error);
1045
1046 sc = device_get_softc(dev);
1047 if (sc->acpi_settings || sc->msr_settings)
1048 free(sc->freq_list, M_DEVBUF);
1049 return (0);
1050}
1051
1052/*
1053 * Probe for supported CPU settings. First, check our static table of
1054 * settings. If no match, try using the ones offered by acpi_perf
1055 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40
1056 * series) export both legacy SMM IO-based access and direct MSR access
1057 * but the direct access specifies invalid values for _PSS.
1058 */
1059static int
1060est_get_info(device_t dev)
1061{
1062 struct est_softc *sc;
1063 uint64_t msr;
1064 int error;
1065
1066 sc = device_get_softc(dev);
1067 msr = rdmsr(MSR_PERF_STATUS);
1068 error = est_table_info(dev, msr, &sc->freq_list);
1069 if (error)
1070 error = est_acpi_info(dev, &sc->freq_list);
1071 if (error)
1072 error = est_msr_info(dev, msr, &sc->freq_list);
1073
1074 if (error) {
1075 printf(
1076 "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
1077 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
1078 return (ENXIO);
1079 }
1080
1081 return (0);
1082}
1083
1084static int
1085est_acpi_info(device_t dev, freq_info **freqs)
1086{
1087 struct est_softc *sc;
1088 struct cf_setting *sets;
1089 freq_info *table;
1090 device_t perf_dev;
1091 int count, error, i, j;
1092 uint16_t saved_id16;
1093
1094 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
1095 if (perf_dev == NULL || !device_is_attached(perf_dev))
1096 return (ENXIO);
1097
1098 /* Fetch settings from acpi_perf. */
1099 sc = device_get_softc(dev);
1100 table = NULL;
1101 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
1102 if (sets == NULL)
1103 return (ENOMEM);
1104 count = MAX_SETTINGS;
1105 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
1106 if (error)
1107 goto out;
1108
1109 /* Parse settings into our local table format. */
1110 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
1111 if (table == NULL) {
1112 error = ENOMEM;
1113 goto out;
1114 }
1115 est_get_id16(&saved_id16);
1116 for (i = 0, j = 0; i < count; i++) {
1117 /*
1118 * Confirm id16 value is correct.
1119 */
1120 if (sets[i].freq > 0) {
1121 error = est_set_id16(dev, sets[i].spec[0], 1);
1122 if (error != 0) {
1123 if (bootverbose)
1124 device_printf(dev, "Invalid freq %u, "
1125 "ignored.\n", sets[i].freq);
1126 } else {
1127 table[j].freq = sets[i].freq;
1128 table[j].volts = sets[i].volts;
1129 table[j].id16 = sets[i].spec[0];
1130 table[j].power = sets[i].power;
1131 ++j;
1132 }
1133 }
1134 }
1135 /* restore saved setting */
1136 est_set_id16(dev, saved_id16, 0);
1137
1138 /* Mark end of table with a terminator. */
1139 bzero(&table[j], sizeof(freq_info));
1140
1141 sc->acpi_settings = TRUE;
1142 *freqs = table;
1143 error = 0;
1144
1145out:
1146 if (sets)
1147 free(sets, M_TEMP);
1148 if (error && table)
1149 free(table, M_DEVBUF);
1150 return (error);
1151}
1152
1153static int
1154est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
1155{
1156 cpu_info *p;
1157 uint32_t id;
1158
1159 /* Find a table which matches (vendor, id32). */
1160 id = msr >> 32;
1161 for (p = ESTprocs; p->id32 != 0; p++) {
1162 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id)
1163 break;
1164 }
1165 if (p->id32 == 0)
1166 return (EOPNOTSUPP);
1167
1168 /* Make sure the current setpoint is valid. */
1169 if (est_get_current(p->freqtab) == NULL) {
1170 device_printf(dev, "current setting not found in table\n");
1171 return (EOPNOTSUPP);
1172 }
1173
1174 *freqs = p->freqtab;
1175 return (0);
1176}
1177
1178static int
1179bus_speed_ok(int bus)
1180{
1181
1182 switch (bus) {
1183 case 100:
1184 case 133:
1185 case 333:
1186 return (1);
1187 default:
1188 return (0);
1189 }
1190}
1191
1192/*
1193 * Flesh out a simple rate table containing the high and low frequencies
1194 * based on the current clock speed and the upper 32 bits of the MSR.
1195 */
1196static int
1197est_msr_info(device_t dev, uint64_t msr, freq_info **freqs)
1198{
1199 struct est_softc *sc;
1200 freq_info *fp;
1201 int bus, freq, volts;
1202 uint16_t id;
1203
1204 if (!msr_info_enabled)
1205 return (EOPNOTSUPP);
1206
1207 /* Figure out the bus clock. */
1208 freq = tsc_freq / 1000000;
1209 id = msr >> 32;
1210 bus = freq / (id >> 8);
1211 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus);
1212 if (!bus_speed_ok(bus)) {
1213 /* We may be running on the low frequency. */
1214 id = msr >> 48;
1215 bus = freq / (id >> 8);
1216 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus);
1217 if (!bus_speed_ok(bus))
1218 return (EOPNOTSUPP);
1219
1220 /* Calculate high frequency. */
1221 id = msr >> 32;
1222 freq = ((id >> 8) & 0xff) * bus;
1223 }
1224
1225 /* Fill out a new freq table containing just the high and low freqs. */
1226 sc = device_get_softc(dev);
1227 fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO);
1228
1229 /* First, the high frequency. */
1230 volts = id & 0xff;
1231 if (volts != 0) {
1232 volts <<= 4;
1233 volts += 700;
1234 }
1235 fp[0].freq = freq;
1236 fp[0].volts = volts;
1237 fp[0].id16 = id;
1238 fp[0].power = CPUFREQ_VAL_UNKNOWN;
1239 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq,
1240 volts);
1241
1242 /* Second, the low frequency. */
1243 id = msr >> 48;
1244 freq = ((id >> 8) & 0xff) * bus;
1245 volts = id & 0xff;
1246 if (volts != 0) {
1247 volts <<= 4;
1248 volts += 700;
1249 }
1250 fp[1].freq = freq;
1251 fp[1].volts = volts;
1252 fp[1].id16 = id;
1253 fp[1].power = CPUFREQ_VAL_UNKNOWN;
1254 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq,
1255 volts);
1256
1257 /* Table is already terminated due to M_ZERO. */
1258 sc->msr_settings = TRUE;
1259 *freqs = fp;
1260 return (0);
1261}
1262
1263static void
1264est_get_id16(uint16_t *id16_p)
1265{
1266 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;
1267}
1268
1269static int
1270est_set_id16(device_t dev, uint16_t id16, int need_check)
1271{
1272 uint64_t msr;
1273 uint16_t new_id16;
1274 int ret = 0;
1275
1276 /* Read the current register, mask out the old, set the new id. */
1277 msr = rdmsr(MSR_PERF_CTL);
1278 msr = (msr & ~0xffff) | id16;
1279 wrmsr(MSR_PERF_CTL, msr);
1280
1281 /* Wait a short while for the new setting. XXX Is this necessary? */
1282 DELAY(EST_TRANS_LAT);
1283
1284 if (need_check) {
1285 est_get_id16(&new_id16);
1286 if (new_id16 != id16) {
1287 if (bootverbose)
1288 device_printf(dev, "Invalid id16 (set, cur) "
1289 "= (%u, %u)\n", id16, new_id16);
1290 ret = ENXIO;
1291 }
1292 }
1293 return (ret);
1294}
1295
1296static freq_info *
1297est_get_current(freq_info *freq_list)
1298{
1299 freq_info *f;
1300 int i;
1301 uint16_t id16;
1302
1303 /*
1304 * Try a few times to get a valid value. Sometimes, if the CPU
1305 * is in the middle of an asynchronous transition (i.e., P4TCC),
1306 * we get a temporary invalid result.
1307 */
1308 for (i = 0; i < 5; i++) {
1309 est_get_id16(&id16);
1310 for (f = freq_list; f->id16 != 0; f++) {
1311 if (f->id16 == id16)
1312 return (f);
1313 }
1314 DELAY(100);
1315 }
1316 return (NULL);
1317}
1318
1319static int
1320est_settings(device_t dev, struct cf_setting *sets, int *count)
1321{
1322 struct est_softc *sc;
1323 freq_info *f;
1324 int i;
1325
1326 sc = device_get_softc(dev);
1327 if (*count < EST_MAX_SETTINGS)
1328 return (E2BIG);
1329
1330 i = 0;
1331 for (f = sc->freq_list; f->freq != 0; f++, i++) {
1332 sets[i].freq = f->freq;
1333 sets[i].volts = f->volts;
1334 sets[i].power = f->power;
1335 sets[i].lat = EST_TRANS_LAT;
1336 sets[i].dev = dev;
1337 }
1338 *count = i;
1339
1340 return (0);
1341}
1342
1343static int
1344est_set(device_t dev, const struct cf_setting *set)
1345{
1346 struct est_softc *sc;
1347 freq_info *f;
1348
1349 /* Find the setting matching the requested one. */
1350 sc = device_get_softc(dev);
1351 for (f = sc->freq_list; f->freq != 0; f++) {
1352 if (f->freq == set->freq)
1353 break;
1354 }
1355 if (f->freq == 0)
1356 return (EINVAL);
1357
1358 /* Read the current register, mask out the old, set the new id. */
1359 est_set_id16(dev, f->id16, 0);
1360
1361 return (0);
1362}
1363
1364static int
1365est_get(device_t dev, struct cf_setting *set)
1366{
1367 struct est_softc *sc;
1368 freq_info *f;
1369
1370 sc = device_get_softc(dev);
1371 f = est_get_current(sc->freq_list);
1372 if (f == NULL)
1373 return (ENXIO);
1374
1375 set->freq = f->freq;
1376 set->volts = f->volts;
1377 set->power = f->power;
1378 set->lat = EST_TRANS_LAT;
1379 set->dev = dev;
1380 return (0);
1381}
1382
1383static int
1384est_type(device_t dev, int *type)
1385{
1386
1387 if (type == NULL)
1388 return (EINVAL);
1389
1390 *type = CPUFREQ_TYPE_ABSOLUTE;
1391 return (0);
1392}
2 * Copyright (c) 2004 Colin Percival
3 * Copyright (c) 2005 Nate Lawson
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted providing that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 182908 2008-09-10 17:41:41Z jhb $");
30
31#include <sys/param.h>
32#include <sys/bus.h>
33#include <sys/cpu.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/smp.h>
38#include <sys/systm.h>
39
40#include "cpufreq_if.h"
41#include <machine/clock.h>
42#include <machine/md_var.h>
43#include <machine/specialreg.h>
44
45#include <contrib/dev/acpica/acpi.h>
46#include <dev/acpica/acpivar.h>
47#include "acpi_if.h"
48
49/* Status/control registers (from the IA-32 System Programming Guide). */
50#define MSR_PERF_STATUS 0x198
51#define MSR_PERF_CTL 0x199
52
53/* Register and bit for enabling SpeedStep. */
54#define MSR_MISC_ENABLE 0x1a0
55#define MSR_SS_ENABLE (1<<16)
56
57/* Frequency and MSR control values. */
58typedef struct {
59 uint16_t freq;
60 uint16_t volts;
61 uint16_t id16;
62 int power;
63} freq_info;
64
65/* Identifying characteristics of a processor and supported frequencies. */
66typedef struct {
67 const char *vendor;
68 uint32_t id32;
69 freq_info *freqtab;
70} cpu_info;
71
72struct est_softc {
73 device_t dev;
74 int acpi_settings;
75 int msr_settings;
76 freq_info *freq_list;
77};
78
79/* Convert MHz and mV into IDs for passing to the MSR. */
80#define ID16(MHz, mV, bus_clk) \
81 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
82#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
83 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
84
85/* Format for storing IDs in our table. */
86#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \
87 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
88#define FREQ_INFO(MHz, mV, bus_clk) \
89 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
90#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
91 { intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
92#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
93 { centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
94
95const char intel_id[] = "GenuineIntel";
96const char centaur_id[] = "CentaurHauls";
97static int msr_info_enabled = 0;
98TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
99
100/* Default bus clock value for Centrino processors. */
101#define INTEL_BUS_CLK 100
102
103/* XXX Update this if new CPUs have more settings. */
104#define EST_MAX_SETTINGS 10
105CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
106
107/* Estimate in microseconds of latency for performing a transition. */
108#define EST_TRANS_LAT 1000
109
110/*
111 * Frequency (MHz) and voltage (mV) settings. Data from the
112 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
113 *
114 * Dothan processors have multiple VID#s with different settings for
115 * each VID#. Since we can't uniquely identify this info
116 * without undisclosed methods from Intel, we can't support newer
117 * processors with this table method. If ACPI Px states are supported,
118 * we get info from them.
119 */
120static freq_info PM17_130[] = {
121 /* 130nm 1.70GHz Pentium M */
122 FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
123 FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
124 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
125 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
126 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
127 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
128 FREQ_INFO( 0, 0, 1),
129};
130static freq_info PM16_130[] = {
131 /* 130nm 1.60GHz Pentium M */
132 FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
133 FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
134 FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
135 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
136 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
137 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
138 FREQ_INFO( 0, 0, 1),
139};
140static freq_info PM15_130[] = {
141 /* 130nm 1.50GHz Pentium M */
142 FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
143 FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
144 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
145 FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
146 FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
147 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
148 FREQ_INFO( 0, 0, 1),
149};
150static freq_info PM14_130[] = {
151 /* 130nm 1.40GHz Pentium M */
152 FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
153 FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
154 FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
155 FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
156 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
157 FREQ_INFO( 0, 0, 1),
158};
159static freq_info PM13_130[] = {
160 /* 130nm 1.30GHz Pentium M */
161 FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
162 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
163 FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
164 FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
165 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
166 FREQ_INFO( 0, 0, 1),
167};
168static freq_info PM13_LV_130[] = {
169 /* 130nm 1.30GHz Low Voltage Pentium M */
170 FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
171 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
172 FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
173 FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
174 FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
175 FREQ_INFO( 800, 988, INTEL_BUS_CLK),
176 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
177 FREQ_INFO( 0, 0, 1),
178};
179static freq_info PM12_LV_130[] = {
180 /* 130 nm 1.20GHz Low Voltage Pentium M */
181 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
182 FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
183 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
184 FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
185 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
186 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
187 FREQ_INFO( 0, 0, 1),
188};
189static freq_info PM11_LV_130[] = {
190 /* 130 nm 1.10GHz Low Voltage Pentium M */
191 FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
192 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
193 FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
194 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
195 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
196 FREQ_INFO( 0, 0, 1),
197};
198static freq_info PM11_ULV_130[] = {
199 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
200 FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
201 FREQ_INFO(1000, 988, INTEL_BUS_CLK),
202 FREQ_INFO( 900, 972, INTEL_BUS_CLK),
203 FREQ_INFO( 800, 956, INTEL_BUS_CLK),
204 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
205 FREQ_INFO( 0, 0, 1),
206};
207static freq_info PM10_ULV_130[] = {
208 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
209 FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
210 FREQ_INFO( 900, 988, INTEL_BUS_CLK),
211 FREQ_INFO( 800, 972, INTEL_BUS_CLK),
212 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
213 FREQ_INFO( 0, 0, 1),
214};
215
216/*
217 * Data from "Intel Pentium M Processor on 90nm Process with
218 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
219 */
220static freq_info PM_765A_90[] = {
221 /* 90 nm 2.10GHz Pentium M, VID #A */
222 FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
223 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
224 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
225 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
226 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
227 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
228 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
229 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
230 FREQ_INFO( 0, 0, 1),
231};
232static freq_info PM_765B_90[] = {
233 /* 90 nm 2.10GHz Pentium M, VID #B */
234 FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
235 FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
236 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
237 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
238 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
239 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
240 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
241 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
242 FREQ_INFO( 0, 0, 1),
243};
244static freq_info PM_765C_90[] = {
245 /* 90 nm 2.10GHz Pentium M, VID #C */
246 FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
247 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
248 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
249 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
250 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
251 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
252 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
253 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
254 FREQ_INFO( 0, 0, 1),
255};
256static freq_info PM_765E_90[] = {
257 /* 90 nm 2.10GHz Pentium M, VID #E */
258 FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
259 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
260 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
261 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
262 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
263 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
264 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
265 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
266 FREQ_INFO( 0, 0, 1),
267};
268static freq_info PM_755A_90[] = {
269 /* 90 nm 2.00GHz Pentium M, VID #A */
270 FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
271 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
272 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
273 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
274 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
275 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
276 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
277 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
278 FREQ_INFO( 0, 0, 1),
279};
280static freq_info PM_755B_90[] = {
281 /* 90 nm 2.00GHz Pentium M, VID #B */
282 FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
283 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
284 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
285 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
286 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
287 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
288 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
289 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
290 FREQ_INFO( 0, 0, 1),
291};
292static freq_info PM_755C_90[] = {
293 /* 90 nm 2.00GHz Pentium M, VID #C */
294 FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
295 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
296 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
297 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
298 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
299 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
300 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
301 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
302 FREQ_INFO( 0, 0, 1),
303};
304static freq_info PM_755D_90[] = {
305 /* 90 nm 2.00GHz Pentium M, VID #D */
306 FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
307 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
308 FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
309 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
310 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
311 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
312 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
313 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
314 FREQ_INFO( 0, 0, 1),
315};
316static freq_info PM_745A_90[] = {
317 /* 90 nm 1.80GHz Pentium M, VID #A */
318 FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
319 FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
320 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
321 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
322 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
323 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
324 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
325 FREQ_INFO( 0, 0, 1),
326};
327static freq_info PM_745B_90[] = {
328 /* 90 nm 1.80GHz Pentium M, VID #B */
329 FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
330 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
331 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
332 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
333 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
334 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
335 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
336 FREQ_INFO( 0, 0, 1),
337};
338static freq_info PM_745C_90[] = {
339 /* 90 nm 1.80GHz Pentium M, VID #C */
340 FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
341 FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
342 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
343 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
344 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
345 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
346 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
347 FREQ_INFO( 0, 0, 1),
348};
349static freq_info PM_745D_90[] = {
350 /* 90 nm 1.80GHz Pentium M, VID #D */
351 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
352 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
353 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
354 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
355 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
356 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
357 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
358 FREQ_INFO( 0, 0, 1),
359};
360static freq_info PM_735A_90[] = {
361 /* 90 nm 1.70GHz Pentium M, VID #A */
362 FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
363 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
364 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
365 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
366 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
367 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
368 FREQ_INFO( 0, 0, 1),
369};
370static freq_info PM_735B_90[] = {
371 /* 90 nm 1.70GHz Pentium M, VID #B */
372 FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
373 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
374 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
375 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
376 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
377 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
378 FREQ_INFO( 0, 0, 1),
379};
380static freq_info PM_735C_90[] = {
381 /* 90 nm 1.70GHz Pentium M, VID #C */
382 FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
383 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
384 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
385 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
386 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
387 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
388 FREQ_INFO( 0, 0, 1),
389};
390static freq_info PM_735D_90[] = {
391 /* 90 nm 1.70GHz Pentium M, VID #D */
392 FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
393 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
394 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
395 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
396 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
397 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
398 FREQ_INFO( 0, 0, 1),
399};
400static freq_info PM_725A_90[] = {
401 /* 90 nm 1.60GHz Pentium M, VID #A */
402 FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
403 FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
404 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
405 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
406 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
407 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
408 FREQ_INFO( 0, 0, 1),
409};
410static freq_info PM_725B_90[] = {
411 /* 90 nm 1.60GHz Pentium M, VID #B */
412 FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
413 FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
414 FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
415 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
416 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
417 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
418 FREQ_INFO( 0, 0, 1),
419};
420static freq_info PM_725C_90[] = {
421 /* 90 nm 1.60GHz Pentium M, VID #C */
422 FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
423 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
424 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
425 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
426 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
427 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
428 FREQ_INFO( 0, 0, 1),
429};
430static freq_info PM_725D_90[] = {
431 /* 90 nm 1.60GHz Pentium M, VID #D */
432 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
433 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
434 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
435 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
436 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
437 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
438 FREQ_INFO( 0, 0, 1),
439};
440static freq_info PM_715A_90[] = {
441 /* 90 nm 1.50GHz Pentium M, VID #A */
442 FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
443 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
444 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
445 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
446 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
447 FREQ_INFO( 0, 0, 1),
448};
449static freq_info PM_715B_90[] = {
450 /* 90 nm 1.50GHz Pentium M, VID #B */
451 FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
452 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
453 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
454 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
455 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
456 FREQ_INFO( 0, 0, 1),
457};
458static freq_info PM_715C_90[] = {
459 /* 90 nm 1.50GHz Pentium M, VID #C */
460 FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
461 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
462 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
463 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
464 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
465 FREQ_INFO( 0, 0, 1),
466};
467static freq_info PM_715D_90[] = {
468 /* 90 nm 1.50GHz Pentium M, VID #D */
469 FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
470 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
471 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
472 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
473 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
474 FREQ_INFO( 0, 0, 1),
475};
476static freq_info PM_778_90[] = {
477 /* 90 nm 1.60GHz Low Voltage Pentium M */
478 FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
479 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
480 FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
481 FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
482 FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
483 FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
484 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
485 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
486 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
487 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
488 FREQ_INFO( 0, 0, 1),
489};
490static freq_info PM_758_90[] = {
491 /* 90 nm 1.50GHz Low Voltage Pentium M */
492 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
493 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
494 FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
495 FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
496 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
497 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
498 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
499 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
500 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
501 FREQ_INFO( 0, 0, 1),
502};
503static freq_info PM_738_90[] = {
504 /* 90 nm 1.40GHz Low Voltage Pentium M */
505 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
506 FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
507 FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
508 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
509 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
510 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
511 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
512 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
513 FREQ_INFO( 0, 0, 1),
514};
515static freq_info PM_773G_90[] = {
516 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
517 FREQ_INFO(1300, 956, INTEL_BUS_CLK),
518 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
519 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
520 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
521 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
522 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
523 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
524};
525static freq_info PM_773H_90[] = {
526 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
527 FREQ_INFO(1300, 940, INTEL_BUS_CLK),
528 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
529 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
530 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
531 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
532 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
533 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
534};
535static freq_info PM_773I_90[] = {
536 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
537 FREQ_INFO(1300, 924, INTEL_BUS_CLK),
538 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
539 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
540 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
541 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
542 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
543 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
544};
545static freq_info PM_773J_90[] = {
546 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
547 FREQ_INFO(1300, 908, INTEL_BUS_CLK),
548 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
549 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
550 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
551 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
552 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
553 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
554};
555static freq_info PM_773K_90[] = {
556 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
557 FREQ_INFO(1300, 892, INTEL_BUS_CLK),
558 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
559 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
560 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
561 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
562 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
563 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
564};
565static freq_info PM_773L_90[] = {
566 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
567 FREQ_INFO(1300, 876, INTEL_BUS_CLK),
568 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
569 FREQ_INFO(1100, 860, INTEL_BUS_CLK),
570 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
571 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
572 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
573 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
574};
575static freq_info PM_753G_90[] = {
576 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
577 FREQ_INFO(1200, 956, INTEL_BUS_CLK),
578 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
579 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
580 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
581 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
582 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
583};
584static freq_info PM_753H_90[] = {
585 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
586 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
587 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
588 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
589 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
590 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
591 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
592};
593static freq_info PM_753I_90[] = {
594 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
595 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
596 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
597 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
598 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
599 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
600 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
601};
602static freq_info PM_753J_90[] = {
603 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
604 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
605 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
606 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
607 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
608 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
609 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
610};
611static freq_info PM_753K_90[] = {
612 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
613 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
614 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
615 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
616 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
617 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
618 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
619};
620static freq_info PM_753L_90[] = {
621 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
622 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
623 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
624 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
625 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
626 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
627 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
628};
629
630static freq_info PM_733JG_90[] = {
631 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
632 FREQ_INFO(1100, 956, INTEL_BUS_CLK),
633 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
634 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
635 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
636 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
637};
638static freq_info PM_733JH_90[] = {
639 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
640 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
641 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
642 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
643 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
644 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
645};
646static freq_info PM_733JI_90[] = {
647 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
648 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
649 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
650 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
651 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
652 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
653};
654static freq_info PM_733JJ_90[] = {
655 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
656 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
657 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
658 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
659 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
660 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
661};
662static freq_info PM_733JK_90[] = {
663 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
664 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
665 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
666 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
667 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
668 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
669};
670static freq_info PM_733JL_90[] = {
671 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
672 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
673 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
674 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
675 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
676 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
677};
678static freq_info PM_733_90[] = {
679 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
680 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
681 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
682 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
683 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
684 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
685 FREQ_INFO( 0, 0, 1),
686};
687static freq_info PM_723_90[] = {
688 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
689 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
690 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
691 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
692 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
693 FREQ_INFO( 0, 0, 1),
694};
695
696/*
697 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
698 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
699 */
700static freq_info C7M_795[] = {
701 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
702 FREQ_INFO_PWR(2000, 1148, 133, 20000),
703 FREQ_INFO_PWR(1867, 1132, 133, 18000),
704 FREQ_INFO_PWR(1600, 1100, 133, 15000),
705 FREQ_INFO_PWR(1467, 1052, 133, 13000),
706 FREQ_INFO_PWR(1200, 1004, 133, 10000),
707 FREQ_INFO_PWR( 800, 844, 133, 7000),
708 FREQ_INFO_PWR( 667, 844, 133, 6000),
709 FREQ_INFO_PWR( 533, 844, 133, 5000),
710 FREQ_INFO(0, 0, 1),
711};
712static freq_info C7M_785[] = {
713 /* 1.80GHz Centaur C7-M 533 Mhz FSB */
714 FREQ_INFO_PWR(1867, 1148, 133, 18000),
715 FREQ_INFO_PWR(1600, 1100, 133, 15000),
716 FREQ_INFO_PWR(1467, 1052, 133, 13000),
717 FREQ_INFO_PWR(1200, 1004, 133, 10000),
718 FREQ_INFO_PWR( 800, 844, 133, 7000),
719 FREQ_INFO_PWR( 667, 844, 133, 6000),
720 FREQ_INFO_PWR( 533, 844, 133, 5000),
721 FREQ_INFO(0, 0, 1),
722};
723static freq_info C7M_765[] = {
724 /* 1.60GHz Centaur C7-M 533 Mhz FSB */
725 FREQ_INFO_PWR(1600, 1084, 133, 15000),
726 FREQ_INFO_PWR(1467, 1052, 133, 13000),
727 FREQ_INFO_PWR(1200, 1004, 133, 10000),
728 FREQ_INFO_PWR( 800, 844, 133, 7000),
729 FREQ_INFO_PWR( 667, 844, 133, 6000),
730 FREQ_INFO_PWR( 533, 844, 133, 5000),
731 FREQ_INFO(0, 0, 1),
732};
733
734static freq_info C7M_794[] = {
735 /* 2.00GHz Centaur C7-M 400 Mhz FSB */
736 FREQ_INFO_PWR(2000, 1148, 100, 20000),
737 FREQ_INFO_PWR(1800, 1132, 100, 18000),
738 FREQ_INFO_PWR(1600, 1100, 100, 15000),
739 FREQ_INFO_PWR(1400, 1052, 100, 13000),
740 FREQ_INFO_PWR(1000, 1004, 100, 10000),
741 FREQ_INFO_PWR( 800, 844, 100, 7000),
742 FREQ_INFO_PWR( 600, 844, 100, 6000),
743 FREQ_INFO_PWR( 400, 844, 100, 5000),
744 FREQ_INFO(0, 0, 1),
745};
746static freq_info C7M_784[] = {
747 /* 1.80GHz Centaur C7-M 400 Mhz FSB */
748 FREQ_INFO_PWR(1800, 1148, 100, 18000),
749 FREQ_INFO_PWR(1600, 1100, 100, 15000),
750 FREQ_INFO_PWR(1400, 1052, 100, 13000),
751 FREQ_INFO_PWR(1000, 1004, 100, 10000),
752 FREQ_INFO_PWR( 800, 844, 100, 7000),
753 FREQ_INFO_PWR( 600, 844, 100, 6000),
754 FREQ_INFO_PWR( 400, 844, 100, 5000),
755 FREQ_INFO(0, 0, 1),
756};
757static freq_info C7M_764[] = {
758 /* 1.60GHz Centaur C7-M 400 Mhz FSB */
759 FREQ_INFO_PWR(1600, 1084, 100, 15000),
760 FREQ_INFO_PWR(1400, 1052, 100, 13000),
761 FREQ_INFO_PWR(1000, 1004, 100, 10000),
762 FREQ_INFO_PWR( 800, 844, 100, 7000),
763 FREQ_INFO_PWR( 600, 844, 100, 6000),
764 FREQ_INFO_PWR( 400, 844, 100, 5000),
765 FREQ_INFO(0, 0, 1),
766};
767static freq_info C7M_754[] = {
768 /* 1.50GHz Centaur C7-M 400 Mhz FSB */
769 FREQ_INFO_PWR(1500, 1004, 100, 12000),
770 FREQ_INFO_PWR(1400, 988, 100, 11000),
771 FREQ_INFO_PWR(1000, 940, 100, 9000),
772 FREQ_INFO_PWR( 800, 844, 100, 7000),
773 FREQ_INFO_PWR( 600, 844, 100, 6000),
774 FREQ_INFO_PWR( 400, 844, 100, 5000),
775 FREQ_INFO(0, 0, 1),
776};
777static freq_info C7M_771[] = {
778 /* 1.20GHz Centaur C7-M 400 Mhz FSB */
779 FREQ_INFO_PWR(1200, 860, 100, 7000),
780 FREQ_INFO_PWR(1000, 860, 100, 6000),
781 FREQ_INFO_PWR( 800, 844, 100, 5500),
782 FREQ_INFO_PWR( 600, 844, 100, 5000),
783 FREQ_INFO_PWR( 400, 844, 100, 4000),
784 FREQ_INFO(0, 0, 1),
785};
786
787static freq_info C7M_775_ULV[] = {
788 /* 1.50GHz Centaur C7-M ULV */
789 FREQ_INFO_PWR(1500, 956, 100, 7500),
790 FREQ_INFO_PWR(1400, 940, 100, 6000),
791 FREQ_INFO_PWR(1000, 860, 100, 5000),
792 FREQ_INFO_PWR( 800, 828, 100, 2800),
793 FREQ_INFO_PWR( 600, 796, 100, 2500),
794 FREQ_INFO_PWR( 400, 796, 100, 2000),
795 FREQ_INFO(0, 0, 1),
796};
797static freq_info C7M_772_ULV[] = {
798 /* 1.20GHz Centaur C7-M ULV */
799 FREQ_INFO_PWR(1200, 844, 100, 5000),
800 FREQ_INFO_PWR(1000, 844, 100, 4000),
801 FREQ_INFO_PWR( 800, 828, 100, 2800),
802 FREQ_INFO_PWR( 600, 796, 100, 2500),
803 FREQ_INFO_PWR( 400, 796, 100, 2000),
804 FREQ_INFO(0, 0, 1),
805};
806static freq_info C7M_779_ULV[] = {
807 /* 1.00GHz Centaur C7-M ULV */
808 FREQ_INFO_PWR(1000, 796, 100, 3500),
809 FREQ_INFO_PWR( 800, 796, 100, 2800),
810 FREQ_INFO_PWR( 600, 796, 100, 2500),
811 FREQ_INFO_PWR( 400, 796, 100, 2000),
812 FREQ_INFO(0, 0, 1),
813};
814static freq_info C7M_770_ULV[] = {
815 /* 1.00GHz Centaur C7-M ULV */
816 FREQ_INFO_PWR(1000, 844, 100, 5000),
817 FREQ_INFO_PWR( 800, 796, 100, 2800),
818 FREQ_INFO_PWR( 600, 796, 100, 2500),
819 FREQ_INFO_PWR( 400, 796, 100, 2000),
820 FREQ_INFO(0, 0, 1),
821};
822
823static cpu_info ESTprocs[] = {
824 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
825 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
826 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
827 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
828 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
829 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
830 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),
831 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK),
832 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK),
833 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK),
834 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK),
835 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK),
836 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK),
837 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK),
838 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK),
839 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK),
840 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK),
841 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK),
842 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK),
843 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK),
844 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK),
845 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK),
846 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK),
847 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK),
848 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK),
849 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK),
850 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK),
851 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK),
852 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK),
853 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK),
854 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK),
855 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK),
856 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK),
857 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK),
858 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK),
859 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK),
860 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK),
861 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK),
862 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK),
863 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK),
864 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK),
865 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK),
866 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK),
867 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK),
868 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK),
869 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK),
870 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK),
871 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK),
872 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK),
873 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
874 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
875 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
876 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
877 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
878 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
879 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
880 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
881
882 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133),
883 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
884 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133),
885 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
886 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133),
887 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
888 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
889 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
890 CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
891 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
892 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
893 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
894 { NULL, 0, NULL },
895};
896
897static void est_identify(driver_t *driver, device_t parent);
898static int est_features(driver_t *driver, u_int *features);
899static int est_probe(device_t parent);
900static int est_attach(device_t parent);
901static int est_detach(device_t parent);
902static int est_get_info(device_t dev);
903static int est_acpi_info(device_t dev, freq_info **freqs);
904static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
905static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
906static freq_info *est_get_current(freq_info *freq_list);
907static int est_settings(device_t dev, struct cf_setting *sets, int *count);
908static int est_set(device_t dev, const struct cf_setting *set);
909static int est_get(device_t dev, struct cf_setting *set);
910static int est_type(device_t dev, int *type);
911static int est_set_id16(device_t dev, uint16_t id16, int need_check);
912static void est_get_id16(uint16_t *id16_p);
913
914static device_method_t est_methods[] = {
915 /* Device interface */
916 DEVMETHOD(device_identify, est_identify),
917 DEVMETHOD(device_probe, est_probe),
918 DEVMETHOD(device_attach, est_attach),
919 DEVMETHOD(device_detach, est_detach),
920
921 /* cpufreq interface */
922 DEVMETHOD(cpufreq_drv_set, est_set),
923 DEVMETHOD(cpufreq_drv_get, est_get),
924 DEVMETHOD(cpufreq_drv_type, est_type),
925 DEVMETHOD(cpufreq_drv_settings, est_settings),
926
927 /* ACPI interface */
928 DEVMETHOD(acpi_get_features, est_features),
929
930 {0, 0}
931};
932
933static driver_t est_driver = {
934 "est",
935 est_methods,
936 sizeof(struct est_softc),
937};
938
939static devclass_t est_devclass;
940DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
941
942static int
943est_features(driver_t *driver, u_int *features)
944{
945
946 /* Notify the ACPI CPU that we support direct access to MSRs */
947 *features = ACPI_CAP_PERF_MSRS;
948 return (0);
949}
950
951static void
952est_identify(driver_t *driver, device_t parent)
953{
954 device_t child;
955
956 /* Make sure we're not being doubly invoked. */
957 if (device_find_child(parent, "est", -1) != NULL)
958 return;
959
960 /* Check that CPUID is supported and the vendor is Intel.*/
961 if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 &&
962 strcmp(cpu_vendor, centaur_id) != 0))
963 return;
964
965 /*
966 * Check if the CPU supports EST.
967 */
968 if (!(cpu_feature2 & CPUID2_EST))
969 return;
970
971 /*
972 * We add a child for each CPU since settings must be performed
973 * on each CPU in the SMP case.
974 */
975 child = BUS_ADD_CHILD(parent, 10, "est", -1);
976 if (child == NULL)
977 device_printf(parent, "add est child failed\n");
978}
979
980static int
981est_probe(device_t dev)
982{
983 device_t perf_dev;
984 uint64_t msr;
985 int error, type;
986
987 if (resource_disabled("est", 0))
988 return (ENXIO);
989
990 /*
991 * If the ACPI perf driver has attached and is not just offering
992 * info, let it manage things.
993 */
994 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
995 if (perf_dev && device_is_attached(perf_dev)) {
996 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
997 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
998 return (ENXIO);
999 }
1000
1001 /* Attempt to enable SpeedStep if not currently enabled. */
1002 msr = rdmsr(MSR_MISC_ENABLE);
1003 if ((msr & MSR_SS_ENABLE) == 0) {
1004 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
1005 if (bootverbose)
1006 device_printf(dev, "enabling SpeedStep\n");
1007
1008 /* Check if the enable failed. */
1009 msr = rdmsr(MSR_MISC_ENABLE);
1010 if ((msr & MSR_SS_ENABLE) == 0) {
1011 device_printf(dev, "failed to enable SpeedStep\n");
1012 return (ENXIO);
1013 }
1014 }
1015
1016 device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
1017 return (0);
1018}
1019
1020static int
1021est_attach(device_t dev)
1022{
1023 struct est_softc *sc;
1024
1025 sc = device_get_softc(dev);
1026 sc->dev = dev;
1027
1028 /* Check CPU for supported settings. */
1029 if (est_get_info(dev))
1030 return (ENXIO);
1031
1032 cpufreq_register(dev);
1033 return (0);
1034}
1035
1036static int
1037est_detach(device_t dev)
1038{
1039 struct est_softc *sc;
1040 int error;
1041
1042 error = cpufreq_unregister(dev);
1043 if (error)
1044 return (error);
1045
1046 sc = device_get_softc(dev);
1047 if (sc->acpi_settings || sc->msr_settings)
1048 free(sc->freq_list, M_DEVBUF);
1049 return (0);
1050}
1051
1052/*
1053 * Probe for supported CPU settings. First, check our static table of
1054 * settings. If no match, try using the ones offered by acpi_perf
1055 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40
1056 * series) export both legacy SMM IO-based access and direct MSR access
1057 * but the direct access specifies invalid values for _PSS.
1058 */
1059static int
1060est_get_info(device_t dev)
1061{
1062 struct est_softc *sc;
1063 uint64_t msr;
1064 int error;
1065
1066 sc = device_get_softc(dev);
1067 msr = rdmsr(MSR_PERF_STATUS);
1068 error = est_table_info(dev, msr, &sc->freq_list);
1069 if (error)
1070 error = est_acpi_info(dev, &sc->freq_list);
1071 if (error)
1072 error = est_msr_info(dev, msr, &sc->freq_list);
1073
1074 if (error) {
1075 printf(
1076 "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
1077 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
1078 return (ENXIO);
1079 }
1080
1081 return (0);
1082}
1083
1084static int
1085est_acpi_info(device_t dev, freq_info **freqs)
1086{
1087 struct est_softc *sc;
1088 struct cf_setting *sets;
1089 freq_info *table;
1090 device_t perf_dev;
1091 int count, error, i, j;
1092 uint16_t saved_id16;
1093
1094 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
1095 if (perf_dev == NULL || !device_is_attached(perf_dev))
1096 return (ENXIO);
1097
1098 /* Fetch settings from acpi_perf. */
1099 sc = device_get_softc(dev);
1100 table = NULL;
1101 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
1102 if (sets == NULL)
1103 return (ENOMEM);
1104 count = MAX_SETTINGS;
1105 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
1106 if (error)
1107 goto out;
1108
1109 /* Parse settings into our local table format. */
1110 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
1111 if (table == NULL) {
1112 error = ENOMEM;
1113 goto out;
1114 }
1115 est_get_id16(&saved_id16);
1116 for (i = 0, j = 0; i < count; i++) {
1117 /*
1118 * Confirm id16 value is correct.
1119 */
1120 if (sets[i].freq > 0) {
1121 error = est_set_id16(dev, sets[i].spec[0], 1);
1122 if (error != 0) {
1123 if (bootverbose)
1124 device_printf(dev, "Invalid freq %u, "
1125 "ignored.\n", sets[i].freq);
1126 } else {
1127 table[j].freq = sets[i].freq;
1128 table[j].volts = sets[i].volts;
1129 table[j].id16 = sets[i].spec[0];
1130 table[j].power = sets[i].power;
1131 ++j;
1132 }
1133 }
1134 }
1135 /* restore saved setting */
1136 est_set_id16(dev, saved_id16, 0);
1137
1138 /* Mark end of table with a terminator. */
1139 bzero(&table[j], sizeof(freq_info));
1140
1141 sc->acpi_settings = TRUE;
1142 *freqs = table;
1143 error = 0;
1144
1145out:
1146 if (sets)
1147 free(sets, M_TEMP);
1148 if (error && table)
1149 free(table, M_DEVBUF);
1150 return (error);
1151}
1152
1153static int
1154est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
1155{
1156 cpu_info *p;
1157 uint32_t id;
1158
1159 /* Find a table which matches (vendor, id32). */
1160 id = msr >> 32;
1161 for (p = ESTprocs; p->id32 != 0; p++) {
1162 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id)
1163 break;
1164 }
1165 if (p->id32 == 0)
1166 return (EOPNOTSUPP);
1167
1168 /* Make sure the current setpoint is valid. */
1169 if (est_get_current(p->freqtab) == NULL) {
1170 device_printf(dev, "current setting not found in table\n");
1171 return (EOPNOTSUPP);
1172 }
1173
1174 *freqs = p->freqtab;
1175 return (0);
1176}
1177
1178static int
1179bus_speed_ok(int bus)
1180{
1181
1182 switch (bus) {
1183 case 100:
1184 case 133:
1185 case 333:
1186 return (1);
1187 default:
1188 return (0);
1189 }
1190}
1191
1192/*
1193 * Flesh out a simple rate table containing the high and low frequencies
1194 * based on the current clock speed and the upper 32 bits of the MSR.
1195 */
1196static int
1197est_msr_info(device_t dev, uint64_t msr, freq_info **freqs)
1198{
1199 struct est_softc *sc;
1200 freq_info *fp;
1201 int bus, freq, volts;
1202 uint16_t id;
1203
1204 if (!msr_info_enabled)
1205 return (EOPNOTSUPP);
1206
1207 /* Figure out the bus clock. */
1208 freq = tsc_freq / 1000000;
1209 id = msr >> 32;
1210 bus = freq / (id >> 8);
1211 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus);
1212 if (!bus_speed_ok(bus)) {
1213 /* We may be running on the low frequency. */
1214 id = msr >> 48;
1215 bus = freq / (id >> 8);
1216 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus);
1217 if (!bus_speed_ok(bus))
1218 return (EOPNOTSUPP);
1219
1220 /* Calculate high frequency. */
1221 id = msr >> 32;
1222 freq = ((id >> 8) & 0xff) * bus;
1223 }
1224
1225 /* Fill out a new freq table containing just the high and low freqs. */
1226 sc = device_get_softc(dev);
1227 fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO);
1228
1229 /* First, the high frequency. */
1230 volts = id & 0xff;
1231 if (volts != 0) {
1232 volts <<= 4;
1233 volts += 700;
1234 }
1235 fp[0].freq = freq;
1236 fp[0].volts = volts;
1237 fp[0].id16 = id;
1238 fp[0].power = CPUFREQ_VAL_UNKNOWN;
1239 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq,
1240 volts);
1241
1242 /* Second, the low frequency. */
1243 id = msr >> 48;
1244 freq = ((id >> 8) & 0xff) * bus;
1245 volts = id & 0xff;
1246 if (volts != 0) {
1247 volts <<= 4;
1248 volts += 700;
1249 }
1250 fp[1].freq = freq;
1251 fp[1].volts = volts;
1252 fp[1].id16 = id;
1253 fp[1].power = CPUFREQ_VAL_UNKNOWN;
1254 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq,
1255 volts);
1256
1257 /* Table is already terminated due to M_ZERO. */
1258 sc->msr_settings = TRUE;
1259 *freqs = fp;
1260 return (0);
1261}
1262
1263static void
1264est_get_id16(uint16_t *id16_p)
1265{
1266 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;
1267}
1268
1269static int
1270est_set_id16(device_t dev, uint16_t id16, int need_check)
1271{
1272 uint64_t msr;
1273 uint16_t new_id16;
1274 int ret = 0;
1275
1276 /* Read the current register, mask out the old, set the new id. */
1277 msr = rdmsr(MSR_PERF_CTL);
1278 msr = (msr & ~0xffff) | id16;
1279 wrmsr(MSR_PERF_CTL, msr);
1280
1281 /* Wait a short while for the new setting. XXX Is this necessary? */
1282 DELAY(EST_TRANS_LAT);
1283
1284 if (need_check) {
1285 est_get_id16(&new_id16);
1286 if (new_id16 != id16) {
1287 if (bootverbose)
1288 device_printf(dev, "Invalid id16 (set, cur) "
1289 "= (%u, %u)\n", id16, new_id16);
1290 ret = ENXIO;
1291 }
1292 }
1293 return (ret);
1294}
1295
1296static freq_info *
1297est_get_current(freq_info *freq_list)
1298{
1299 freq_info *f;
1300 int i;
1301 uint16_t id16;
1302
1303 /*
1304 * Try a few times to get a valid value. Sometimes, if the CPU
1305 * is in the middle of an asynchronous transition (i.e., P4TCC),
1306 * we get a temporary invalid result.
1307 */
1308 for (i = 0; i < 5; i++) {
1309 est_get_id16(&id16);
1310 for (f = freq_list; f->id16 != 0; f++) {
1311 if (f->id16 == id16)
1312 return (f);
1313 }
1314 DELAY(100);
1315 }
1316 return (NULL);
1317}
1318
1319static int
1320est_settings(device_t dev, struct cf_setting *sets, int *count)
1321{
1322 struct est_softc *sc;
1323 freq_info *f;
1324 int i;
1325
1326 sc = device_get_softc(dev);
1327 if (*count < EST_MAX_SETTINGS)
1328 return (E2BIG);
1329
1330 i = 0;
1331 for (f = sc->freq_list; f->freq != 0; f++, i++) {
1332 sets[i].freq = f->freq;
1333 sets[i].volts = f->volts;
1334 sets[i].power = f->power;
1335 sets[i].lat = EST_TRANS_LAT;
1336 sets[i].dev = dev;
1337 }
1338 *count = i;
1339
1340 return (0);
1341}
1342
1343static int
1344est_set(device_t dev, const struct cf_setting *set)
1345{
1346 struct est_softc *sc;
1347 freq_info *f;
1348
1349 /* Find the setting matching the requested one. */
1350 sc = device_get_softc(dev);
1351 for (f = sc->freq_list; f->freq != 0; f++) {
1352 if (f->freq == set->freq)
1353 break;
1354 }
1355 if (f->freq == 0)
1356 return (EINVAL);
1357
1358 /* Read the current register, mask out the old, set the new id. */
1359 est_set_id16(dev, f->id16, 0);
1360
1361 return (0);
1362}
1363
1364static int
1365est_get(device_t dev, struct cf_setting *set)
1366{
1367 struct est_softc *sc;
1368 freq_info *f;
1369
1370 sc = device_get_softc(dev);
1371 f = est_get_current(sc->freq_list);
1372 if (f == NULL)
1373 return (ENXIO);
1374
1375 set->freq = f->freq;
1376 set->volts = f->volts;
1377 set->power = f->power;
1378 set->lat = EST_TRANS_LAT;
1379 set->dev = dev;
1380 return (0);
1381}
1382
1383static int
1384est_type(device_t dev, int *type)
1385{
1386
1387 if (type == NULL)
1388 return (EINVAL);
1389
1390 *type = CPUFREQ_TYPE_ABSOLUTE;
1391 return (0);
1392}