1/*-
2 * Copyright (c) 2004 Colin Percival
3 * Copyright (c) 2005 Nate Lawson
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted providing that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 185341 2008-11-26 19:25:13Z jkim $");
30
31#include <sys/param.h>
32#include <sys/bus.h>
33#include <sys/cpu.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/smp.h>
38#include <sys/systm.h>
39
40#include "cpufreq_if.h"
41#include <machine/clock.h>
42#include <machine/cputypes.h>
43#include <machine/md_var.h>
44#include <machine/specialreg.h>
45
46#include <contrib/dev/acpica/acpi.h>
47#include <dev/acpica/acpivar.h>
48#include "acpi_if.h"
49
50/* Status/control registers (from the IA-32 System Programming Guide). */
51#define MSR_PERF_STATUS 0x198
52#define MSR_PERF_CTL 0x199
53
54/* Register and bit for enabling SpeedStep. */
55#define MSR_MISC_ENABLE 0x1a0
56#define MSR_SS_ENABLE (1<<16)
57
58#ifndef CPU_VENDOR_CENTAUR
59#define CPU_VENDOR_CENTAUR 0x111d
60#endif
61
62/* Frequency and MSR control values. */
63typedef struct {
64 uint16_t freq;
65 uint16_t volts;
66 uint16_t id16;
67 int power;
68} freq_info;
69
70/* Identifying characteristics of a processor and supported frequencies. */
71typedef struct {
72 const u_int vendor_id;
73 uint32_t id32;
74 freq_info *freqtab;
75} cpu_info;
76
77struct est_softc {
78 device_t dev;
79 int acpi_settings;
80 int msr_settings;
81 freq_info *freq_list;
82};
83
84/* Convert MHz and mV into IDs for passing to the MSR. */
85#define ID16(MHz, mV, bus_clk) \
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
87#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
88 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
89
90/* Format for storing IDs in our table. */
91#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \
92 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
93#define FREQ_INFO(MHz, mV, bus_clk) \
94 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
95#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
96 { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
97#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
98 { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
99
100static int msr_info_enabled = 0;
101TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
102
103/* Default bus clock value for Centrino processors. */
104#define INTEL_BUS_CLK 100
105
106/* XXX Update this if new CPUs have more settings. */
107#define EST_MAX_SETTINGS 10
108CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
109
110/* Estimate in microseconds of latency for performing a transition. */
111#define EST_TRANS_LAT 1000
112
113/*
114 * Frequency (MHz) and voltage (mV) settings. Data from the
115 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
116 *
117 * Dothan processors have multiple VID#s with different settings for
118 * each VID#. Since we can't uniquely identify this info
119 * without undisclosed methods from Intel, we can't support newer
120 * processors with this table method. If ACPI Px states are supported,
121 * we get info from them.
122 */
123static freq_info PM17_130[] = {
124 /* 130nm 1.70GHz Pentium M */
125 FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
126 FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
127 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
128 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
129 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
130 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
131 FREQ_INFO( 0, 0, 1),
132};
133static freq_info PM16_130[] = {
134 /* 130nm 1.60GHz Pentium M */
135 FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
136 FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
137 FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
138 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
139 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
140 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
141 FREQ_INFO( 0, 0, 1),
142};
143static freq_info PM15_130[] = {
144 /* 130nm 1.50GHz Pentium M */
145 FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
146 FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
147 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
148 FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
149 FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
150 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
151 FREQ_INFO( 0, 0, 1),
152};
153static freq_info PM14_130[] = {
154 /* 130nm 1.40GHz Pentium M */
155 FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
156 FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
157 FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
158 FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
159 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
160 FREQ_INFO( 0, 0, 1),
161};
162static freq_info PM13_130[] = {
163 /* 130nm 1.30GHz Pentium M */
164 FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
165 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
166 FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
167 FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
168 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
169 FREQ_INFO( 0, 0, 1),
170};
171static freq_info PM13_LV_130[] = {
172 /* 130nm 1.30GHz Low Voltage Pentium M */
173 FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
174 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
175 FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
176 FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
177 FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
178 FREQ_INFO( 800, 988, INTEL_BUS_CLK),
179 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
180 FREQ_INFO( 0, 0, 1),
181};
182static freq_info PM12_LV_130[] = {
183 /* 130 nm 1.20GHz Low Voltage Pentium M */
184 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
185 FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
186 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
187 FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
188 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
189 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
190 FREQ_INFO( 0, 0, 1),
191};
192static freq_info PM11_LV_130[] = {
193 /* 130 nm 1.10GHz Low Voltage Pentium M */
194 FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
195 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
196 FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
197 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
198 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
199 FREQ_INFO( 0, 0, 1),
200};
201static freq_info PM11_ULV_130[] = {
202 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
203 FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
204 FREQ_INFO(1000, 988, INTEL_BUS_CLK),
205 FREQ_INFO( 900, 972, INTEL_BUS_CLK),
206 FREQ_INFO( 800, 956, INTEL_BUS_CLK),
207 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
208 FREQ_INFO( 0, 0, 1),
209};
210static freq_info PM10_ULV_130[] = {
211 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
212 FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
213 FREQ_INFO( 900, 988, INTEL_BUS_CLK),
214 FREQ_INFO( 800, 972, INTEL_BUS_CLK),
215 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
216 FREQ_INFO( 0, 0, 1),
217};
218
219/*
220 * Data from "Intel Pentium M Processor on 90nm Process with
221 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
222 */
223static freq_info PM_765A_90[] = {
224 /* 90 nm 2.10GHz Pentium M, VID #A */
225 FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
226 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
227 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
228 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
229 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
230 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
231 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
232 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
233 FREQ_INFO( 0, 0, 1),
234};
235static freq_info PM_765B_90[] = {
236 /* 90 nm 2.10GHz Pentium M, VID #B */
237 FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
238 FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
239 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
240 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
241 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
242 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
243 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
244 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
245 FREQ_INFO( 0, 0, 1),
246};
247static freq_info PM_765C_90[] = {
248 /* 90 nm 2.10GHz Pentium M, VID #C */
249 FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
250 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
251 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
252 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
253 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
254 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
255 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
256 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
257 FREQ_INFO( 0, 0, 1),
258};
259static freq_info PM_765E_90[] = {
260 /* 90 nm 2.10GHz Pentium M, VID #E */
261 FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
262 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
263 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
264 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
265 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
266 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
267 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
268 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
269 FREQ_INFO( 0, 0, 1),
270};
271static freq_info PM_755A_90[] = {
272 /* 90 nm 2.00GHz Pentium M, VID #A */
273 FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
274 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
275 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
276 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
277 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
278 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
279 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
280 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
281 FREQ_INFO( 0, 0, 1),
282};
283static freq_info PM_755B_90[] = {
284 /* 90 nm 2.00GHz Pentium M, VID #B */
285 FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
286 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
287 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
288 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
289 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
290 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
291 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
292 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
293 FREQ_INFO( 0, 0, 1),
294};
295static freq_info PM_755C_90[] = {
296 /* 90 nm 2.00GHz Pentium M, VID #C */
297 FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
298 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
299 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
300 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
301 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
302 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
303 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
304 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
305 FREQ_INFO( 0, 0, 1),
306};
307static freq_info PM_755D_90[] = {
308 /* 90 nm 2.00GHz Pentium M, VID #D */
309 FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
310 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
311 FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
312 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
313 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
314 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
315 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
316 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
317 FREQ_INFO( 0, 0, 1),
318};
319static freq_info PM_745A_90[] = {
320 /* 90 nm 1.80GHz Pentium M, VID #A */
321 FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
322 FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
323 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
324 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
325 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
326 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
327 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
328 FREQ_INFO( 0, 0, 1),
329};
330static freq_info PM_745B_90[] = {
331 /* 90 nm 1.80GHz Pentium M, VID #B */
332 FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
333 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
334 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
335 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
336 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
337 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
338 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
339 FREQ_INFO( 0, 0, 1),
340};
341static freq_info PM_745C_90[] = {
342 /* 90 nm 1.80GHz Pentium M, VID #C */
343 FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
344 FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
345 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
346 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
347 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
348 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
349 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
350 FREQ_INFO( 0, 0, 1),
351};
352static freq_info PM_745D_90[] = {
353 /* 90 nm 1.80GHz Pentium M, VID #D */
354 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
355 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
356 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
357 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
358 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
359 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
360 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
361 FREQ_INFO( 0, 0, 1),
362};
363static freq_info PM_735A_90[] = {
364 /* 90 nm 1.70GHz Pentium M, VID #A */
365 FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
366 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
367 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
368 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
369 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
370 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
371 FREQ_INFO( 0, 0, 1),
372};
373static freq_info PM_735B_90[] = {
374 /* 90 nm 1.70GHz Pentium M, VID #B */
375 FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
376 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
377 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
378 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
379 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
380 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
381 FREQ_INFO( 0, 0, 1),
382};
383static freq_info PM_735C_90[] = {
384 /* 90 nm 1.70GHz Pentium M, VID #C */
385 FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
386 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
387 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
388 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
389 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
390 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
391 FREQ_INFO( 0, 0, 1),
392};
393static freq_info PM_735D_90[] = {
394 /* 90 nm 1.70GHz Pentium M, VID #D */
395 FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
396 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
397 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
398 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
399 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
400 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
401 FREQ_INFO( 0, 0, 1),
402};
403static freq_info PM_725A_90[] = {
404 /* 90 nm 1.60GHz Pentium M, VID #A */
405 FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
406 FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
407 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
408 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
409 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
410 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
411 FREQ_INFO( 0, 0, 1),
412};
413static freq_info PM_725B_90[] = {
414 /* 90 nm 1.60GHz Pentium M, VID #B */
415 FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
416 FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
417 FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
418 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
419 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
420 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
421 FREQ_INFO( 0, 0, 1),
422};
423static freq_info PM_725C_90[] = {
424 /* 90 nm 1.60GHz Pentium M, VID #C */
425 FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
426 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
427 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
428 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
429 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
430 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
431 FREQ_INFO( 0, 0, 1),
432};
433static freq_info PM_725D_90[] = {
434 /* 90 nm 1.60GHz Pentium M, VID #D */
435 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
436 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
437 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
438 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
439 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
440 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
441 FREQ_INFO( 0, 0, 1),
442};
443static freq_info PM_715A_90[] = {
444 /* 90 nm 1.50GHz Pentium M, VID #A */
445 FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
446 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
447 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
448 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
449 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
450 FREQ_INFO( 0, 0, 1),
451};
452static freq_info PM_715B_90[] = {
453 /* 90 nm 1.50GHz Pentium M, VID #B */
454 FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
455 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
456 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
457 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
458 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
459 FREQ_INFO( 0, 0, 1),
460};
461static freq_info PM_715C_90[] = {
462 /* 90 nm 1.50GHz Pentium M, VID #C */
463 FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
464 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
465 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
466 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
467 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
468 FREQ_INFO( 0, 0, 1),
469};
470static freq_info PM_715D_90[] = {
471 /* 90 nm 1.50GHz Pentium M, VID #D */
472 FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
473 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
474 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
475 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
476 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
477 FREQ_INFO( 0, 0, 1),
478};
479static freq_info PM_778_90[] = {
480 /* 90 nm 1.60GHz Low Voltage Pentium M */
481 FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
482 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
483 FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
484 FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
485 FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
486 FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
487 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
488 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
489 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
490 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
491 FREQ_INFO( 0, 0, 1),
492};
493static freq_info PM_758_90[] = {
494 /* 90 nm 1.50GHz Low Voltage Pentium M */
495 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
496 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
497 FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
498 FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
499 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
500 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
501 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
502 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
503 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
504 FREQ_INFO( 0, 0, 1),
505};
506static freq_info PM_738_90[] = {
507 /* 90 nm 1.40GHz Low Voltage Pentium M */
508 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
509 FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
510 FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
511 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
512 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
513 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
514 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
515 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
516 FREQ_INFO( 0, 0, 1),
517};
518static freq_info PM_773G_90[] = {
519 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
520 FREQ_INFO(1300, 956, INTEL_BUS_CLK),
521 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
522 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
523 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
524 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
525 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
526 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
527};
528static freq_info PM_773H_90[] = {
529 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
530 FREQ_INFO(1300, 940, INTEL_BUS_CLK),
531 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
532 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
533 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
534 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
535 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
536 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
537};
538static freq_info PM_773I_90[] = {
539 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
540 FREQ_INFO(1300, 924, INTEL_BUS_CLK),
541 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
542 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
543 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
544 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
545 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
546 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
547};
548static freq_info PM_773J_90[] = {
549 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
550 FREQ_INFO(1300, 908, INTEL_BUS_CLK),
551 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
552 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
553 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
554 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
555 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
556 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
557};
558static freq_info PM_773K_90[] = {
559 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
560 FREQ_INFO(1300, 892, INTEL_BUS_CLK),
561 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
562 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
563 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
564 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
565 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
566 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
567};
568static freq_info PM_773L_90[] = {
569 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
570 FREQ_INFO(1300, 876, INTEL_BUS_CLK),
571 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
572 FREQ_INFO(1100, 860, INTEL_BUS_CLK),
573 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
574 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
575 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
576 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
577};
578static freq_info PM_753G_90[] = {
579 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
580 FREQ_INFO(1200, 956, INTEL_BUS_CLK),
581 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
582 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
583 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
584 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
585 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
586};
587static freq_info PM_753H_90[] = {
588 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
589 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
590 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
591 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
592 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
593 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
594 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
595};
596static freq_info PM_753I_90[] = {
597 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
598 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
599 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
600 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
601 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
602 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
603 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
604};
605static freq_info PM_753J_90[] = {
606 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
607 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
608 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
609 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
610 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
611 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
612 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
613};
614static freq_info PM_753K_90[] = {
615 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
616 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
617 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
618 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
619 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
620 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
621 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
622};
623static freq_info PM_753L_90[] = {
624 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
625 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
626 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
627 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
628 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
629 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
630 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
631};
632
633static freq_info PM_733JG_90[] = {
634 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
635 FREQ_INFO(1100, 956, INTEL_BUS_CLK),
636 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
637 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
638 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
639 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
640};
641static freq_info PM_733JH_90[] = {
642 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
643 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
644 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
645 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
646 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
647 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
648};
649static freq_info PM_733JI_90[] = {
650 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
651 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
652 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
653 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
654 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
655 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
656};
657static freq_info PM_733JJ_90[] = {
658 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
659 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
660 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
661 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
662 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
663 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
664};
665static freq_info PM_733JK_90[] = {
666 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
667 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
668 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
669 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
670 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
671 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
672};
673static freq_info PM_733JL_90[] = {
674 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
675 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
676 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
677 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
678 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
679 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
680};
681static freq_info PM_733_90[] = {
682 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
683 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
684 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
685 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
686 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
687 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
688 FREQ_INFO( 0, 0, 1),
689};
690static freq_info PM_723_90[] = {
691 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
692 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
693 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
694 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
695 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
696 FREQ_INFO( 0, 0, 1),
697};
698
699/*
700 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
701 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
702 */
703static freq_info C7M_795[] = {
704 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
705 FREQ_INFO_PWR(2000, 1148, 133, 20000),
706 FREQ_INFO_PWR(1867, 1132, 133, 18000),
707 FREQ_INFO_PWR(1600, 1100, 133, 15000),
708 FREQ_INFO_PWR(1467, 1052, 133, 13000),
709 FREQ_INFO_PWR(1200, 1004, 133, 10000),
710 FREQ_INFO_PWR( 800, 844, 133, 7000),
711 FREQ_INFO_PWR( 667, 844, 133, 6000),
712 FREQ_INFO_PWR( 533, 844, 133, 5000),
713 FREQ_INFO(0, 0, 1),
714};
715static freq_info C7M_785[] = {
716 /* 1.80GHz Centaur C7-M 533 Mhz FSB */
717 FREQ_INFO_PWR(1867, 1148, 133, 18000),
718 FREQ_INFO_PWR(1600, 1100, 133, 15000),
719 FREQ_INFO_PWR(1467, 1052, 133, 13000),
720 FREQ_INFO_PWR(1200, 1004, 133, 10000),
721 FREQ_INFO_PWR( 800, 844, 133, 7000),
722 FREQ_INFO_PWR( 667, 844, 133, 6000),
723 FREQ_INFO_PWR( 533, 844, 133, 5000),
724 FREQ_INFO(0, 0, 1),
725};
726static freq_info C7M_765[] = {
727 /* 1.60GHz Centaur C7-M 533 Mhz FSB */
728 FREQ_INFO_PWR(1600, 1084, 133, 15000),
729 FREQ_INFO_PWR(1467, 1052, 133, 13000),
730 FREQ_INFO_PWR(1200, 1004, 133, 10000),
731 FREQ_INFO_PWR( 800, 844, 133, 7000),
732 FREQ_INFO_PWR( 667, 844, 133, 6000),
733 FREQ_INFO_PWR( 533, 844, 133, 5000),
734 FREQ_INFO(0, 0, 1),
735};
736
737static freq_info C7M_794[] = {
738 /* 2.00GHz Centaur C7-M 400 Mhz FSB */
739 FREQ_INFO_PWR(2000, 1148, 100, 20000),
740 FREQ_INFO_PWR(1800, 1132, 100, 18000),
741 FREQ_INFO_PWR(1600, 1100, 100, 15000),
742 FREQ_INFO_PWR(1400, 1052, 100, 13000),
743 FREQ_INFO_PWR(1000, 1004, 100, 10000),
744 FREQ_INFO_PWR( 800, 844, 100, 7000),
745 FREQ_INFO_PWR( 600, 844, 100, 6000),
746 FREQ_INFO_PWR( 400, 844, 100, 5000),
747 FREQ_INFO(0, 0, 1),
748};
749static freq_info C7M_784[] = {
750 /* 1.80GHz Centaur C7-M 400 Mhz FSB */
751 FREQ_INFO_PWR(1800, 1148, 100, 18000),
752 FREQ_INFO_PWR(1600, 1100, 100, 15000),
753 FREQ_INFO_PWR(1400, 1052, 100, 13000),
754 FREQ_INFO_PWR(1000, 1004, 100, 10000),
755 FREQ_INFO_PWR( 800, 844, 100, 7000),
756 FREQ_INFO_PWR( 600, 844, 100, 6000),
757 FREQ_INFO_PWR( 400, 844, 100, 5000),
758 FREQ_INFO(0, 0, 1),
759};
760static freq_info C7M_764[] = {
761 /* 1.60GHz Centaur C7-M 400 Mhz FSB */
762 FREQ_INFO_PWR(1600, 1084, 100, 15000),
763 FREQ_INFO_PWR(1400, 1052, 100, 13000),
764 FREQ_INFO_PWR(1000, 1004, 100, 10000),
765 FREQ_INFO_PWR( 800, 844, 100, 7000),
766 FREQ_INFO_PWR( 600, 844, 100, 6000),
767 FREQ_INFO_PWR( 400, 844, 100, 5000),
768 FREQ_INFO(0, 0, 1),
769};
770static freq_info C7M_754[] = {
771 /* 1.50GHz Centaur C7-M 400 Mhz FSB */
772 FREQ_INFO_PWR(1500, 1004, 100, 12000),
773 FREQ_INFO_PWR(1400, 988, 100, 11000),
774 FREQ_INFO_PWR(1000, 940, 100, 9000),
775 FREQ_INFO_PWR( 800, 844, 100, 7000),
776 FREQ_INFO_PWR( 600, 844, 100, 6000),
777 FREQ_INFO_PWR( 400, 844, 100, 5000),
778 FREQ_INFO(0, 0, 1),
779};
780static freq_info C7M_771[] = {
781 /* 1.20GHz Centaur C7-M 400 Mhz FSB */
782 FREQ_INFO_PWR(1200, 860, 100, 7000),
783 FREQ_INFO_PWR(1000, 860, 100, 6000),
784 FREQ_INFO_PWR( 800, 844, 100, 5500),
785 FREQ_INFO_PWR( 600, 844, 100, 5000),
786 FREQ_INFO_PWR( 400, 844, 100, 4000),
787 FREQ_INFO(0, 0, 1),
788};
789
790static freq_info C7M_775_ULV[] = {
791 /* 1.50GHz Centaur C7-M ULV */
792 FREQ_INFO_PWR(1500, 956, 100, 7500),
793 FREQ_INFO_PWR(1400, 940, 100, 6000),
794 FREQ_INFO_PWR(1000, 860, 100, 5000),
795 FREQ_INFO_PWR( 800, 828, 100, 2800),
796 FREQ_INFO_PWR( 600, 796, 100, 2500),
797 FREQ_INFO_PWR( 400, 796, 100, 2000),
798 FREQ_INFO(0, 0, 1),
799};
800static freq_info C7M_772_ULV[] = {
801 /* 1.20GHz Centaur C7-M ULV */
802 FREQ_INFO_PWR(1200, 844, 100, 5000),
803 FREQ_INFO_PWR(1000, 844, 100, 4000),
804 FREQ_INFO_PWR( 800, 828, 100, 2800),
805 FREQ_INFO_PWR( 600, 796, 100, 2500),
806 FREQ_INFO_PWR( 400, 796, 100, 2000),
807 FREQ_INFO(0, 0, 1),
808};
809static freq_info C7M_779_ULV[] = {
810 /* 1.00GHz Centaur C7-M ULV */
811 FREQ_INFO_PWR(1000, 796, 100, 3500),
812 FREQ_INFO_PWR( 800, 796, 100, 2800),
813 FREQ_INFO_PWR( 600, 796, 100, 2500),
814 FREQ_INFO_PWR( 400, 796, 100, 2000),
815 FREQ_INFO(0, 0, 1),
816};
817static freq_info C7M_770_ULV[] = {
818 /* 1.00GHz Centaur C7-M ULV */
819 FREQ_INFO_PWR(1000, 844, 100, 5000),
820 FREQ_INFO_PWR( 800, 796, 100, 2800),
821 FREQ_INFO_PWR( 600, 796, 100, 2500),
822 FREQ_INFO_PWR( 400, 796, 100, 2000),
823 FREQ_INFO(0, 0, 1),
824};
825
826static cpu_info ESTprocs[] = {
827 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
828 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
829 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
830 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
831 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
832 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
833 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),
834 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK),
835 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK),
836 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK),
837 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK),
838 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK),
839 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK),
840 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK),
841 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK),
842 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK),
843 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK),
844 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK),
845 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK),
846 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK),
847 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK),
848 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK),
849 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK),
850 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK),
851 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK),
852 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK),
853 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK),
854 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK),
855 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK),
856 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK),
857 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK),
858 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK),
859 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK),
860 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK),
861 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK),
862 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK),
863 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK),
864 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK),
865 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK),
866 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK),
867 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK),
868 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK),
869 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK),
870 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK),
871 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK),
872 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK),
873 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK),
874 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK),
875 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK),
876 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
877 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
878 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
879 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
880 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
881 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
882 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
883 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
884
885 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133),
886 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
887 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133),
888 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
889 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133),
890 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
891 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
892 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
893 CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
894 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
895 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
896 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
897 { 0, 0, NULL },
898};
899
900static void est_identify(driver_t *driver, device_t parent);
901static int est_features(driver_t *driver, u_int *features);
902static int est_probe(device_t parent);
903static int est_attach(device_t parent);
904static int est_detach(device_t parent);
905static int est_get_info(device_t dev);
906static int est_acpi_info(device_t dev, freq_info **freqs);
907static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
908static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
909static freq_info *est_get_current(freq_info *freq_list);
910static int est_settings(device_t dev, struct cf_setting *sets, int *count);
911static int est_set(device_t dev, const struct cf_setting *set);
912static int est_get(device_t dev, struct cf_setting *set);
913static int est_type(device_t dev, int *type);
914static int est_set_id16(device_t dev, uint16_t id16, int need_check);
915static void est_get_id16(uint16_t *id16_p);
916
917static device_method_t est_methods[] = {
918 /* Device interface */
919 DEVMETHOD(device_identify, est_identify),
920 DEVMETHOD(device_probe, est_probe),
921 DEVMETHOD(device_attach, est_attach),
922 DEVMETHOD(device_detach, est_detach),
923
924 /* cpufreq interface */
925 DEVMETHOD(cpufreq_drv_set, est_set),
926 DEVMETHOD(cpufreq_drv_get, est_get),
927 DEVMETHOD(cpufreq_drv_type, est_type),
928 DEVMETHOD(cpufreq_drv_settings, est_settings),
929
930 /* ACPI interface */
931 DEVMETHOD(acpi_get_features, est_features),
932
933 {0, 0}
934};
935
936static driver_t est_driver = {
937 "est",
938 est_methods,
939 sizeof(struct est_softc),
940};
941
942static devclass_t est_devclass;
943DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
944
945static int
946est_features(driver_t *driver, u_int *features)
947{
948
949 /* Notify the ACPI CPU that we support direct access to MSRs */
950 *features = ACPI_CAP_PERF_MSRS;
951 return (0);
952}
953
954static void
955est_identify(driver_t *driver, device_t parent)
956{
957 device_t child;
958
959 /* Make sure we're not being doubly invoked. */
960 if (device_find_child(parent, "est", -1) != NULL)
961 return;
962
963 /* Check that CPUID is supported and the vendor is Intel.*/
964 if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
965 cpu_vendor_id != CPU_VENDOR_CENTAUR))
966 return;
967
968 /*
969 * Check if the CPU supports EST.
970 */
971 if (!(cpu_feature2 & CPUID2_EST))
972 return;
973
974 /*
975 * We add a child for each CPU since settings must be performed
976 * on each CPU in the SMP case.
977 */
978 child = BUS_ADD_CHILD(parent, 10, "est", -1);
979 if (child == NULL)
980 device_printf(parent, "add est child failed\n");
981}
982
983static int
984est_probe(device_t dev)
985{
986 device_t perf_dev;
987 uint64_t msr;
988 int error, type;
989
990 if (resource_disabled("est", 0))
991 return (ENXIO);
992
993 /*
994 * If the ACPI perf driver has attached and is not just offering
995 * info, let it manage things.
996 */
997 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
998 if (perf_dev && device_is_attached(perf_dev)) {
999 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
1000 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
1001 return (ENXIO);
1002 }
1003
1004 /* Attempt to enable SpeedStep if not currently enabled. */
1005 msr = rdmsr(MSR_MISC_ENABLE);
1006 if ((msr & MSR_SS_ENABLE) == 0) {
1007 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
1008 if (bootverbose)
1009 device_printf(dev, "enabling SpeedStep\n");
1010
1011 /* Check if the enable failed. */
1012 msr = rdmsr(MSR_MISC_ENABLE);
1013 if ((msr & MSR_SS_ENABLE) == 0) {
1014 device_printf(dev, "failed to enable SpeedStep\n");
1015 return (ENXIO);
1016 }
1017 }
1018
1019 device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
1020 return (0);
1021}
1022
1023static int
1024est_attach(device_t dev)
1025{
1026 struct est_softc *sc;
1027
1028 sc = device_get_softc(dev);
1029 sc->dev = dev;
1030
1031 /* Check CPU for supported settings. */
1032 if (est_get_info(dev))
1033 return (ENXIO);
1034
1035 cpufreq_register(dev);
1036 return (0);
1037}
1038
1039static int
1040est_detach(device_t dev)
1041{
1042 struct est_softc *sc;
1043 int error;
1044
1045 error = cpufreq_unregister(dev);
1046 if (error)
1047 return (error);
1048
1049 sc = device_get_softc(dev);
1050 if (sc->acpi_settings || sc->msr_settings)
1051 free(sc->freq_list, M_DEVBUF);
1052 return (0);
1053}
1054
1055/*
1056 * Probe for supported CPU settings. First, check our static table of
1057 * settings. If no match, try using the ones offered by acpi_perf
1058 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40
1059 * series) export both legacy SMM IO-based access and direct MSR access
1060 * but the direct access specifies invalid values for _PSS.
1061 */
1062static int
1063est_get_info(device_t dev)
1064{
1065 struct est_softc *sc;
1066 uint64_t msr;
1067 int error;
1068
1069 sc = device_get_softc(dev);
1070 msr = rdmsr(MSR_PERF_STATUS);
1071 error = est_table_info(dev, msr, &sc->freq_list);
1072 if (error)
1073 error = est_acpi_info(dev, &sc->freq_list);
1074 if (error)
1075 error = est_msr_info(dev, msr, &sc->freq_list);
1076
1077 if (error) {
1078 printf(
1079 "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
1080 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
1081 return (ENXIO);
1082 }
1083
1084 return (0);
1085}
1086
1087static int
1088est_acpi_info(device_t dev, freq_info **freqs)
1089{
1090 struct est_softc *sc;
1091 struct cf_setting *sets;
1092 freq_info *table;
1093 device_t perf_dev;
1094 int count, error, i, j;
1095 uint16_t saved_id16;
1096
1097 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
1098 if (perf_dev == NULL || !device_is_attached(perf_dev))
1099 return (ENXIO);
1100
1101 /* Fetch settings from acpi_perf. */
1102 sc = device_get_softc(dev);
1103 table = NULL;
1104 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
1105 if (sets == NULL)
1106 return (ENOMEM);
1107 count = MAX_SETTINGS;
1108 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
1109 if (error)
1110 goto out;
1111
1112 /* Parse settings into our local table format. */
1113 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
1114 if (table == NULL) {
1115 error = ENOMEM;
1116 goto out;
1117 }
1118 est_get_id16(&saved_id16);
1119 for (i = 0, j = 0; i < count; i++) {
1120 /*
1121 * Confirm id16 value is correct.
1122 */
1123 if (sets[i].freq > 0) {
1124 error = est_set_id16(dev, sets[i].spec[0], 1);
1125 if (error != 0) {
1126 if (bootverbose)
1127 device_printf(dev, "Invalid freq %u, "
1128 "ignored.\n", sets[i].freq);
1129 } else {
1130 table[j].freq = sets[i].freq;
1131 table[j].volts = sets[i].volts;
1132 table[j].id16 = sets[i].spec[0];
1133 table[j].power = sets[i].power;
1134 ++j;
1135 }
1136 }
1137 }
1138 /* restore saved setting */
1139 est_set_id16(dev, saved_id16, 0);
1140
1141 /* Mark end of table with a terminator. */
1142 bzero(&table[j], sizeof(freq_info));
1143
1144 sc->acpi_settings = TRUE;
1145 *freqs = table;
1146 error = 0;
1147
1148out:
1149 if (sets)
1150 free(sets, M_TEMP);
1151 if (error && table)
1152 free(table, M_DEVBUF);
1153 return (error);
1154}
1155
1156static int
1157est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
1158{
1159 cpu_info *p;
1160 uint32_t id;
1161
1162 /* Find a table which matches (vendor, id32). */
1163 id = msr >> 32;
1164 for (p = ESTprocs; p->id32 != 0; p++) {
1165 if (p->vendor_id == cpu_vendor_id && p->id32 == id)
1166 break;
1167 }
1168 if (p->id32 == 0)
1169 return (EOPNOTSUPP);
1170
1171 /* Make sure the current setpoint is valid. */
1172 if (est_get_current(p->freqtab) == NULL) {
1173 device_printf(dev, "current setting not found in table\n");
1174 return (EOPNOTSUPP);
1175 }
1176
1177 *freqs = p->freqtab;
1178 return (0);
1179}
1180
1181static int
1182bus_speed_ok(int bus)
1183{
1184
1185 switch (bus) {
1186 case 100:
1187 case 133:
1188 case 333:
1189 return (1);
1190 default:
1191 return (0);
1192 }
1193}
1194
1195/*
1196 * Flesh out a simple rate table containing the high and low frequencies
1197 * based on the current clock speed and the upper 32 bits of the MSR.
1198 */
1199static int
1200est_msr_info(device_t dev, uint64_t msr, freq_info **freqs)
1201{
1202 struct est_softc *sc;
1203 freq_info *fp;
1204 int bus, freq, volts;
1205 uint16_t id;
1206
1207 if (!msr_info_enabled)
1208 return (EOPNOTSUPP);
1209
1210 /* Figure out the bus clock. */
1211 freq = tsc_freq / 1000000;
1212 id = msr >> 32;
1213 bus = freq / (id >> 8);
1214 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus);
1215 if (!bus_speed_ok(bus)) {
1216 /* We may be running on the low frequency. */
1217 id = msr >> 48;
1218 bus = freq / (id >> 8);
1219 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus);
1220 if (!bus_speed_ok(bus))
1221 return (EOPNOTSUPP);
1222
1223 /* Calculate high frequency. */
1224 id = msr >> 32;
1225 freq = ((id >> 8) & 0xff) * bus;
1226 }
1227
1228 /* Fill out a new freq table containing just the high and low freqs. */
1229 sc = device_get_softc(dev);
1230 fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO);
1231
1232 /* First, the high frequency. */
1233 volts = id & 0xff;
1234 if (volts != 0) {
1235 volts <<= 4;
1236 volts += 700;
1237 }
1238 fp[0].freq = freq;
1239 fp[0].volts = volts;
1240 fp[0].id16 = id;
1241 fp[0].power = CPUFREQ_VAL_UNKNOWN;
1242 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq,
1243 volts);
1244
1245 /* Second, the low frequency. */
1246 id = msr >> 48;
1247 freq = ((id >> 8) & 0xff) * bus;
1248 volts = id & 0xff;
1249 if (volts != 0) {
1250 volts <<= 4;
1251 volts += 700;
1252 }
1253 fp[1].freq = freq;
1254 fp[1].volts = volts;
1255 fp[1].id16 = id;
1256 fp[1].power = CPUFREQ_VAL_UNKNOWN;
1257 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq,
1258 volts);
1259
1260 /* Table is already terminated due to M_ZERO. */
1261 sc->msr_settings = TRUE;
1262 *freqs = fp;
1263 return (0);
1264}
1265
1266static void
1267est_get_id16(uint16_t *id16_p)
1268{
1269 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;
1270}
1271
1272static int
1273est_set_id16(device_t dev, uint16_t id16, int need_check)
1274{
1275 uint64_t msr;
1276 uint16_t new_id16;
1277 int ret = 0;
1278
1279 /* Read the current register, mask out the old, set the new id. */
1280 msr = rdmsr(MSR_PERF_CTL);
1281 msr = (msr & ~0xffff) | id16;
1282 wrmsr(MSR_PERF_CTL, msr);
1283
1284 /* Wait a short while for the new setting. XXX Is this necessary? */
1285 DELAY(EST_TRANS_LAT);
1286
1287 if (need_check) {
1288 est_get_id16(&new_id16);
1289 if (new_id16 != id16) {
1290 if (bootverbose)
1291 device_printf(dev, "Invalid id16 (set, cur) "
1292 "= (%u, %u)\n", id16, new_id16);
1293 ret = ENXIO;
1294 }
1295 }
1296 return (ret);
1297}
1298
1299static freq_info *
1300est_get_current(freq_info *freq_list)
1301{
1302 freq_info *f;
1303 int i;
1304 uint16_t id16;
1305
1306 /*
1307 * Try a few times to get a valid value. Sometimes, if the CPU
1308 * is in the middle of an asynchronous transition (i.e., P4TCC),
1309 * we get a temporary invalid result.
1310 */
1311 for (i = 0; i < 5; i++) {
1312 est_get_id16(&id16);
1313 for (f = freq_list; f->id16 != 0; f++) {
1314 if (f->id16 == id16)
1315 return (f);
1316 }
1317 DELAY(100);
1318 }
1319 return (NULL);
1320}
1321
1322static int
1323est_settings(device_t dev, struct cf_setting *sets, int *count)
1324{
1325 struct est_softc *sc;
1326 freq_info *f;
1327 int i;
1328
1329 sc = device_get_softc(dev);
1330 if (*count < EST_MAX_SETTINGS)
1331 return (E2BIG);
1332
1333 i = 0;
1334 for (f = sc->freq_list; f->freq != 0; f++, i++) {
1335 sets[i].freq = f->freq;
1336 sets[i].volts = f->volts;
1337 sets[i].power = f->power;
1338 sets[i].lat = EST_TRANS_LAT;
1339 sets[i].dev = dev;
1340 }
1341 *count = i;
1342
1343 return (0);
1344}
1345
1346static int
1347est_set(device_t dev, const struct cf_setting *set)
1348{
1349 struct est_softc *sc;
1350 freq_info *f;
1351
1352 /* Find the setting matching the requested one. */
1353 sc = device_get_softc(dev);
1354 for (f = sc->freq_list; f->freq != 0; f++) {
1355 if (f->freq == set->freq)
1356 break;
1357 }
1358 if (f->freq == 0)
1359 return (EINVAL);
1360
1361 /* Read the current register, mask out the old, set the new id. */
1362 est_set_id16(dev, f->id16, 0);
1363
1364 return (0);
1365}
1366
1367static int
1368est_get(device_t dev, struct cf_setting *set)
1369{
1370 struct est_softc *sc;
1371 freq_info *f;
1372
1373 sc = device_get_softc(dev);
1374 f = est_get_current(sc->freq_list);
1375 if (f == NULL)
1376 return (ENXIO);
1377
1378 set->freq = f->freq;
1379 set->volts = f->volts;
1380 set->power = f->power;
1381 set->lat = EST_TRANS_LAT;
1382 set->dev = dev;
1383 return (0);
1384}
1385
1386static int
1387est_type(device_t dev, int *type)
1388{
1389
1390 if (type == NULL)
1391 return (EINVAL);
1392
1393 *type = CPUFREQ_TYPE_ABSOLUTE;
1394 return (0);
1395}
2 * Copyright (c) 2004 Colin Percival
3 * Copyright (c) 2005 Nate Lawson
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted providing that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 185341 2008-11-26 19:25:13Z jkim $");
30
31#include <sys/param.h>
32#include <sys/bus.h>
33#include <sys/cpu.h>
34#include <sys/kernel.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/smp.h>
38#include <sys/systm.h>
39
40#include "cpufreq_if.h"
41#include <machine/clock.h>
42#include <machine/cputypes.h>
43#include <machine/md_var.h>
44#include <machine/specialreg.h>
45
46#include <contrib/dev/acpica/acpi.h>
47#include <dev/acpica/acpivar.h>
48#include "acpi_if.h"
49
50/* Status/control registers (from the IA-32 System Programming Guide). */
51#define MSR_PERF_STATUS 0x198
52#define MSR_PERF_CTL 0x199
53
54/* Register and bit for enabling SpeedStep. */
55#define MSR_MISC_ENABLE 0x1a0
56#define MSR_SS_ENABLE (1<<16)
57
58#ifndef CPU_VENDOR_CENTAUR
59#define CPU_VENDOR_CENTAUR 0x111d
60#endif
61
62/* Frequency and MSR control values. */
63typedef struct {
64 uint16_t freq;
65 uint16_t volts;
66 uint16_t id16;
67 int power;
68} freq_info;
69
70/* Identifying characteristics of a processor and supported frequencies. */
71typedef struct {
72 const u_int vendor_id;
73 uint32_t id32;
74 freq_info *freqtab;
75} cpu_info;
76
77struct est_softc {
78 device_t dev;
79 int acpi_settings;
80 int msr_settings;
81 freq_info *freq_list;
82};
83
84/* Convert MHz and mV into IDs for passing to the MSR. */
85#define ID16(MHz, mV, bus_clk) \
86 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
87#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
88 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
89
90/* Format for storing IDs in our table. */
91#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \
92 { MHz, mV, ID16(MHz, mV, bus_clk), mW }
93#define FREQ_INFO(MHz, mV, bus_clk) \
94 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
95#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
96 { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
97#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
98 { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
99
100static int msr_info_enabled = 0;
101TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
102
103/* Default bus clock value for Centrino processors. */
104#define INTEL_BUS_CLK 100
105
106/* XXX Update this if new CPUs have more settings. */
107#define EST_MAX_SETTINGS 10
108CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
109
110/* Estimate in microseconds of latency for performing a transition. */
111#define EST_TRANS_LAT 1000
112
113/*
114 * Frequency (MHz) and voltage (mV) settings. Data from the
115 * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
116 *
117 * Dothan processors have multiple VID#s with different settings for
118 * each VID#. Since we can't uniquely identify this info
119 * without undisclosed methods from Intel, we can't support newer
120 * processors with this table method. If ACPI Px states are supported,
121 * we get info from them.
122 */
123static freq_info PM17_130[] = {
124 /* 130nm 1.70GHz Pentium M */
125 FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
126 FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
127 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
128 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
129 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
130 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
131 FREQ_INFO( 0, 0, 1),
132};
133static freq_info PM16_130[] = {
134 /* 130nm 1.60GHz Pentium M */
135 FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
136 FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
137 FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
138 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
139 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
140 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
141 FREQ_INFO( 0, 0, 1),
142};
143static freq_info PM15_130[] = {
144 /* 130nm 1.50GHz Pentium M */
145 FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
146 FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
147 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
148 FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
149 FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
150 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
151 FREQ_INFO( 0, 0, 1),
152};
153static freq_info PM14_130[] = {
154 /* 130nm 1.40GHz Pentium M */
155 FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
156 FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
157 FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
158 FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
159 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
160 FREQ_INFO( 0, 0, 1),
161};
162static freq_info PM13_130[] = {
163 /* 130nm 1.30GHz Pentium M */
164 FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
165 FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
166 FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
167 FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
168 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
169 FREQ_INFO( 0, 0, 1),
170};
171static freq_info PM13_LV_130[] = {
172 /* 130nm 1.30GHz Low Voltage Pentium M */
173 FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
174 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
175 FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
176 FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
177 FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
178 FREQ_INFO( 800, 988, INTEL_BUS_CLK),
179 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
180 FREQ_INFO( 0, 0, 1),
181};
182static freq_info PM12_LV_130[] = {
183 /* 130 nm 1.20GHz Low Voltage Pentium M */
184 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
185 FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
186 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
187 FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
188 FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
189 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
190 FREQ_INFO( 0, 0, 1),
191};
192static freq_info PM11_LV_130[] = {
193 /* 130 nm 1.10GHz Low Voltage Pentium M */
194 FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
195 FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
196 FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
197 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
198 FREQ_INFO( 600, 956, INTEL_BUS_CLK),
199 FREQ_INFO( 0, 0, 1),
200};
201static freq_info PM11_ULV_130[] = {
202 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
203 FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
204 FREQ_INFO(1000, 988, INTEL_BUS_CLK),
205 FREQ_INFO( 900, 972, INTEL_BUS_CLK),
206 FREQ_INFO( 800, 956, INTEL_BUS_CLK),
207 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
208 FREQ_INFO( 0, 0, 1),
209};
210static freq_info PM10_ULV_130[] = {
211 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
212 FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
213 FREQ_INFO( 900, 988, INTEL_BUS_CLK),
214 FREQ_INFO( 800, 972, INTEL_BUS_CLK),
215 FREQ_INFO( 600, 844, INTEL_BUS_CLK),
216 FREQ_INFO( 0, 0, 1),
217};
218
219/*
220 * Data from "Intel Pentium M Processor on 90nm Process with
221 * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
222 */
223static freq_info PM_765A_90[] = {
224 /* 90 nm 2.10GHz Pentium M, VID #A */
225 FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
226 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
227 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
228 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
229 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
230 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
231 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
232 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
233 FREQ_INFO( 0, 0, 1),
234};
235static freq_info PM_765B_90[] = {
236 /* 90 nm 2.10GHz Pentium M, VID #B */
237 FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
238 FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
239 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
240 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
241 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
242 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
243 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
244 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
245 FREQ_INFO( 0, 0, 1),
246};
247static freq_info PM_765C_90[] = {
248 /* 90 nm 2.10GHz Pentium M, VID #C */
249 FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
250 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
251 FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
252 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
253 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
254 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
255 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
256 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
257 FREQ_INFO( 0, 0, 1),
258};
259static freq_info PM_765E_90[] = {
260 /* 90 nm 2.10GHz Pentium M, VID #E */
261 FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
262 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
263 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
264 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
265 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
266 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
267 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
268 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
269 FREQ_INFO( 0, 0, 1),
270};
271static freq_info PM_755A_90[] = {
272 /* 90 nm 2.00GHz Pentium M, VID #A */
273 FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
274 FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
275 FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
276 FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
277 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
278 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
279 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
280 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
281 FREQ_INFO( 0, 0, 1),
282};
283static freq_info PM_755B_90[] = {
284 /* 90 nm 2.00GHz Pentium M, VID #B */
285 FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
286 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
287 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
288 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
289 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
290 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
291 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
292 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
293 FREQ_INFO( 0, 0, 1),
294};
295static freq_info PM_755C_90[] = {
296 /* 90 nm 2.00GHz Pentium M, VID #C */
297 FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
298 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
299 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
300 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
301 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
302 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
303 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
304 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
305 FREQ_INFO( 0, 0, 1),
306};
307static freq_info PM_755D_90[] = {
308 /* 90 nm 2.00GHz Pentium M, VID #D */
309 FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
310 FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
311 FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
312 FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
313 FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
314 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
315 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
316 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
317 FREQ_INFO( 0, 0, 1),
318};
319static freq_info PM_745A_90[] = {
320 /* 90 nm 1.80GHz Pentium M, VID #A */
321 FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
322 FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
323 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
324 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
325 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
326 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
327 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
328 FREQ_INFO( 0, 0, 1),
329};
330static freq_info PM_745B_90[] = {
331 /* 90 nm 1.80GHz Pentium M, VID #B */
332 FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
333 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
334 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
335 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
336 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
337 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
338 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
339 FREQ_INFO( 0, 0, 1),
340};
341static freq_info PM_745C_90[] = {
342 /* 90 nm 1.80GHz Pentium M, VID #C */
343 FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
344 FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
345 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
346 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
347 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
348 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
349 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
350 FREQ_INFO( 0, 0, 1),
351};
352static freq_info PM_745D_90[] = {
353 /* 90 nm 1.80GHz Pentium M, VID #D */
354 FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
355 FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
356 FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
357 FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
358 FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
359 FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
360 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
361 FREQ_INFO( 0, 0, 1),
362};
363static freq_info PM_735A_90[] = {
364 /* 90 nm 1.70GHz Pentium M, VID #A */
365 FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
366 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
367 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
368 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
369 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
370 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
371 FREQ_INFO( 0, 0, 1),
372};
373static freq_info PM_735B_90[] = {
374 /* 90 nm 1.70GHz Pentium M, VID #B */
375 FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
376 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
377 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
378 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
379 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
380 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
381 FREQ_INFO( 0, 0, 1),
382};
383static freq_info PM_735C_90[] = {
384 /* 90 nm 1.70GHz Pentium M, VID #C */
385 FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
386 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
387 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
388 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
389 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
390 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
391 FREQ_INFO( 0, 0, 1),
392};
393static freq_info PM_735D_90[] = {
394 /* 90 nm 1.70GHz Pentium M, VID #D */
395 FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
396 FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
397 FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
398 FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
399 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
400 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
401 FREQ_INFO( 0, 0, 1),
402};
403static freq_info PM_725A_90[] = {
404 /* 90 nm 1.60GHz Pentium M, VID #A */
405 FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
406 FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
407 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
408 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
409 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
410 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
411 FREQ_INFO( 0, 0, 1),
412};
413static freq_info PM_725B_90[] = {
414 /* 90 nm 1.60GHz Pentium M, VID #B */
415 FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
416 FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
417 FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
418 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
419 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
420 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
421 FREQ_INFO( 0, 0, 1),
422};
423static freq_info PM_725C_90[] = {
424 /* 90 nm 1.60GHz Pentium M, VID #C */
425 FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
426 FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
427 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
428 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
429 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
430 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
431 FREQ_INFO( 0, 0, 1),
432};
433static freq_info PM_725D_90[] = {
434 /* 90 nm 1.60GHz Pentium M, VID #D */
435 FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
436 FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
437 FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
438 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
439 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
440 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
441 FREQ_INFO( 0, 0, 1),
442};
443static freq_info PM_715A_90[] = {
444 /* 90 nm 1.50GHz Pentium M, VID #A */
445 FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
446 FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
447 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
448 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
449 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
450 FREQ_INFO( 0, 0, 1),
451};
452static freq_info PM_715B_90[] = {
453 /* 90 nm 1.50GHz Pentium M, VID #B */
454 FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
455 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
456 FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
457 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
458 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
459 FREQ_INFO( 0, 0, 1),
460};
461static freq_info PM_715C_90[] = {
462 /* 90 nm 1.50GHz Pentium M, VID #C */
463 FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
464 FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
465 FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
466 FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
467 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
468 FREQ_INFO( 0, 0, 1),
469};
470static freq_info PM_715D_90[] = {
471 /* 90 nm 1.50GHz Pentium M, VID #D */
472 FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
473 FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
474 FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
475 FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
476 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
477 FREQ_INFO( 0, 0, 1),
478};
479static freq_info PM_778_90[] = {
480 /* 90 nm 1.60GHz Low Voltage Pentium M */
481 FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
482 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
483 FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
484 FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
485 FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
486 FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
487 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
488 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
489 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
490 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
491 FREQ_INFO( 0, 0, 1),
492};
493static freq_info PM_758_90[] = {
494 /* 90 nm 1.50GHz Low Voltage Pentium M */
495 FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
496 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
497 FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
498 FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
499 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
500 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
501 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
502 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
503 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
504 FREQ_INFO( 0, 0, 1),
505};
506static freq_info PM_738_90[] = {
507 /* 90 nm 1.40GHz Low Voltage Pentium M */
508 FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
509 FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
510 FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
511 FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
512 FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
513 FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
514 FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
515 FREQ_INFO( 600, 988, INTEL_BUS_CLK),
516 FREQ_INFO( 0, 0, 1),
517};
518static freq_info PM_773G_90[] = {
519 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
520 FREQ_INFO(1300, 956, INTEL_BUS_CLK),
521 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
522 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
523 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
524 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
525 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
526 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
527};
528static freq_info PM_773H_90[] = {
529 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
530 FREQ_INFO(1300, 940, INTEL_BUS_CLK),
531 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
532 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
533 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
534 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
535 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
536 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
537};
538static freq_info PM_773I_90[] = {
539 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
540 FREQ_INFO(1300, 924, INTEL_BUS_CLK),
541 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
542 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
543 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
544 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
545 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
546 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
547};
548static freq_info PM_773J_90[] = {
549 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
550 FREQ_INFO(1300, 908, INTEL_BUS_CLK),
551 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
552 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
553 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
554 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
555 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
556 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
557};
558static freq_info PM_773K_90[] = {
559 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
560 FREQ_INFO(1300, 892, INTEL_BUS_CLK),
561 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
562 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
563 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
564 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
565 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
566 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
567};
568static freq_info PM_773L_90[] = {
569 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
570 FREQ_INFO(1300, 876, INTEL_BUS_CLK),
571 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
572 FREQ_INFO(1100, 860, INTEL_BUS_CLK),
573 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
574 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
575 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
576 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
577};
578static freq_info PM_753G_90[] = {
579 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
580 FREQ_INFO(1200, 956, INTEL_BUS_CLK),
581 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
582 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
583 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
584 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
585 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
586};
587static freq_info PM_753H_90[] = {
588 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
589 FREQ_INFO(1200, 940, INTEL_BUS_CLK),
590 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
591 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
592 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
593 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
594 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
595};
596static freq_info PM_753I_90[] = {
597 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
598 FREQ_INFO(1200, 924, INTEL_BUS_CLK),
599 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
600 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
601 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
602 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
603 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
604};
605static freq_info PM_753J_90[] = {
606 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
607 FREQ_INFO(1200, 908, INTEL_BUS_CLK),
608 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
609 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
610 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
611 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
612 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
613};
614static freq_info PM_753K_90[] = {
615 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
616 FREQ_INFO(1200, 892, INTEL_BUS_CLK),
617 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
618 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
619 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
620 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
621 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
622};
623static freq_info PM_753L_90[] = {
624 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
625 FREQ_INFO(1200, 876, INTEL_BUS_CLK),
626 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
627 FREQ_INFO(1000, 860, INTEL_BUS_CLK),
628 FREQ_INFO( 900, 844, INTEL_BUS_CLK),
629 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
630 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
631};
632
633static freq_info PM_733JG_90[] = {
634 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
635 FREQ_INFO(1100, 956, INTEL_BUS_CLK),
636 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
637 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
638 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
639 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
640};
641static freq_info PM_733JH_90[] = {
642 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
643 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
644 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
645 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
646 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
647 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
648};
649static freq_info PM_733JI_90[] = {
650 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
651 FREQ_INFO(1100, 924, INTEL_BUS_CLK),
652 FREQ_INFO(1000, 908, INTEL_BUS_CLK),
653 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
654 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
655 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
656};
657static freq_info PM_733JJ_90[] = {
658 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
659 FREQ_INFO(1100, 908, INTEL_BUS_CLK),
660 FREQ_INFO(1000, 892, INTEL_BUS_CLK),
661 FREQ_INFO( 900, 876, INTEL_BUS_CLK),
662 FREQ_INFO( 800, 860, INTEL_BUS_CLK),
663 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
664};
665static freq_info PM_733JK_90[] = {
666 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
667 FREQ_INFO(1100, 892, INTEL_BUS_CLK),
668 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
669 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
670 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
671 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
672};
673static freq_info PM_733JL_90[] = {
674 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
675 FREQ_INFO(1100, 876, INTEL_BUS_CLK),
676 FREQ_INFO(1000, 876, INTEL_BUS_CLK),
677 FREQ_INFO( 900, 860, INTEL_BUS_CLK),
678 FREQ_INFO( 800, 844, INTEL_BUS_CLK),
679 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
680};
681static freq_info PM_733_90[] = {
682 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
683 FREQ_INFO(1100, 940, INTEL_BUS_CLK),
684 FREQ_INFO(1000, 924, INTEL_BUS_CLK),
685 FREQ_INFO( 900, 892, INTEL_BUS_CLK),
686 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
687 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
688 FREQ_INFO( 0, 0, 1),
689};
690static freq_info PM_723_90[] = {
691 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
692 FREQ_INFO(1000, 940, INTEL_BUS_CLK),
693 FREQ_INFO( 900, 908, INTEL_BUS_CLK),
694 FREQ_INFO( 800, 876, INTEL_BUS_CLK),
695 FREQ_INFO( 600, 812, INTEL_BUS_CLK),
696 FREQ_INFO( 0, 0, 1),
697};
698
699/*
700 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
701 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
702 */
703static freq_info C7M_795[] = {
704 /* 2.00GHz Centaur C7-M 533 Mhz FSB */
705 FREQ_INFO_PWR(2000, 1148, 133, 20000),
706 FREQ_INFO_PWR(1867, 1132, 133, 18000),
707 FREQ_INFO_PWR(1600, 1100, 133, 15000),
708 FREQ_INFO_PWR(1467, 1052, 133, 13000),
709 FREQ_INFO_PWR(1200, 1004, 133, 10000),
710 FREQ_INFO_PWR( 800, 844, 133, 7000),
711 FREQ_INFO_PWR( 667, 844, 133, 6000),
712 FREQ_INFO_PWR( 533, 844, 133, 5000),
713 FREQ_INFO(0, 0, 1),
714};
715static freq_info C7M_785[] = {
716 /* 1.80GHz Centaur C7-M 533 Mhz FSB */
717 FREQ_INFO_PWR(1867, 1148, 133, 18000),
718 FREQ_INFO_PWR(1600, 1100, 133, 15000),
719 FREQ_INFO_PWR(1467, 1052, 133, 13000),
720 FREQ_INFO_PWR(1200, 1004, 133, 10000),
721 FREQ_INFO_PWR( 800, 844, 133, 7000),
722 FREQ_INFO_PWR( 667, 844, 133, 6000),
723 FREQ_INFO_PWR( 533, 844, 133, 5000),
724 FREQ_INFO(0, 0, 1),
725};
726static freq_info C7M_765[] = {
727 /* 1.60GHz Centaur C7-M 533 Mhz FSB */
728 FREQ_INFO_PWR(1600, 1084, 133, 15000),
729 FREQ_INFO_PWR(1467, 1052, 133, 13000),
730 FREQ_INFO_PWR(1200, 1004, 133, 10000),
731 FREQ_INFO_PWR( 800, 844, 133, 7000),
732 FREQ_INFO_PWR( 667, 844, 133, 6000),
733 FREQ_INFO_PWR( 533, 844, 133, 5000),
734 FREQ_INFO(0, 0, 1),
735};
736
737static freq_info C7M_794[] = {
738 /* 2.00GHz Centaur C7-M 400 Mhz FSB */
739 FREQ_INFO_PWR(2000, 1148, 100, 20000),
740 FREQ_INFO_PWR(1800, 1132, 100, 18000),
741 FREQ_INFO_PWR(1600, 1100, 100, 15000),
742 FREQ_INFO_PWR(1400, 1052, 100, 13000),
743 FREQ_INFO_PWR(1000, 1004, 100, 10000),
744 FREQ_INFO_PWR( 800, 844, 100, 7000),
745 FREQ_INFO_PWR( 600, 844, 100, 6000),
746 FREQ_INFO_PWR( 400, 844, 100, 5000),
747 FREQ_INFO(0, 0, 1),
748};
749static freq_info C7M_784[] = {
750 /* 1.80GHz Centaur C7-M 400 Mhz FSB */
751 FREQ_INFO_PWR(1800, 1148, 100, 18000),
752 FREQ_INFO_PWR(1600, 1100, 100, 15000),
753 FREQ_INFO_PWR(1400, 1052, 100, 13000),
754 FREQ_INFO_PWR(1000, 1004, 100, 10000),
755 FREQ_INFO_PWR( 800, 844, 100, 7000),
756 FREQ_INFO_PWR( 600, 844, 100, 6000),
757 FREQ_INFO_PWR( 400, 844, 100, 5000),
758 FREQ_INFO(0, 0, 1),
759};
760static freq_info C7M_764[] = {
761 /* 1.60GHz Centaur C7-M 400 Mhz FSB */
762 FREQ_INFO_PWR(1600, 1084, 100, 15000),
763 FREQ_INFO_PWR(1400, 1052, 100, 13000),
764 FREQ_INFO_PWR(1000, 1004, 100, 10000),
765 FREQ_INFO_PWR( 800, 844, 100, 7000),
766 FREQ_INFO_PWR( 600, 844, 100, 6000),
767 FREQ_INFO_PWR( 400, 844, 100, 5000),
768 FREQ_INFO(0, 0, 1),
769};
770static freq_info C7M_754[] = {
771 /* 1.50GHz Centaur C7-M 400 Mhz FSB */
772 FREQ_INFO_PWR(1500, 1004, 100, 12000),
773 FREQ_INFO_PWR(1400, 988, 100, 11000),
774 FREQ_INFO_PWR(1000, 940, 100, 9000),
775 FREQ_INFO_PWR( 800, 844, 100, 7000),
776 FREQ_INFO_PWR( 600, 844, 100, 6000),
777 FREQ_INFO_PWR( 400, 844, 100, 5000),
778 FREQ_INFO(0, 0, 1),
779};
780static freq_info C7M_771[] = {
781 /* 1.20GHz Centaur C7-M 400 Mhz FSB */
782 FREQ_INFO_PWR(1200, 860, 100, 7000),
783 FREQ_INFO_PWR(1000, 860, 100, 6000),
784 FREQ_INFO_PWR( 800, 844, 100, 5500),
785 FREQ_INFO_PWR( 600, 844, 100, 5000),
786 FREQ_INFO_PWR( 400, 844, 100, 4000),
787 FREQ_INFO(0, 0, 1),
788};
789
790static freq_info C7M_775_ULV[] = {
791 /* 1.50GHz Centaur C7-M ULV */
792 FREQ_INFO_PWR(1500, 956, 100, 7500),
793 FREQ_INFO_PWR(1400, 940, 100, 6000),
794 FREQ_INFO_PWR(1000, 860, 100, 5000),
795 FREQ_INFO_PWR( 800, 828, 100, 2800),
796 FREQ_INFO_PWR( 600, 796, 100, 2500),
797 FREQ_INFO_PWR( 400, 796, 100, 2000),
798 FREQ_INFO(0, 0, 1),
799};
800static freq_info C7M_772_ULV[] = {
801 /* 1.20GHz Centaur C7-M ULV */
802 FREQ_INFO_PWR(1200, 844, 100, 5000),
803 FREQ_INFO_PWR(1000, 844, 100, 4000),
804 FREQ_INFO_PWR( 800, 828, 100, 2800),
805 FREQ_INFO_PWR( 600, 796, 100, 2500),
806 FREQ_INFO_PWR( 400, 796, 100, 2000),
807 FREQ_INFO(0, 0, 1),
808};
809static freq_info C7M_779_ULV[] = {
810 /* 1.00GHz Centaur C7-M ULV */
811 FREQ_INFO_PWR(1000, 796, 100, 3500),
812 FREQ_INFO_PWR( 800, 796, 100, 2800),
813 FREQ_INFO_PWR( 600, 796, 100, 2500),
814 FREQ_INFO_PWR( 400, 796, 100, 2000),
815 FREQ_INFO(0, 0, 1),
816};
817static freq_info C7M_770_ULV[] = {
818 /* 1.00GHz Centaur C7-M ULV */
819 FREQ_INFO_PWR(1000, 844, 100, 5000),
820 FREQ_INFO_PWR( 800, 796, 100, 2800),
821 FREQ_INFO_PWR( 600, 796, 100, 2500),
822 FREQ_INFO_PWR( 400, 796, 100, 2000),
823 FREQ_INFO(0, 0, 1),
824};
825
826static cpu_info ESTprocs[] = {
827 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
828 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
829 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
830 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
831 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
832 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
833 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),
834 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK),
835 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK),
836 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK),
837 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK),
838 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK),
839 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK),
840 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK),
841 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK),
842 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK),
843 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK),
844 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK),
845 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK),
846 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK),
847 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK),
848 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK),
849 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK),
850 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK),
851 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK),
852 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK),
853 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK),
854 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK),
855 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK),
856 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK),
857 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK),
858 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK),
859 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK),
860 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK),
861 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK),
862 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK),
863 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK),
864 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK),
865 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK),
866 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK),
867 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK),
868 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK),
869 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK),
870 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK),
871 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK),
872 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK),
873 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK),
874 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK),
875 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK),
876 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
877 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
878 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
879 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
880 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
881 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
882 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
883 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
884
885 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133),
886 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
887 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133),
888 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
889 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133),
890 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
891 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
892 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
893 CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
894 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
895 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
896 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
897 { 0, 0, NULL },
898};
899
900static void est_identify(driver_t *driver, device_t parent);
901static int est_features(driver_t *driver, u_int *features);
902static int est_probe(device_t parent);
903static int est_attach(device_t parent);
904static int est_detach(device_t parent);
905static int est_get_info(device_t dev);
906static int est_acpi_info(device_t dev, freq_info **freqs);
907static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
908static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
909static freq_info *est_get_current(freq_info *freq_list);
910static int est_settings(device_t dev, struct cf_setting *sets, int *count);
911static int est_set(device_t dev, const struct cf_setting *set);
912static int est_get(device_t dev, struct cf_setting *set);
913static int est_type(device_t dev, int *type);
914static int est_set_id16(device_t dev, uint16_t id16, int need_check);
915static void est_get_id16(uint16_t *id16_p);
916
917static device_method_t est_methods[] = {
918 /* Device interface */
919 DEVMETHOD(device_identify, est_identify),
920 DEVMETHOD(device_probe, est_probe),
921 DEVMETHOD(device_attach, est_attach),
922 DEVMETHOD(device_detach, est_detach),
923
924 /* cpufreq interface */
925 DEVMETHOD(cpufreq_drv_set, est_set),
926 DEVMETHOD(cpufreq_drv_get, est_get),
927 DEVMETHOD(cpufreq_drv_type, est_type),
928 DEVMETHOD(cpufreq_drv_settings, est_settings),
929
930 /* ACPI interface */
931 DEVMETHOD(acpi_get_features, est_features),
932
933 {0, 0}
934};
935
936static driver_t est_driver = {
937 "est",
938 est_methods,
939 sizeof(struct est_softc),
940};
941
942static devclass_t est_devclass;
943DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
944
945static int
946est_features(driver_t *driver, u_int *features)
947{
948
949 /* Notify the ACPI CPU that we support direct access to MSRs */
950 *features = ACPI_CAP_PERF_MSRS;
951 return (0);
952}
953
954static void
955est_identify(driver_t *driver, device_t parent)
956{
957 device_t child;
958
959 /* Make sure we're not being doubly invoked. */
960 if (device_find_child(parent, "est", -1) != NULL)
961 return;
962
963 /* Check that CPUID is supported and the vendor is Intel.*/
964 if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
965 cpu_vendor_id != CPU_VENDOR_CENTAUR))
966 return;
967
968 /*
969 * Check if the CPU supports EST.
970 */
971 if (!(cpu_feature2 & CPUID2_EST))
972 return;
973
974 /*
975 * We add a child for each CPU since settings must be performed
976 * on each CPU in the SMP case.
977 */
978 child = BUS_ADD_CHILD(parent, 10, "est", -1);
979 if (child == NULL)
980 device_printf(parent, "add est child failed\n");
981}
982
983static int
984est_probe(device_t dev)
985{
986 device_t perf_dev;
987 uint64_t msr;
988 int error, type;
989
990 if (resource_disabled("est", 0))
991 return (ENXIO);
992
993 /*
994 * If the ACPI perf driver has attached and is not just offering
995 * info, let it manage things.
996 */
997 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
998 if (perf_dev && device_is_attached(perf_dev)) {
999 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
1000 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
1001 return (ENXIO);
1002 }
1003
1004 /* Attempt to enable SpeedStep if not currently enabled. */
1005 msr = rdmsr(MSR_MISC_ENABLE);
1006 if ((msr & MSR_SS_ENABLE) == 0) {
1007 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
1008 if (bootverbose)
1009 device_printf(dev, "enabling SpeedStep\n");
1010
1011 /* Check if the enable failed. */
1012 msr = rdmsr(MSR_MISC_ENABLE);
1013 if ((msr & MSR_SS_ENABLE) == 0) {
1014 device_printf(dev, "failed to enable SpeedStep\n");
1015 return (ENXIO);
1016 }
1017 }
1018
1019 device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
1020 return (0);
1021}
1022
1023static int
1024est_attach(device_t dev)
1025{
1026 struct est_softc *sc;
1027
1028 sc = device_get_softc(dev);
1029 sc->dev = dev;
1030
1031 /* Check CPU for supported settings. */
1032 if (est_get_info(dev))
1033 return (ENXIO);
1034
1035 cpufreq_register(dev);
1036 return (0);
1037}
1038
1039static int
1040est_detach(device_t dev)
1041{
1042 struct est_softc *sc;
1043 int error;
1044
1045 error = cpufreq_unregister(dev);
1046 if (error)
1047 return (error);
1048
1049 sc = device_get_softc(dev);
1050 if (sc->acpi_settings || sc->msr_settings)
1051 free(sc->freq_list, M_DEVBUF);
1052 return (0);
1053}
1054
1055/*
1056 * Probe for supported CPU settings. First, check our static table of
1057 * settings. If no match, try using the ones offered by acpi_perf
1058 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40
1059 * series) export both legacy SMM IO-based access and direct MSR access
1060 * but the direct access specifies invalid values for _PSS.
1061 */
1062static int
1063est_get_info(device_t dev)
1064{
1065 struct est_softc *sc;
1066 uint64_t msr;
1067 int error;
1068
1069 sc = device_get_softc(dev);
1070 msr = rdmsr(MSR_PERF_STATUS);
1071 error = est_table_info(dev, msr, &sc->freq_list);
1072 if (error)
1073 error = est_acpi_info(dev, &sc->freq_list);
1074 if (error)
1075 error = est_msr_info(dev, msr, &sc->freq_list);
1076
1077 if (error) {
1078 printf(
1079 "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
1080 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
1081 return (ENXIO);
1082 }
1083
1084 return (0);
1085}
1086
1087static int
1088est_acpi_info(device_t dev, freq_info **freqs)
1089{
1090 struct est_softc *sc;
1091 struct cf_setting *sets;
1092 freq_info *table;
1093 device_t perf_dev;
1094 int count, error, i, j;
1095 uint16_t saved_id16;
1096
1097 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
1098 if (perf_dev == NULL || !device_is_attached(perf_dev))
1099 return (ENXIO);
1100
1101 /* Fetch settings from acpi_perf. */
1102 sc = device_get_softc(dev);
1103 table = NULL;
1104 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
1105 if (sets == NULL)
1106 return (ENOMEM);
1107 count = MAX_SETTINGS;
1108 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
1109 if (error)
1110 goto out;
1111
1112 /* Parse settings into our local table format. */
1113 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
1114 if (table == NULL) {
1115 error = ENOMEM;
1116 goto out;
1117 }
1118 est_get_id16(&saved_id16);
1119 for (i = 0, j = 0; i < count; i++) {
1120 /*
1121 * Confirm id16 value is correct.
1122 */
1123 if (sets[i].freq > 0) {
1124 error = est_set_id16(dev, sets[i].spec[0], 1);
1125 if (error != 0) {
1126 if (bootverbose)
1127 device_printf(dev, "Invalid freq %u, "
1128 "ignored.\n", sets[i].freq);
1129 } else {
1130 table[j].freq = sets[i].freq;
1131 table[j].volts = sets[i].volts;
1132 table[j].id16 = sets[i].spec[0];
1133 table[j].power = sets[i].power;
1134 ++j;
1135 }
1136 }
1137 }
1138 /* restore saved setting */
1139 est_set_id16(dev, saved_id16, 0);
1140
1141 /* Mark end of table with a terminator. */
1142 bzero(&table[j], sizeof(freq_info));
1143
1144 sc->acpi_settings = TRUE;
1145 *freqs = table;
1146 error = 0;
1147
1148out:
1149 if (sets)
1150 free(sets, M_TEMP);
1151 if (error && table)
1152 free(table, M_DEVBUF);
1153 return (error);
1154}
1155
1156static int
1157est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
1158{
1159 cpu_info *p;
1160 uint32_t id;
1161
1162 /* Find a table which matches (vendor, id32). */
1163 id = msr >> 32;
1164 for (p = ESTprocs; p->id32 != 0; p++) {
1165 if (p->vendor_id == cpu_vendor_id && p->id32 == id)
1166 break;
1167 }
1168 if (p->id32 == 0)
1169 return (EOPNOTSUPP);
1170
1171 /* Make sure the current setpoint is valid. */
1172 if (est_get_current(p->freqtab) == NULL) {
1173 device_printf(dev, "current setting not found in table\n");
1174 return (EOPNOTSUPP);
1175 }
1176
1177 *freqs = p->freqtab;
1178 return (0);
1179}
1180
1181static int
1182bus_speed_ok(int bus)
1183{
1184
1185 switch (bus) {
1186 case 100:
1187 case 133:
1188 case 333:
1189 return (1);
1190 default:
1191 return (0);
1192 }
1193}
1194
1195/*
1196 * Flesh out a simple rate table containing the high and low frequencies
1197 * based on the current clock speed and the upper 32 bits of the MSR.
1198 */
1199static int
1200est_msr_info(device_t dev, uint64_t msr, freq_info **freqs)
1201{
1202 struct est_softc *sc;
1203 freq_info *fp;
1204 int bus, freq, volts;
1205 uint16_t id;
1206
1207 if (!msr_info_enabled)
1208 return (EOPNOTSUPP);
1209
1210 /* Figure out the bus clock. */
1211 freq = tsc_freq / 1000000;
1212 id = msr >> 32;
1213 bus = freq / (id >> 8);
1214 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus);
1215 if (!bus_speed_ok(bus)) {
1216 /* We may be running on the low frequency. */
1217 id = msr >> 48;
1218 bus = freq / (id >> 8);
1219 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus);
1220 if (!bus_speed_ok(bus))
1221 return (EOPNOTSUPP);
1222
1223 /* Calculate high frequency. */
1224 id = msr >> 32;
1225 freq = ((id >> 8) & 0xff) * bus;
1226 }
1227
1228 /* Fill out a new freq table containing just the high and low freqs. */
1229 sc = device_get_softc(dev);
1230 fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO);
1231
1232 /* First, the high frequency. */
1233 volts = id & 0xff;
1234 if (volts != 0) {
1235 volts <<= 4;
1236 volts += 700;
1237 }
1238 fp[0].freq = freq;
1239 fp[0].volts = volts;
1240 fp[0].id16 = id;
1241 fp[0].power = CPUFREQ_VAL_UNKNOWN;
1242 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq,
1243 volts);
1244
1245 /* Second, the low frequency. */
1246 id = msr >> 48;
1247 freq = ((id >> 8) & 0xff) * bus;
1248 volts = id & 0xff;
1249 if (volts != 0) {
1250 volts <<= 4;
1251 volts += 700;
1252 }
1253 fp[1].freq = freq;
1254 fp[1].volts = volts;
1255 fp[1].id16 = id;
1256 fp[1].power = CPUFREQ_VAL_UNKNOWN;
1257 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq,
1258 volts);
1259
1260 /* Table is already terminated due to M_ZERO. */
1261 sc->msr_settings = TRUE;
1262 *freqs = fp;
1263 return (0);
1264}
1265
1266static void
1267est_get_id16(uint16_t *id16_p)
1268{
1269 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;
1270}
1271
1272static int
1273est_set_id16(device_t dev, uint16_t id16, int need_check)
1274{
1275 uint64_t msr;
1276 uint16_t new_id16;
1277 int ret = 0;
1278
1279 /* Read the current register, mask out the old, set the new id. */
1280 msr = rdmsr(MSR_PERF_CTL);
1281 msr = (msr & ~0xffff) | id16;
1282 wrmsr(MSR_PERF_CTL, msr);
1283
1284 /* Wait a short while for the new setting. XXX Is this necessary? */
1285 DELAY(EST_TRANS_LAT);
1286
1287 if (need_check) {
1288 est_get_id16(&new_id16);
1289 if (new_id16 != id16) {
1290 if (bootverbose)
1291 device_printf(dev, "Invalid id16 (set, cur) "
1292 "= (%u, %u)\n", id16, new_id16);
1293 ret = ENXIO;
1294 }
1295 }
1296 return (ret);
1297}
1298
1299static freq_info *
1300est_get_current(freq_info *freq_list)
1301{
1302 freq_info *f;
1303 int i;
1304 uint16_t id16;
1305
1306 /*
1307 * Try a few times to get a valid value. Sometimes, if the CPU
1308 * is in the middle of an asynchronous transition (i.e., P4TCC),
1309 * we get a temporary invalid result.
1310 */
1311 for (i = 0; i < 5; i++) {
1312 est_get_id16(&id16);
1313 for (f = freq_list; f->id16 != 0; f++) {
1314 if (f->id16 == id16)
1315 return (f);
1316 }
1317 DELAY(100);
1318 }
1319 return (NULL);
1320}
1321
1322static int
1323est_settings(device_t dev, struct cf_setting *sets, int *count)
1324{
1325 struct est_softc *sc;
1326 freq_info *f;
1327 int i;
1328
1329 sc = device_get_softc(dev);
1330 if (*count < EST_MAX_SETTINGS)
1331 return (E2BIG);
1332
1333 i = 0;
1334 for (f = sc->freq_list; f->freq != 0; f++, i++) {
1335 sets[i].freq = f->freq;
1336 sets[i].volts = f->volts;
1337 sets[i].power = f->power;
1338 sets[i].lat = EST_TRANS_LAT;
1339 sets[i].dev = dev;
1340 }
1341 *count = i;
1342
1343 return (0);
1344}
1345
1346static int
1347est_set(device_t dev, const struct cf_setting *set)
1348{
1349 struct est_softc *sc;
1350 freq_info *f;
1351
1352 /* Find the setting matching the requested one. */
1353 sc = device_get_softc(dev);
1354 for (f = sc->freq_list; f->freq != 0; f++) {
1355 if (f->freq == set->freq)
1356 break;
1357 }
1358 if (f->freq == 0)
1359 return (EINVAL);
1360
1361 /* Read the current register, mask out the old, set the new id. */
1362 est_set_id16(dev, f->id16, 0);
1363
1364 return (0);
1365}
1366
1367static int
1368est_get(device_t dev, struct cf_setting *set)
1369{
1370 struct est_softc *sc;
1371 freq_info *f;
1372
1373 sc = device_get_softc(dev);
1374 f = est_get_current(sc->freq_list);
1375 if (f == NULL)
1376 return (ENXIO);
1377
1378 set->freq = f->freq;
1379 set->volts = f->volts;
1380 set->power = f->power;
1381 set->lat = EST_TRANS_LAT;
1382 set->dev = dev;
1383 return (0);
1384}
1385
1386static int
1387est_type(device_t dev, int *type)
1388{
1389
1390 if (type == NULL)
1391 return (EINVAL);
1392
1393 *type = CPUFREQ_TYPE_ABSOLUTE;
1394 return (0);
1395}