56
57/*
58 * SBus support.
59 */
60
61#include <sys/param.h>
62#include <sys/systm.h>
63#include <sys/bus.h>
64#include <sys/kernel.h>
65#include <sys/malloc.h>
66#include <sys/module.h>
67#include <sys/pcpu.h>
68#include <sys/queue.h>
69#include <sys/reboot.h>
70#include <sys/rman.h>
71
72#include <dev/ofw/ofw_bus.h>
73#include <dev/ofw/ofw_bus_subr.h>
74#include <dev/ofw/openfirm.h>
75
76#include <machine/bus.h>
77#include <machine/bus_common.h>
78#include <machine/bus_private.h>
79#include <machine/iommureg.h>
80#include <machine/iommuvar.h>
81#include <machine/resource.h>
82
83#include <sparc64/sbus/ofw_sbus.h>
84#include <sparc64/sbus/sbusreg.h>
85#include <sparc64/sbus/sbusvar.h>
86
87struct sbus_devinfo {
88 int sdi_burstsz;
89 int sdi_clockfreq;
90 int sdi_slot;
91
92 struct ofw_bus_devinfo sdi_obdinfo;
93 struct resource_list sdi_rl;
94};
95
96/* Range descriptor, allocated for each sc_range. */
97struct sbus_rd {
98 bus_addr_t rd_poffset;
99 bus_addr_t rd_pend;
100 int rd_slot;
101 bus_addr_t rd_coffset;
102 bus_addr_t rd_cend;
103 struct rman rd_rman;
104 bus_space_handle_t rd_bushandle;
105 struct resource *rd_res;
106};
107
108struct sbus_softc {
109 device_t sc_dev;
110 bus_dma_tag_t sc_cdmatag;
111 int sc_clockfreq; /* clock frequency (in Hz) */
112 int sc_nrange;
113 struct sbus_rd *sc_rd;
114 int sc_burst; /* burst transfer sizes supp. */
115
116 struct resource *sc_sysio_res;
117 int sc_ign; /* IGN for this sysio */
118 struct iommu_state sc_is; /* IOMMU state (iommuvar.h) */
119
120 struct resource *sc_ot_ires;
121 void *sc_ot_ihand;
122 struct resource *sc_pf_ires;
123 void *sc_pf_ihand;
124};
125
126#define SYSIO_READ8(sc, off) \
127 bus_read_8((sc)->sc_sysio_res, (off))
128#define SYSIO_WRITE8(sc, off, v) \
129 bus_write_8((sc)->sc_sysio_res, (off), (v))
130
131static device_probe_t sbus_probe;
132static device_attach_t sbus_attach;
133static bus_print_child_t sbus_print_child;
134static bus_probe_nomatch_t sbus_probe_nomatch;
135static bus_read_ivar_t sbus_read_ivar;
136static bus_get_resource_list_t sbus_get_resource_list;
137static bus_setup_intr_t sbus_setup_intr;
138static bus_alloc_resource_t sbus_alloc_resource;
139static bus_activate_resource_t sbus_activate_resource;
140static bus_adjust_resource_t sbus_adjust_resource;
141static bus_release_resource_t sbus_release_resource;
142static bus_get_dma_tag_t sbus_get_dma_tag;
143static ofw_bus_get_devinfo_t sbus_get_devinfo;
144
145static int sbus_inlist(const char *, const char *const *);
146static struct sbus_devinfo * sbus_setup_dinfo(device_t, struct sbus_softc *,
147 phandle_t);
148static void sbus_destroy_dinfo(struct sbus_devinfo *);
149static void sbus_intr_enable(void *);
150static void sbus_intr_disable(void *);
151static void sbus_intr_assign(void *);
152static void sbus_intr_clear(void *);
153static int sbus_find_intrmap(struct sbus_softc *, u_int, bus_addr_t *,
154 bus_addr_t *);
155static driver_intr_t sbus_overtemp;
156static driver_intr_t sbus_pwrfail;
157static int sbus_print_res(struct sbus_devinfo *);
158
159static device_method_t sbus_methods[] = {
160 /* Device interface */
161 DEVMETHOD(device_probe, sbus_probe),
162 DEVMETHOD(device_attach, sbus_attach),
163 DEVMETHOD(device_shutdown, bus_generic_shutdown),
164 DEVMETHOD(device_suspend, bus_generic_suspend),
165 DEVMETHOD(device_resume, bus_generic_resume),
166
167 /* Bus interface */
168 DEVMETHOD(bus_print_child, sbus_print_child),
169 DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch),
170 DEVMETHOD(bus_read_ivar, sbus_read_ivar),
171 DEVMETHOD(bus_alloc_resource, sbus_alloc_resource),
172 DEVMETHOD(bus_activate_resource, sbus_activate_resource),
173 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
174 DEVMETHOD(bus_adjust_resource, sbus_adjust_resource),
175 DEVMETHOD(bus_release_resource, sbus_release_resource),
176 DEVMETHOD(bus_setup_intr, sbus_setup_intr),
177 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
178 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
179 DEVMETHOD(bus_get_resource_list, sbus_get_resource_list),
180 DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str),
181 DEVMETHOD(bus_get_dma_tag, sbus_get_dma_tag),
182
183 /* ofw_bus interface */
184 DEVMETHOD(ofw_bus_get_devinfo, sbus_get_devinfo),
185 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
186 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
187 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
188 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
189 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
190
| 56
57/*
58 * SBus support.
59 */
60
61#include <sys/param.h>
62#include <sys/systm.h>
63#include <sys/bus.h>
64#include <sys/kernel.h>
65#include <sys/malloc.h>
66#include <sys/module.h>
67#include <sys/pcpu.h>
68#include <sys/queue.h>
69#include <sys/reboot.h>
70#include <sys/rman.h>
71
72#include <dev/ofw/ofw_bus.h>
73#include <dev/ofw/ofw_bus_subr.h>
74#include <dev/ofw/openfirm.h>
75
76#include <machine/bus.h>
77#include <machine/bus_common.h>
78#include <machine/bus_private.h>
79#include <machine/iommureg.h>
80#include <machine/iommuvar.h>
81#include <machine/resource.h>
82
83#include <sparc64/sbus/ofw_sbus.h>
84#include <sparc64/sbus/sbusreg.h>
85#include <sparc64/sbus/sbusvar.h>
86
87struct sbus_devinfo {
88 int sdi_burstsz;
89 int sdi_clockfreq;
90 int sdi_slot;
91
92 struct ofw_bus_devinfo sdi_obdinfo;
93 struct resource_list sdi_rl;
94};
95
96/* Range descriptor, allocated for each sc_range. */
97struct sbus_rd {
98 bus_addr_t rd_poffset;
99 bus_addr_t rd_pend;
100 int rd_slot;
101 bus_addr_t rd_coffset;
102 bus_addr_t rd_cend;
103 struct rman rd_rman;
104 bus_space_handle_t rd_bushandle;
105 struct resource *rd_res;
106};
107
108struct sbus_softc {
109 device_t sc_dev;
110 bus_dma_tag_t sc_cdmatag;
111 int sc_clockfreq; /* clock frequency (in Hz) */
112 int sc_nrange;
113 struct sbus_rd *sc_rd;
114 int sc_burst; /* burst transfer sizes supp. */
115
116 struct resource *sc_sysio_res;
117 int sc_ign; /* IGN for this sysio */
118 struct iommu_state sc_is; /* IOMMU state (iommuvar.h) */
119
120 struct resource *sc_ot_ires;
121 void *sc_ot_ihand;
122 struct resource *sc_pf_ires;
123 void *sc_pf_ihand;
124};
125
126#define SYSIO_READ8(sc, off) \
127 bus_read_8((sc)->sc_sysio_res, (off))
128#define SYSIO_WRITE8(sc, off, v) \
129 bus_write_8((sc)->sc_sysio_res, (off), (v))
130
131static device_probe_t sbus_probe;
132static device_attach_t sbus_attach;
133static bus_print_child_t sbus_print_child;
134static bus_probe_nomatch_t sbus_probe_nomatch;
135static bus_read_ivar_t sbus_read_ivar;
136static bus_get_resource_list_t sbus_get_resource_list;
137static bus_setup_intr_t sbus_setup_intr;
138static bus_alloc_resource_t sbus_alloc_resource;
139static bus_activate_resource_t sbus_activate_resource;
140static bus_adjust_resource_t sbus_adjust_resource;
141static bus_release_resource_t sbus_release_resource;
142static bus_get_dma_tag_t sbus_get_dma_tag;
143static ofw_bus_get_devinfo_t sbus_get_devinfo;
144
145static int sbus_inlist(const char *, const char *const *);
146static struct sbus_devinfo * sbus_setup_dinfo(device_t, struct sbus_softc *,
147 phandle_t);
148static void sbus_destroy_dinfo(struct sbus_devinfo *);
149static void sbus_intr_enable(void *);
150static void sbus_intr_disable(void *);
151static void sbus_intr_assign(void *);
152static void sbus_intr_clear(void *);
153static int sbus_find_intrmap(struct sbus_softc *, u_int, bus_addr_t *,
154 bus_addr_t *);
155static driver_intr_t sbus_overtemp;
156static driver_intr_t sbus_pwrfail;
157static int sbus_print_res(struct sbus_devinfo *);
158
159static device_method_t sbus_methods[] = {
160 /* Device interface */
161 DEVMETHOD(device_probe, sbus_probe),
162 DEVMETHOD(device_attach, sbus_attach),
163 DEVMETHOD(device_shutdown, bus_generic_shutdown),
164 DEVMETHOD(device_suspend, bus_generic_suspend),
165 DEVMETHOD(device_resume, bus_generic_resume),
166
167 /* Bus interface */
168 DEVMETHOD(bus_print_child, sbus_print_child),
169 DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch),
170 DEVMETHOD(bus_read_ivar, sbus_read_ivar),
171 DEVMETHOD(bus_alloc_resource, sbus_alloc_resource),
172 DEVMETHOD(bus_activate_resource, sbus_activate_resource),
173 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
174 DEVMETHOD(bus_adjust_resource, sbus_adjust_resource),
175 DEVMETHOD(bus_release_resource, sbus_release_resource),
176 DEVMETHOD(bus_setup_intr, sbus_setup_intr),
177 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
178 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
179 DEVMETHOD(bus_get_resource_list, sbus_get_resource_list),
180 DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str),
181 DEVMETHOD(bus_get_dma_tag, sbus_get_dma_tag),
182
183 /* ofw_bus interface */
184 DEVMETHOD(ofw_bus_get_devinfo, sbus_get_devinfo),
185 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
186 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
187 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
188 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
189 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
190
|
192};
193
194static driver_t sbus_driver = {
195 "sbus",
196 sbus_methods,
197 sizeof(struct sbus_softc),
198};
199
200static devclass_t sbus_devclass;
201
202EARLY_DRIVER_MODULE(sbus, nexus, sbus_driver, sbus_devclass, 0, 0,
203 BUS_PASS_BUS);
204MODULE_DEPEND(sbus, nexus, 1, 1, 1);
205MODULE_VERSION(sbus, 1);
206
207#define OFW_SBUS_TYPE "sbus"
208#define OFW_SBUS_NAME "sbus"
209
210static const struct intr_controller sbus_ic = {
211 sbus_intr_enable,
212 sbus_intr_disable,
213 sbus_intr_assign,
214 sbus_intr_clear
215};
216
217struct sbus_icarg {
218 struct sbus_softc *sica_sc;
219 bus_addr_t sica_map;
220 bus_addr_t sica_clr;
221};
222
223static const char *const sbus_order_first[] = {
224 "auxio",
225 "dma",
226 NULL
227};
228
229static int
230sbus_inlist(const char *name, const char *const *list)
231{
232 int i;
233
234 if (name == NULL)
235 return (0);
236 for (i = 0; list[i] != NULL; i++) {
237 if (strcmp(name, list[i]) == 0)
238 return (1);
239 }
240 return (0);
241}
242
243static int
244sbus_probe(device_t dev)
245{
246 const char *t;
247
248 t = ofw_bus_get_type(dev);
249 if (((t == NULL || strcmp(t, OFW_SBUS_TYPE) != 0)) &&
250 strcmp(ofw_bus_get_name(dev), OFW_SBUS_NAME) != 0)
251 return (ENXIO);
252 device_set_desc(dev, "U2S UPA-SBus bridge");
253 return (0);
254}
255
256static int
257sbus_attach(device_t dev)
258{
259 struct sbus_softc *sc;
260 struct sbus_devinfo *sdi;
261 struct sbus_icarg *sica;
262 struct sbus_ranges *range;
263 struct resource *res;
264 struct resource_list *rl;
265 device_t cdev;
266 bus_addr_t intrclr, intrmap, phys;
267 bus_size_t size;
268 u_long vec;
269 phandle_t child, node;
270 uint32_t prop;
271 int i, j;
272
273 sc = device_get_softc(dev);
274 sc->sc_dev = dev;
275 node = ofw_bus_get_node(dev);
276
277 i = 0;
278 sc->sc_sysio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
279 RF_ACTIVE);
280 if (sc->sc_sysio_res == NULL)
281 panic("%s: cannot allocate device memory", __func__);
282
283 if (OF_getprop(node, "interrupts", &prop, sizeof(prop)) == -1)
284 panic("%s: cannot get IGN", __func__);
285 sc->sc_ign = INTIGN(prop);
286
287 /*
288 * Record clock frequency for synchronous SCSI.
289 * IS THIS THE CORRECT DEFAULT??
290 */
291 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
292 prop = 25000000;
293 sc->sc_clockfreq = prop;
294 prop /= 1000;
295 device_printf(dev, "clock %d.%03d MHz\n", prop / 1000, prop % 1000);
296
297 /*
298 * Collect address translations from the OBP.
299 */
300 if ((sc->sc_nrange = OF_getprop_alloc(node, "ranges",
301 sizeof(*range), (void **)&range)) == -1) {
302 panic("%s: error getting ranges property", __func__);
303 }
304 sc->sc_rd = malloc(sizeof(*sc->sc_rd) * sc->sc_nrange, M_DEVBUF,
305 M_NOWAIT | M_ZERO);
306 if (sc->sc_rd == NULL)
307 panic("%s: cannot allocate rmans", __func__);
308 /*
309 * Preallocate all space that the SBus bridge decodes, so that nothing
310 * else gets in the way; set up rmans etc.
311 */
312 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
313 for (i = 0; i < sc->sc_nrange; i++) {
314 phys = range[i].poffset | ((bus_addr_t)range[i].pspace << 32);
315 size = range[i].size;
316 sc->sc_rd[i].rd_slot = range[i].cspace;
317 sc->sc_rd[i].rd_coffset = range[i].coffset;
318 sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size;
319 j = resource_list_add_next(rl, SYS_RES_MEMORY, phys,
320 phys + size - 1, size);
321 if ((res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &j,
322 RF_ACTIVE)) == NULL)
323 panic("%s: cannot allocate decoded range", __func__);
324 sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res);
325 sc->sc_rd[i].rd_rman.rm_type = RMAN_ARRAY;
326 sc->sc_rd[i].rd_rman.rm_descr = "SBus Device Memory";
327 if (rman_init(&sc->sc_rd[i].rd_rman) != 0 ||
328 rman_manage_region(&sc->sc_rd[i].rd_rman, 0, size) != 0)
329 panic("%s: failed to set up memory rman", __func__);
330 sc->sc_rd[i].rd_poffset = phys;
331 sc->sc_rd[i].rd_pend = phys + size;
332 sc->sc_rd[i].rd_res = res;
333 }
334 free(range, M_OFWPROP);
335
336 /*
337 * Get the SBus burst transfer size if burst transfers are supported.
338 */
339 if (OF_getprop(node, "up-burst-sizes", &sc->sc_burst,
340 sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0)
341 sc->sc_burst =
342 (SBUS_BURST64_DEF << SBUS_BURST64_SHIFT) | SBUS_BURST_DEF;
343
344 /* initalise the IOMMU */
345
346 /* punch in our copies */
347 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(SBUS_IOMMU_BITS);
348 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_sysio_res);
349 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_sysio_res);
350 sc->sc_is.is_iommu = SBR_IOMMU;
351 sc->sc_is.is_dtag = SBR_IOMMU_TLB_TAG_DIAG;
352 sc->sc_is.is_ddram = SBR_IOMMU_TLB_DATA_DIAG;
353 sc->sc_is.is_dqueue = SBR_IOMMU_QUEUE_DIAG;
354 sc->sc_is.is_dva = SBR_IOMMU_SVADIAG;
355 sc->sc_is.is_dtcmp = 0;
356 sc->sc_is.is_sb[0] = SBR_STRBUF;
357 sc->sc_is.is_sb[1] = 0;
358
359 /*
360 * Note: the SBus IOMMU ignores the high bits of an address, so a NULL
361 * DMA pointer will be translated by the first page of the IOTSB.
362 * To detect bugs we'll allocate and ignore the first entry.
363 */
364 iommu_init(device_get_nameunit(dev), &sc->sc_is, 3, -1, 1);
365
366 /* Create the DMA tag. */
367 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
368 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr,
369 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_cdmatag) != 0)
370 panic("%s: bus_dma_tag_create failed", __func__);
371 /* Customize the tag. */
372 sc->sc_cdmatag->dt_cookie = &sc->sc_is;
373 sc->sc_cdmatag->dt_mt = &iommu_dma_methods;
374
375 /*
376 * Hunt through all the interrupt mapping regs and register our
377 * interrupt controller for the corresponding interrupt vectors.
378 * We do this early in order to be able to catch stray interrupts.
379 */
380 for (i = 0; i <= SBUS_MAX_INO; i++) {
381 if (sbus_find_intrmap(sc, i, &intrmap, &intrclr) == 0)
382 continue;
383 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
384 if (sica == NULL)
385 panic("%s: could not allocate interrupt controller "
386 "argument", __func__);
387 sica->sica_sc = sc;
388 sica->sica_map = intrmap;
389 sica->sica_clr = intrclr;
390#ifdef SBUS_DEBUG
391 device_printf(dev,
392 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
393 i, (i & INTMAP_OBIO_MASK) == 0 ? "SBus slot" : "OBIO",
394 (u_long)intrmap, (u_long)SYSIO_READ8(sc, intrmap),
395 (u_long)intrclr);
396#endif
397 j = intr_controller_register(INTMAP_VEC(sc->sc_ign, i),
398 &sbus_ic, sica);
399 if (j != 0)
400 device_printf(dev, "could not register interrupt "
401 "controller for INO %d (%d)\n", i, j);
402 }
403
404 /* Enable the over-temperature and power-fail interrupts. */
405 i = 4;
406 sc->sc_ot_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
407 RF_ACTIVE);
408 if (sc->sc_ot_ires == NULL ||
409 INTIGN(vec = rman_get_start(sc->sc_ot_ires)) != sc->sc_ign ||
410 INTVEC(SYSIO_READ8(sc, SBR_THERM_INT_MAP)) != vec ||
411 intr_vectors[vec].iv_ic != &sbus_ic ||
412 bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_BRIDGE,
413 NULL, sbus_overtemp, sc, &sc->sc_ot_ihand) != 0)
414 panic("%s: failed to set up temperature interrupt", __func__);
415 i = 3;
416 sc->sc_pf_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
417 RF_ACTIVE);
418 if (sc->sc_pf_ires == NULL ||
419 INTIGN(vec = rman_get_start(sc->sc_pf_ires)) != sc->sc_ign ||
420 INTVEC(SYSIO_READ8(sc, SBR_POWER_INT_MAP)) != vec ||
421 intr_vectors[vec].iv_ic != &sbus_ic ||
422 bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_BRIDGE,
423 NULL, sbus_pwrfail, sc, &sc->sc_pf_ihand) != 0)
424 panic("%s: failed to set up power fail interrupt", __func__);
425
426 /* Initialize the counter-timer. */
427 sparc64_counter_init(device_get_nameunit(dev),
428 rman_get_bustag(sc->sc_sysio_res),
429 rman_get_bushandle(sc->sc_sysio_res), SBR_TC0);
430
431 /*
432 * Loop through ROM children, fixing any relative addresses
433 * and then configuring each device.
434 */
435 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
436 if ((sdi = sbus_setup_dinfo(dev, sc, child)) == NULL)
437 continue;
438 /*
439 * For devices where there are variants that are actually
440 * split into two SBus devices (as opposed to the first
441 * half of the device being a SBus device and the second
442 * half hanging off of the first one) like 'auxio' and
443 * 'SUNW,fdtwo' or 'dma' and 'esp' probe the SBus device
444 * which is a prerequisite to the driver attaching to the
445 * second one with a lower order. Saves us from dealing
446 * with different probe orders in the respective device
447 * drivers which generally is more hackish.
448 */
449 cdev = device_add_child_ordered(dev, (OF_child(child) == 0 &&
450 sbus_inlist(sdi->sdi_obdinfo.obd_name, sbus_order_first)) ?
451 SBUS_ORDER_FIRST : SBUS_ORDER_NORMAL, NULL, -1);
452 if (cdev == NULL) {
453 device_printf(dev,
454 "<%s>: device_add_child_ordered failed\n",
455 sdi->sdi_obdinfo.obd_name);
456 sbus_destroy_dinfo(sdi);
457 continue;
458 }
459 device_set_ivars(cdev, sdi);
460 }
461 return (bus_generic_attach(dev));
462}
463
464static struct sbus_devinfo *
465sbus_setup_dinfo(device_t dev, struct sbus_softc *sc, phandle_t node)
466{
467 struct sbus_devinfo *sdi;
468 struct sbus_regs *reg;
469 u_int32_t base, iv, *intr;
470 int i, nreg, nintr, slot, rslot;
471
472 sdi = malloc(sizeof(*sdi), M_DEVBUF, M_ZERO | M_WAITOK);
473 if (ofw_bus_gen_setup_devinfo(&sdi->sdi_obdinfo, node) != 0) {
474 free(sdi, M_DEVBUF);
475 return (NULL);
476 }
477 resource_list_init(&sdi->sdi_rl);
478 slot = -1;
479 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®);
480 if (nreg == -1) {
481 if (sdi->sdi_obdinfo.obd_type == NULL ||
482 strcmp(sdi->sdi_obdinfo.obd_type, "hierarchical") != 0) {
483 device_printf(dev, "<%s>: incomplete\n",
484 sdi->sdi_obdinfo.obd_name);
485 goto fail;
486 }
487 } else {
488 for (i = 0; i < nreg; i++) {
489 base = reg[i].sbr_offset;
490 if (SBUS_ABS(base)) {
491 rslot = SBUS_ABS_TO_SLOT(base);
492 base = SBUS_ABS_TO_OFFSET(base);
493 } else
494 rslot = reg[i].sbr_slot;
495 if (slot != -1 && slot != rslot) {
496 device_printf(dev, "<%s>: multiple slots\n",
497 sdi->sdi_obdinfo.obd_name);
498 free(reg, M_OFWPROP);
499 goto fail;
500 }
501 slot = rslot;
502
503 resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i,
504 base, base + reg[i].sbr_size, reg[i].sbr_size);
505 }
506 free(reg, M_OFWPROP);
507 }
508 sdi->sdi_slot = slot;
509
510 /*
511 * The `interrupts' property contains the SBus interrupt level.
512 */
513 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr),
514 (void **)&intr);
515 if (nintr != -1) {
516 for (i = 0; i < nintr; i++) {
517 iv = intr[i];
518 /*
519 * SBus card devices need the slot number encoded into
520 * the vector as this is generally not done.
521 */
522 if ((iv & INTMAP_OBIO_MASK) == 0)
523 iv |= slot << 3;
524 iv = INTMAP_VEC(sc->sc_ign, iv);
525 resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i,
526 iv, iv, 1);
527 }
528 free(intr, M_OFWPROP);
529 }
530 if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz,
531 sizeof(sdi->sdi_burstsz)) == -1)
532 sdi->sdi_burstsz = sc->sc_burst;
533 else
534 sdi->sdi_burstsz &= sc->sc_burst;
535 if (OF_getprop(node, "clock-frequency", &sdi->sdi_clockfreq,
536 sizeof(sdi->sdi_clockfreq)) == -1)
537 sdi->sdi_clockfreq = sc->sc_clockfreq;
538
539 return (sdi);
540
541fail:
542 sbus_destroy_dinfo(sdi);
543 return (NULL);
544}
545
546static void
547sbus_destroy_dinfo(struct sbus_devinfo *dinfo)
548{
549
550 resource_list_free(&dinfo->sdi_rl);
551 ofw_bus_gen_destroy_devinfo(&dinfo->sdi_obdinfo);
552 free(dinfo, M_DEVBUF);
553}
554
555static int
556sbus_print_child(device_t dev, device_t child)
557{
558 int rv;
559
560 rv = bus_print_child_header(dev, child);
561 rv += sbus_print_res(device_get_ivars(child));
562 rv += bus_print_child_footer(dev, child);
563 return (rv);
564}
565
566static void
567sbus_probe_nomatch(device_t dev, device_t child)
568{
569 const char *type;
570
571 device_printf(dev, "<%s>", ofw_bus_get_name(child));
572 sbus_print_res(device_get_ivars(child));
573 type = ofw_bus_get_type(child);
574 printf(" type %s (no driver attached)\n",
575 type != NULL ? type : "unknown");
576}
577
578static int
579sbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
580{
581 struct sbus_softc *sc;
582 struct sbus_devinfo *dinfo;
583
584 sc = device_get_softc(dev);
585 if ((dinfo = device_get_ivars(child)) == NULL)
586 return (ENOENT);
587 switch (which) {
588 case SBUS_IVAR_BURSTSZ:
589 *result = dinfo->sdi_burstsz;
590 break;
591 case SBUS_IVAR_CLOCKFREQ:
592 *result = dinfo->sdi_clockfreq;
593 break;
594 case SBUS_IVAR_IGN:
595 *result = sc->sc_ign;
596 break;
597 case SBUS_IVAR_SLOT:
598 *result = dinfo->sdi_slot;
599 break;
600 default:
601 return (ENOENT);
602 }
603 return (0);
604}
605
606static struct resource_list *
607sbus_get_resource_list(device_t dev, device_t child)
608{
609 struct sbus_devinfo *sdi;
610
611 sdi = device_get_ivars(child);
612 return (&sdi->sdi_rl);
613}
614
615static void
616sbus_intr_enable(void *arg)
617{
618 struct intr_vector *iv = arg;
619 struct sbus_icarg *sica = iv->iv_icarg;
620
621 SYSIO_WRITE8(sica->sica_sc, sica->sica_map,
622 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
623}
624
625static void
626sbus_intr_disable(void *arg)
627{
628 struct intr_vector *iv = arg;
629 struct sbus_icarg *sica = iv->iv_icarg;
630
631 SYSIO_WRITE8(sica->sica_sc, sica->sica_map, iv->iv_vec);
632}
633
634static void
635sbus_intr_assign(void *arg)
636{
637 struct intr_vector *iv = arg;
638 struct sbus_icarg *sica = iv->iv_icarg;
639
640 SYSIO_WRITE8(sica->sica_sc, sica->sica_map, INTMAP_TID(
641 SYSIO_READ8(sica->sica_sc, sica->sica_map), iv->iv_mid));
642}
643
644static void
645sbus_intr_clear(void *arg)
646{
647 struct intr_vector *iv = arg;
648 struct sbus_icarg *sica = iv->iv_icarg;
649
650 SYSIO_WRITE8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE);
651}
652
653static int
654sbus_find_intrmap(struct sbus_softc *sc, u_int ino, bus_addr_t *intrmapptr,
655 bus_addr_t *intrclrptr)
656{
657 bus_addr_t intrclr, intrmap;
658 int i;
659
660 if (ino > SBUS_MAX_INO) {
661 device_printf(sc->sc_dev, "out of range INO %d requested\n",
662 ino);
663 return (0);
664 }
665
666 if ((ino & INTMAP_OBIO_MASK) == 0) {
667 intrmap = SBR_SLOT0_INT_MAP + INTSLOT(ino) * 8;
668 intrclr = SBR_SLOT0_INT_CLR +
669 (INTSLOT(ino) * 8 * 8) + (INTPRI(ino) * 8);
670 } else {
671 intrclr = 0;
672 for (i = 0, intrmap = SBR_SCSI_INT_MAP;
673 intrmap <= SBR_RESERVED_INT_MAP; intrmap += 8, i++) {
674 if (INTVEC(SYSIO_READ8(sc, intrmap)) ==
675 INTMAP_VEC(sc->sc_ign, ino)) {
676 intrclr = SBR_SCSI_INT_CLR + i * 8;
677 break;
678 }
679 }
680 if (intrclr == 0)
681 return (0);
682 }
683 if (intrmapptr != NULL)
684 *intrmapptr = intrmap;
685 if (intrclrptr != NULL)
686 *intrclrptr = intrclr;
687 return (1);
688}
689
690static int
691sbus_setup_intr(device_t dev, device_t child, struct resource *ires, int flags,
692 driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep)
693{
694 struct sbus_softc *sc;
695 u_long vec;
696
697 sc = device_get_softc(dev);
698 /*
699 * Make sure the vector is fully specified and we registered
700 * our interrupt controller for it.
701 */
702 vec = rman_get_start(ires);
703 if (INTIGN(vec) != sc->sc_ign || intr_vectors[vec].iv_ic != &sbus_ic) {
704 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
705 return (EINVAL);
706 }
707 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
708 arg, cookiep));
709}
710
711static struct resource *
712sbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
713 u_long start, u_long end, u_long count, u_int flags)
714{
715 struct sbus_softc *sc;
716 struct rman *rm;
717 struct resource *rv;
718 struct resource_list *rl;
719 struct resource_list_entry *rle;
720 device_t schild;
721 bus_addr_t toffs;
722 bus_size_t tend;
723 int i, slot;
724 int isdefault, passthrough;
725
726 isdefault = (start == 0UL && end == ~0UL);
727 passthrough = (device_get_parent(child) != bus);
728 rle = NULL;
729 sc = device_get_softc(bus);
730 rl = BUS_GET_RESOURCE_LIST(bus, child);
731 switch (type) {
732 case SYS_RES_IRQ:
733 return (resource_list_alloc(rl, bus, child, type, rid, start,
734 end, count, flags));
735 case SYS_RES_MEMORY:
736 if (!passthrough) {
737 rle = resource_list_find(rl, type, *rid);
738 if (rle == NULL)
739 return (NULL);
740 if (rle->res != NULL)
741 panic("%s: resource entry is busy", __func__);
742 if (isdefault) {
743 start = rle->start;
744 count = ulmax(count, rle->count);
745 end = ulmax(rle->end, start + count - 1);
746 }
747 }
748 rm = NULL;
749 schild = child;
750 while (device_get_parent(schild) != bus)
751 schild = device_get_parent(schild);
752 slot = sbus_get_slot(schild);
753 for (i = 0; i < sc->sc_nrange; i++) {
754 if (sc->sc_rd[i].rd_slot != slot ||
755 start < sc->sc_rd[i].rd_coffset ||
756 start > sc->sc_rd[i].rd_cend)
757 continue;
758 /* Disallow cross-range allocations. */
759 if (end > sc->sc_rd[i].rd_cend)
760 return (NULL);
761 /* We've found the connection to the parent bus */
762 toffs = start - sc->sc_rd[i].rd_coffset;
763 tend = end - sc->sc_rd[i].rd_coffset;
764 rm = &sc->sc_rd[i].rd_rman;
765 break;
766 }
767 if (rm == NULL)
768 return (NULL);
769
770 rv = rman_reserve_resource(rm, toffs, tend, count, flags &
771 ~RF_ACTIVE, child);
772 if (rv == NULL)
773 return (NULL);
774 rman_set_rid(rv, *rid);
775
776 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child,
777 type, *rid, rv)) {
778 rman_release_resource(rv);
779 return (NULL);
780 }
781 if (!passthrough)
782 rle->res = rv;
783 return (rv);
784 default:
785 return (NULL);
786 }
787}
788
789static int
790sbus_activate_resource(device_t bus, device_t child, int type, int rid,
791 struct resource *r)
792{
793 struct sbus_softc *sc;
794 struct bus_space_tag *tag;
795 int i;
796
797 switch (type) {
798 case SYS_RES_IRQ:
799 return (bus_generic_activate_resource(bus, child, type, rid,
800 r));
801 case SYS_RES_MEMORY:
802 sc = device_get_softc(bus);
803 for (i = 0; i < sc->sc_nrange; i++) {
804 if (rman_is_region_manager(r,
805 &sc->sc_rd[i].rd_rman) != 0) {
806 tag = sparc64_alloc_bus_tag(r,
807 rman_get_bustag(sc->sc_sysio_res),
808 SBUS_BUS_SPACE, NULL);
809 if (tag == NULL)
810 return (ENOMEM);
811 rman_set_bustag(r, tag);
812 rman_set_bushandle(r,
813 sc->sc_rd[i].rd_bushandle +
814 rman_get_start(r));
815 return (rman_activate_resource(r));
816 }
817 }
818 /* FALLTHROUGH */
819 default:
820 return (EINVAL);
821 }
822}
823
824static int
825sbus_adjust_resource(device_t bus, device_t child, int type,
826 struct resource *r, u_long start, u_long end)
827{
828 struct sbus_softc *sc;
829 int i;
830
831 if (type == SYS_RES_MEMORY) {
832 sc = device_get_softc(bus);
833 for (i = 0; i < sc->sc_nrange; i++)
834 if (rman_is_region_manager(r,
835 &sc->sc_rd[i].rd_rman) != 0)
836 return (rman_adjust_resource(r, start, end));
837 return (EINVAL);
838 }
839 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
840}
841
842static int
843sbus_release_resource(device_t bus, device_t child, int type, int rid,
844 struct resource *r)
845{
846 struct resource_list *rl;
847 struct resource_list_entry *rle;
848 int error, passthrough;
849
850 passthrough = (device_get_parent(child) != bus);
851 rl = BUS_GET_RESOURCE_LIST(bus, child);
852 if (type == SYS_RES_MEMORY) {
853 if ((rman_get_flags(r) & RF_ACTIVE) != 0) {
854 error = bus_deactivate_resource(child, type, rid, r);
855 if (error)
856 return (error);
857 }
858 error = rman_release_resource(r);
859 if (error != 0)
860 return (error);
861 if (!passthrough) {
862 rle = resource_list_find(rl, type, rid);
863 KASSERT(rle != NULL,
864 ("%s: resource entry not found!", __func__));
865 KASSERT(rle->res != NULL,
866 ("%s: resource entry is not busy", __func__));
867 rle->res = NULL;
868 }
869 return (0);
870 }
871 return (resource_list_release(rl, bus, child, type, rid, r));
872}
873
874static bus_dma_tag_t
875sbus_get_dma_tag(device_t bus, device_t child)
876{
877 struct sbus_softc *sc;
878
879 sc = device_get_softc(bus);
880 return (sc->sc_cdmatag);
881}
882
883static const struct ofw_bus_devinfo *
884sbus_get_devinfo(device_t bus, device_t child)
885{
886 struct sbus_devinfo *sdi;
887
888 sdi = device_get_ivars(child);
889 return (&sdi->sdi_obdinfo);
890}
891
892/*
893 * Handle an overtemp situation.
894 *
895 * SPARCs have temperature sensors which generate interrupts
896 * if the machine's temperature exceeds a certain threshold.
897 * This handles the interrupt and powers off the machine.
898 * The same needs to be done to PCI controller drivers.
899 */
900static void
901sbus_overtemp(void *arg)
902{
903 static int shutdown;
904
905 /* As the interrupt is cleared we may be called multiple times. */
906 if (shutdown != 0)
907 return;
908 shutdown++;
909 printf("DANGER: OVER TEMPERATURE detected\nShutting down NOW.\n");
910 shutdown_nice(RB_POWEROFF);
911}
912
913/* Try to shut down in time in case of power failure. */
914static void
915sbus_pwrfail(void *arg)
916{
917 static int shutdown;
918
919 /* As the interrupt is cleared we may be called multiple times. */
920 if (shutdown != 0)
921 return;
922 shutdown++;
923 printf("Power failure detected\nShutting down NOW.\n");
924 shutdown_nice(0);
925}
926
927static int
928sbus_print_res(struct sbus_devinfo *sdi)
929{
930 int rv;
931
932 rv = 0;
933 rv += resource_list_print_type(&sdi->sdi_rl, "mem", SYS_RES_MEMORY,
934 "%#lx");
935 rv += resource_list_print_type(&sdi->sdi_rl, "irq", SYS_RES_IRQ,
936 "%ld");
937 return (rv);
938}
| 192};
193
194static driver_t sbus_driver = {
195 "sbus",
196 sbus_methods,
197 sizeof(struct sbus_softc),
198};
199
200static devclass_t sbus_devclass;
201
202EARLY_DRIVER_MODULE(sbus, nexus, sbus_driver, sbus_devclass, 0, 0,
203 BUS_PASS_BUS);
204MODULE_DEPEND(sbus, nexus, 1, 1, 1);
205MODULE_VERSION(sbus, 1);
206
207#define OFW_SBUS_TYPE "sbus"
208#define OFW_SBUS_NAME "sbus"
209
210static const struct intr_controller sbus_ic = {
211 sbus_intr_enable,
212 sbus_intr_disable,
213 sbus_intr_assign,
214 sbus_intr_clear
215};
216
217struct sbus_icarg {
218 struct sbus_softc *sica_sc;
219 bus_addr_t sica_map;
220 bus_addr_t sica_clr;
221};
222
223static const char *const sbus_order_first[] = {
224 "auxio",
225 "dma",
226 NULL
227};
228
229static int
230sbus_inlist(const char *name, const char *const *list)
231{
232 int i;
233
234 if (name == NULL)
235 return (0);
236 for (i = 0; list[i] != NULL; i++) {
237 if (strcmp(name, list[i]) == 0)
238 return (1);
239 }
240 return (0);
241}
242
243static int
244sbus_probe(device_t dev)
245{
246 const char *t;
247
248 t = ofw_bus_get_type(dev);
249 if (((t == NULL || strcmp(t, OFW_SBUS_TYPE) != 0)) &&
250 strcmp(ofw_bus_get_name(dev), OFW_SBUS_NAME) != 0)
251 return (ENXIO);
252 device_set_desc(dev, "U2S UPA-SBus bridge");
253 return (0);
254}
255
256static int
257sbus_attach(device_t dev)
258{
259 struct sbus_softc *sc;
260 struct sbus_devinfo *sdi;
261 struct sbus_icarg *sica;
262 struct sbus_ranges *range;
263 struct resource *res;
264 struct resource_list *rl;
265 device_t cdev;
266 bus_addr_t intrclr, intrmap, phys;
267 bus_size_t size;
268 u_long vec;
269 phandle_t child, node;
270 uint32_t prop;
271 int i, j;
272
273 sc = device_get_softc(dev);
274 sc->sc_dev = dev;
275 node = ofw_bus_get_node(dev);
276
277 i = 0;
278 sc->sc_sysio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
279 RF_ACTIVE);
280 if (sc->sc_sysio_res == NULL)
281 panic("%s: cannot allocate device memory", __func__);
282
283 if (OF_getprop(node, "interrupts", &prop, sizeof(prop)) == -1)
284 panic("%s: cannot get IGN", __func__);
285 sc->sc_ign = INTIGN(prop);
286
287 /*
288 * Record clock frequency for synchronous SCSI.
289 * IS THIS THE CORRECT DEFAULT??
290 */
291 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
292 prop = 25000000;
293 sc->sc_clockfreq = prop;
294 prop /= 1000;
295 device_printf(dev, "clock %d.%03d MHz\n", prop / 1000, prop % 1000);
296
297 /*
298 * Collect address translations from the OBP.
299 */
300 if ((sc->sc_nrange = OF_getprop_alloc(node, "ranges",
301 sizeof(*range), (void **)&range)) == -1) {
302 panic("%s: error getting ranges property", __func__);
303 }
304 sc->sc_rd = malloc(sizeof(*sc->sc_rd) * sc->sc_nrange, M_DEVBUF,
305 M_NOWAIT | M_ZERO);
306 if (sc->sc_rd == NULL)
307 panic("%s: cannot allocate rmans", __func__);
308 /*
309 * Preallocate all space that the SBus bridge decodes, so that nothing
310 * else gets in the way; set up rmans etc.
311 */
312 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
313 for (i = 0; i < sc->sc_nrange; i++) {
314 phys = range[i].poffset | ((bus_addr_t)range[i].pspace << 32);
315 size = range[i].size;
316 sc->sc_rd[i].rd_slot = range[i].cspace;
317 sc->sc_rd[i].rd_coffset = range[i].coffset;
318 sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size;
319 j = resource_list_add_next(rl, SYS_RES_MEMORY, phys,
320 phys + size - 1, size);
321 if ((res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &j,
322 RF_ACTIVE)) == NULL)
323 panic("%s: cannot allocate decoded range", __func__);
324 sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res);
325 sc->sc_rd[i].rd_rman.rm_type = RMAN_ARRAY;
326 sc->sc_rd[i].rd_rman.rm_descr = "SBus Device Memory";
327 if (rman_init(&sc->sc_rd[i].rd_rman) != 0 ||
328 rman_manage_region(&sc->sc_rd[i].rd_rman, 0, size) != 0)
329 panic("%s: failed to set up memory rman", __func__);
330 sc->sc_rd[i].rd_poffset = phys;
331 sc->sc_rd[i].rd_pend = phys + size;
332 sc->sc_rd[i].rd_res = res;
333 }
334 free(range, M_OFWPROP);
335
336 /*
337 * Get the SBus burst transfer size if burst transfers are supported.
338 */
339 if (OF_getprop(node, "up-burst-sizes", &sc->sc_burst,
340 sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0)
341 sc->sc_burst =
342 (SBUS_BURST64_DEF << SBUS_BURST64_SHIFT) | SBUS_BURST_DEF;
343
344 /* initalise the IOMMU */
345
346 /* punch in our copies */
347 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(SBUS_IOMMU_BITS);
348 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_sysio_res);
349 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_sysio_res);
350 sc->sc_is.is_iommu = SBR_IOMMU;
351 sc->sc_is.is_dtag = SBR_IOMMU_TLB_TAG_DIAG;
352 sc->sc_is.is_ddram = SBR_IOMMU_TLB_DATA_DIAG;
353 sc->sc_is.is_dqueue = SBR_IOMMU_QUEUE_DIAG;
354 sc->sc_is.is_dva = SBR_IOMMU_SVADIAG;
355 sc->sc_is.is_dtcmp = 0;
356 sc->sc_is.is_sb[0] = SBR_STRBUF;
357 sc->sc_is.is_sb[1] = 0;
358
359 /*
360 * Note: the SBus IOMMU ignores the high bits of an address, so a NULL
361 * DMA pointer will be translated by the first page of the IOTSB.
362 * To detect bugs we'll allocate and ignore the first entry.
363 */
364 iommu_init(device_get_nameunit(dev), &sc->sc_is, 3, -1, 1);
365
366 /* Create the DMA tag. */
367 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
368 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr,
369 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_cdmatag) != 0)
370 panic("%s: bus_dma_tag_create failed", __func__);
371 /* Customize the tag. */
372 sc->sc_cdmatag->dt_cookie = &sc->sc_is;
373 sc->sc_cdmatag->dt_mt = &iommu_dma_methods;
374
375 /*
376 * Hunt through all the interrupt mapping regs and register our
377 * interrupt controller for the corresponding interrupt vectors.
378 * We do this early in order to be able to catch stray interrupts.
379 */
380 for (i = 0; i <= SBUS_MAX_INO; i++) {
381 if (sbus_find_intrmap(sc, i, &intrmap, &intrclr) == 0)
382 continue;
383 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
384 if (sica == NULL)
385 panic("%s: could not allocate interrupt controller "
386 "argument", __func__);
387 sica->sica_sc = sc;
388 sica->sica_map = intrmap;
389 sica->sica_clr = intrclr;
390#ifdef SBUS_DEBUG
391 device_printf(dev,
392 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
393 i, (i & INTMAP_OBIO_MASK) == 0 ? "SBus slot" : "OBIO",
394 (u_long)intrmap, (u_long)SYSIO_READ8(sc, intrmap),
395 (u_long)intrclr);
396#endif
397 j = intr_controller_register(INTMAP_VEC(sc->sc_ign, i),
398 &sbus_ic, sica);
399 if (j != 0)
400 device_printf(dev, "could not register interrupt "
401 "controller for INO %d (%d)\n", i, j);
402 }
403
404 /* Enable the over-temperature and power-fail interrupts. */
405 i = 4;
406 sc->sc_ot_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
407 RF_ACTIVE);
408 if (sc->sc_ot_ires == NULL ||
409 INTIGN(vec = rman_get_start(sc->sc_ot_ires)) != sc->sc_ign ||
410 INTVEC(SYSIO_READ8(sc, SBR_THERM_INT_MAP)) != vec ||
411 intr_vectors[vec].iv_ic != &sbus_ic ||
412 bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_BRIDGE,
413 NULL, sbus_overtemp, sc, &sc->sc_ot_ihand) != 0)
414 panic("%s: failed to set up temperature interrupt", __func__);
415 i = 3;
416 sc->sc_pf_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
417 RF_ACTIVE);
418 if (sc->sc_pf_ires == NULL ||
419 INTIGN(vec = rman_get_start(sc->sc_pf_ires)) != sc->sc_ign ||
420 INTVEC(SYSIO_READ8(sc, SBR_POWER_INT_MAP)) != vec ||
421 intr_vectors[vec].iv_ic != &sbus_ic ||
422 bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_BRIDGE,
423 NULL, sbus_pwrfail, sc, &sc->sc_pf_ihand) != 0)
424 panic("%s: failed to set up power fail interrupt", __func__);
425
426 /* Initialize the counter-timer. */
427 sparc64_counter_init(device_get_nameunit(dev),
428 rman_get_bustag(sc->sc_sysio_res),
429 rman_get_bushandle(sc->sc_sysio_res), SBR_TC0);
430
431 /*
432 * Loop through ROM children, fixing any relative addresses
433 * and then configuring each device.
434 */
435 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
436 if ((sdi = sbus_setup_dinfo(dev, sc, child)) == NULL)
437 continue;
438 /*
439 * For devices where there are variants that are actually
440 * split into two SBus devices (as opposed to the first
441 * half of the device being a SBus device and the second
442 * half hanging off of the first one) like 'auxio' and
443 * 'SUNW,fdtwo' or 'dma' and 'esp' probe the SBus device
444 * which is a prerequisite to the driver attaching to the
445 * second one with a lower order. Saves us from dealing
446 * with different probe orders in the respective device
447 * drivers which generally is more hackish.
448 */
449 cdev = device_add_child_ordered(dev, (OF_child(child) == 0 &&
450 sbus_inlist(sdi->sdi_obdinfo.obd_name, sbus_order_first)) ?
451 SBUS_ORDER_FIRST : SBUS_ORDER_NORMAL, NULL, -1);
452 if (cdev == NULL) {
453 device_printf(dev,
454 "<%s>: device_add_child_ordered failed\n",
455 sdi->sdi_obdinfo.obd_name);
456 sbus_destroy_dinfo(sdi);
457 continue;
458 }
459 device_set_ivars(cdev, sdi);
460 }
461 return (bus_generic_attach(dev));
462}
463
464static struct sbus_devinfo *
465sbus_setup_dinfo(device_t dev, struct sbus_softc *sc, phandle_t node)
466{
467 struct sbus_devinfo *sdi;
468 struct sbus_regs *reg;
469 u_int32_t base, iv, *intr;
470 int i, nreg, nintr, slot, rslot;
471
472 sdi = malloc(sizeof(*sdi), M_DEVBUF, M_ZERO | M_WAITOK);
473 if (ofw_bus_gen_setup_devinfo(&sdi->sdi_obdinfo, node) != 0) {
474 free(sdi, M_DEVBUF);
475 return (NULL);
476 }
477 resource_list_init(&sdi->sdi_rl);
478 slot = -1;
479 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®);
480 if (nreg == -1) {
481 if (sdi->sdi_obdinfo.obd_type == NULL ||
482 strcmp(sdi->sdi_obdinfo.obd_type, "hierarchical") != 0) {
483 device_printf(dev, "<%s>: incomplete\n",
484 sdi->sdi_obdinfo.obd_name);
485 goto fail;
486 }
487 } else {
488 for (i = 0; i < nreg; i++) {
489 base = reg[i].sbr_offset;
490 if (SBUS_ABS(base)) {
491 rslot = SBUS_ABS_TO_SLOT(base);
492 base = SBUS_ABS_TO_OFFSET(base);
493 } else
494 rslot = reg[i].sbr_slot;
495 if (slot != -1 && slot != rslot) {
496 device_printf(dev, "<%s>: multiple slots\n",
497 sdi->sdi_obdinfo.obd_name);
498 free(reg, M_OFWPROP);
499 goto fail;
500 }
501 slot = rslot;
502
503 resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i,
504 base, base + reg[i].sbr_size, reg[i].sbr_size);
505 }
506 free(reg, M_OFWPROP);
507 }
508 sdi->sdi_slot = slot;
509
510 /*
511 * The `interrupts' property contains the SBus interrupt level.
512 */
513 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr),
514 (void **)&intr);
515 if (nintr != -1) {
516 for (i = 0; i < nintr; i++) {
517 iv = intr[i];
518 /*
519 * SBus card devices need the slot number encoded into
520 * the vector as this is generally not done.
521 */
522 if ((iv & INTMAP_OBIO_MASK) == 0)
523 iv |= slot << 3;
524 iv = INTMAP_VEC(sc->sc_ign, iv);
525 resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i,
526 iv, iv, 1);
527 }
528 free(intr, M_OFWPROP);
529 }
530 if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz,
531 sizeof(sdi->sdi_burstsz)) == -1)
532 sdi->sdi_burstsz = sc->sc_burst;
533 else
534 sdi->sdi_burstsz &= sc->sc_burst;
535 if (OF_getprop(node, "clock-frequency", &sdi->sdi_clockfreq,
536 sizeof(sdi->sdi_clockfreq)) == -1)
537 sdi->sdi_clockfreq = sc->sc_clockfreq;
538
539 return (sdi);
540
541fail:
542 sbus_destroy_dinfo(sdi);
543 return (NULL);
544}
545
546static void
547sbus_destroy_dinfo(struct sbus_devinfo *dinfo)
548{
549
550 resource_list_free(&dinfo->sdi_rl);
551 ofw_bus_gen_destroy_devinfo(&dinfo->sdi_obdinfo);
552 free(dinfo, M_DEVBUF);
553}
554
555static int
556sbus_print_child(device_t dev, device_t child)
557{
558 int rv;
559
560 rv = bus_print_child_header(dev, child);
561 rv += sbus_print_res(device_get_ivars(child));
562 rv += bus_print_child_footer(dev, child);
563 return (rv);
564}
565
566static void
567sbus_probe_nomatch(device_t dev, device_t child)
568{
569 const char *type;
570
571 device_printf(dev, "<%s>", ofw_bus_get_name(child));
572 sbus_print_res(device_get_ivars(child));
573 type = ofw_bus_get_type(child);
574 printf(" type %s (no driver attached)\n",
575 type != NULL ? type : "unknown");
576}
577
578static int
579sbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
580{
581 struct sbus_softc *sc;
582 struct sbus_devinfo *dinfo;
583
584 sc = device_get_softc(dev);
585 if ((dinfo = device_get_ivars(child)) == NULL)
586 return (ENOENT);
587 switch (which) {
588 case SBUS_IVAR_BURSTSZ:
589 *result = dinfo->sdi_burstsz;
590 break;
591 case SBUS_IVAR_CLOCKFREQ:
592 *result = dinfo->sdi_clockfreq;
593 break;
594 case SBUS_IVAR_IGN:
595 *result = sc->sc_ign;
596 break;
597 case SBUS_IVAR_SLOT:
598 *result = dinfo->sdi_slot;
599 break;
600 default:
601 return (ENOENT);
602 }
603 return (0);
604}
605
606static struct resource_list *
607sbus_get_resource_list(device_t dev, device_t child)
608{
609 struct sbus_devinfo *sdi;
610
611 sdi = device_get_ivars(child);
612 return (&sdi->sdi_rl);
613}
614
615static void
616sbus_intr_enable(void *arg)
617{
618 struct intr_vector *iv = arg;
619 struct sbus_icarg *sica = iv->iv_icarg;
620
621 SYSIO_WRITE8(sica->sica_sc, sica->sica_map,
622 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
623}
624
625static void
626sbus_intr_disable(void *arg)
627{
628 struct intr_vector *iv = arg;
629 struct sbus_icarg *sica = iv->iv_icarg;
630
631 SYSIO_WRITE8(sica->sica_sc, sica->sica_map, iv->iv_vec);
632}
633
634static void
635sbus_intr_assign(void *arg)
636{
637 struct intr_vector *iv = arg;
638 struct sbus_icarg *sica = iv->iv_icarg;
639
640 SYSIO_WRITE8(sica->sica_sc, sica->sica_map, INTMAP_TID(
641 SYSIO_READ8(sica->sica_sc, sica->sica_map), iv->iv_mid));
642}
643
644static void
645sbus_intr_clear(void *arg)
646{
647 struct intr_vector *iv = arg;
648 struct sbus_icarg *sica = iv->iv_icarg;
649
650 SYSIO_WRITE8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE);
651}
652
653static int
654sbus_find_intrmap(struct sbus_softc *sc, u_int ino, bus_addr_t *intrmapptr,
655 bus_addr_t *intrclrptr)
656{
657 bus_addr_t intrclr, intrmap;
658 int i;
659
660 if (ino > SBUS_MAX_INO) {
661 device_printf(sc->sc_dev, "out of range INO %d requested\n",
662 ino);
663 return (0);
664 }
665
666 if ((ino & INTMAP_OBIO_MASK) == 0) {
667 intrmap = SBR_SLOT0_INT_MAP + INTSLOT(ino) * 8;
668 intrclr = SBR_SLOT0_INT_CLR +
669 (INTSLOT(ino) * 8 * 8) + (INTPRI(ino) * 8);
670 } else {
671 intrclr = 0;
672 for (i = 0, intrmap = SBR_SCSI_INT_MAP;
673 intrmap <= SBR_RESERVED_INT_MAP; intrmap += 8, i++) {
674 if (INTVEC(SYSIO_READ8(sc, intrmap)) ==
675 INTMAP_VEC(sc->sc_ign, ino)) {
676 intrclr = SBR_SCSI_INT_CLR + i * 8;
677 break;
678 }
679 }
680 if (intrclr == 0)
681 return (0);
682 }
683 if (intrmapptr != NULL)
684 *intrmapptr = intrmap;
685 if (intrclrptr != NULL)
686 *intrclrptr = intrclr;
687 return (1);
688}
689
690static int
691sbus_setup_intr(device_t dev, device_t child, struct resource *ires, int flags,
692 driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep)
693{
694 struct sbus_softc *sc;
695 u_long vec;
696
697 sc = device_get_softc(dev);
698 /*
699 * Make sure the vector is fully specified and we registered
700 * our interrupt controller for it.
701 */
702 vec = rman_get_start(ires);
703 if (INTIGN(vec) != sc->sc_ign || intr_vectors[vec].iv_ic != &sbus_ic) {
704 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
705 return (EINVAL);
706 }
707 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
708 arg, cookiep));
709}
710
711static struct resource *
712sbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
713 u_long start, u_long end, u_long count, u_int flags)
714{
715 struct sbus_softc *sc;
716 struct rman *rm;
717 struct resource *rv;
718 struct resource_list *rl;
719 struct resource_list_entry *rle;
720 device_t schild;
721 bus_addr_t toffs;
722 bus_size_t tend;
723 int i, slot;
724 int isdefault, passthrough;
725
726 isdefault = (start == 0UL && end == ~0UL);
727 passthrough = (device_get_parent(child) != bus);
728 rle = NULL;
729 sc = device_get_softc(bus);
730 rl = BUS_GET_RESOURCE_LIST(bus, child);
731 switch (type) {
732 case SYS_RES_IRQ:
733 return (resource_list_alloc(rl, bus, child, type, rid, start,
734 end, count, flags));
735 case SYS_RES_MEMORY:
736 if (!passthrough) {
737 rle = resource_list_find(rl, type, *rid);
738 if (rle == NULL)
739 return (NULL);
740 if (rle->res != NULL)
741 panic("%s: resource entry is busy", __func__);
742 if (isdefault) {
743 start = rle->start;
744 count = ulmax(count, rle->count);
745 end = ulmax(rle->end, start + count - 1);
746 }
747 }
748 rm = NULL;
749 schild = child;
750 while (device_get_parent(schild) != bus)
751 schild = device_get_parent(schild);
752 slot = sbus_get_slot(schild);
753 for (i = 0; i < sc->sc_nrange; i++) {
754 if (sc->sc_rd[i].rd_slot != slot ||
755 start < sc->sc_rd[i].rd_coffset ||
756 start > sc->sc_rd[i].rd_cend)
757 continue;
758 /* Disallow cross-range allocations. */
759 if (end > sc->sc_rd[i].rd_cend)
760 return (NULL);
761 /* We've found the connection to the parent bus */
762 toffs = start - sc->sc_rd[i].rd_coffset;
763 tend = end - sc->sc_rd[i].rd_coffset;
764 rm = &sc->sc_rd[i].rd_rman;
765 break;
766 }
767 if (rm == NULL)
768 return (NULL);
769
770 rv = rman_reserve_resource(rm, toffs, tend, count, flags &
771 ~RF_ACTIVE, child);
772 if (rv == NULL)
773 return (NULL);
774 rman_set_rid(rv, *rid);
775
776 if ((flags & RF_ACTIVE) != 0 && bus_activate_resource(child,
777 type, *rid, rv)) {
778 rman_release_resource(rv);
779 return (NULL);
780 }
781 if (!passthrough)
782 rle->res = rv;
783 return (rv);
784 default:
785 return (NULL);
786 }
787}
788
789static int
790sbus_activate_resource(device_t bus, device_t child, int type, int rid,
791 struct resource *r)
792{
793 struct sbus_softc *sc;
794 struct bus_space_tag *tag;
795 int i;
796
797 switch (type) {
798 case SYS_RES_IRQ:
799 return (bus_generic_activate_resource(bus, child, type, rid,
800 r));
801 case SYS_RES_MEMORY:
802 sc = device_get_softc(bus);
803 for (i = 0; i < sc->sc_nrange; i++) {
804 if (rman_is_region_manager(r,
805 &sc->sc_rd[i].rd_rman) != 0) {
806 tag = sparc64_alloc_bus_tag(r,
807 rman_get_bustag(sc->sc_sysio_res),
808 SBUS_BUS_SPACE, NULL);
809 if (tag == NULL)
810 return (ENOMEM);
811 rman_set_bustag(r, tag);
812 rman_set_bushandle(r,
813 sc->sc_rd[i].rd_bushandle +
814 rman_get_start(r));
815 return (rman_activate_resource(r));
816 }
817 }
818 /* FALLTHROUGH */
819 default:
820 return (EINVAL);
821 }
822}
823
824static int
825sbus_adjust_resource(device_t bus, device_t child, int type,
826 struct resource *r, u_long start, u_long end)
827{
828 struct sbus_softc *sc;
829 int i;
830
831 if (type == SYS_RES_MEMORY) {
832 sc = device_get_softc(bus);
833 for (i = 0; i < sc->sc_nrange; i++)
834 if (rman_is_region_manager(r,
835 &sc->sc_rd[i].rd_rman) != 0)
836 return (rman_adjust_resource(r, start, end));
837 return (EINVAL);
838 }
839 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
840}
841
842static int
843sbus_release_resource(device_t bus, device_t child, int type, int rid,
844 struct resource *r)
845{
846 struct resource_list *rl;
847 struct resource_list_entry *rle;
848 int error, passthrough;
849
850 passthrough = (device_get_parent(child) != bus);
851 rl = BUS_GET_RESOURCE_LIST(bus, child);
852 if (type == SYS_RES_MEMORY) {
853 if ((rman_get_flags(r) & RF_ACTIVE) != 0) {
854 error = bus_deactivate_resource(child, type, rid, r);
855 if (error)
856 return (error);
857 }
858 error = rman_release_resource(r);
859 if (error != 0)
860 return (error);
861 if (!passthrough) {
862 rle = resource_list_find(rl, type, rid);
863 KASSERT(rle != NULL,
864 ("%s: resource entry not found!", __func__));
865 KASSERT(rle->res != NULL,
866 ("%s: resource entry is not busy", __func__));
867 rle->res = NULL;
868 }
869 return (0);
870 }
871 return (resource_list_release(rl, bus, child, type, rid, r));
872}
873
874static bus_dma_tag_t
875sbus_get_dma_tag(device_t bus, device_t child)
876{
877 struct sbus_softc *sc;
878
879 sc = device_get_softc(bus);
880 return (sc->sc_cdmatag);
881}
882
883static const struct ofw_bus_devinfo *
884sbus_get_devinfo(device_t bus, device_t child)
885{
886 struct sbus_devinfo *sdi;
887
888 sdi = device_get_ivars(child);
889 return (&sdi->sdi_obdinfo);
890}
891
892/*
893 * Handle an overtemp situation.
894 *
895 * SPARCs have temperature sensors which generate interrupts
896 * if the machine's temperature exceeds a certain threshold.
897 * This handles the interrupt and powers off the machine.
898 * The same needs to be done to PCI controller drivers.
899 */
900static void
901sbus_overtemp(void *arg)
902{
903 static int shutdown;
904
905 /* As the interrupt is cleared we may be called multiple times. */
906 if (shutdown != 0)
907 return;
908 shutdown++;
909 printf("DANGER: OVER TEMPERATURE detected\nShutting down NOW.\n");
910 shutdown_nice(RB_POWEROFF);
911}
912
913/* Try to shut down in time in case of power failure. */
914static void
915sbus_pwrfail(void *arg)
916{
917 static int shutdown;
918
919 /* As the interrupt is cleared we may be called multiple times. */
920 if (shutdown != 0)
921 return;
922 shutdown++;
923 printf("Power failure detected\nShutting down NOW.\n");
924 shutdown_nice(0);
925}
926
927static int
928sbus_print_res(struct sbus_devinfo *sdi)
929{
930 int rv;
931
932 rv = 0;
933 rv += resource_list_print_type(&sdi->sdi_rl, "mem", SYS_RES_MEMORY,
934 "%#lx");
935 rv += resource_list_print_type(&sdi->sdi_rl, "irq", SYS_RES_IRQ,
936 "%ld");
937 return (rv);
938}
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