60c60
< __FBSDID("$FreeBSD: head/sys/sparc64/sbus/lsi64854.c 226381 2011-10-15 09:29:43Z marius $");
---
> __FBSDID("$FreeBSD: head/sys/sparc64/sbus/lsi64854.c 226947 2011-10-30 21:17:42Z marius $");
97c97,102
< #define MAX_DMA_SZ (16*1024*1024)
---
> /*
> * The rules say we cannot transfer more than the limit of this DMA chip (64k
> * for old and 16Mb for new), and we cannot cross a 16Mb boundary.
> */
> #define MAX_DMA_SZ (64 * 1024)
> #define BOUNDARY (16 * 1024 * 1024)
127a133
> sc->sc_maxdmasize = MAX_DMA_SZ;
137a144
> sc->sc_maxdmasize = nsc->sc_maxxfer;
156c163
< 1, 0, /* alignment, boundary */
---
> 1, BOUNDARY, /* alignment, boundary */
160c167
< MAX_DMA_SZ, /* maxsize */
---
> sc->sc_maxdmasize, /* maxsize */
162c169
< MAX_DMA_SZ, /* maxsegsize */
---
> sc->sc_maxdmasize, /* maxsegsize */
253,262c260,269
< if (sc->sc_rev != DMAREV_HME) { \
< /* \
< * Select drain bit based on revision \
< * also clears errors and D_TC flag \
< */ \
< csr = L64854_GCSR(sc); \
< if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
< csr |= D_ESC_DRAIN; \
< else \
< csr |= L64854_INVALIDATE; \
---
> if (sc->sc_rev != DMAREV_HME) { \
> /* \
> * Select drain bit based on revision \
> * also clears errors and D_TC flag \
> */ \
> csr = L64854_GCSR(sc); \
> if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
> csr |= D_ESC_DRAIN; \
> else \
> csr |= L64854_INVALIDATE; \
264c271
< L64854_SCSR(sc,csr); \
---
> L64854_SCSR(sc, csr); \
270c277,278
< DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
---
> DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", \
> dontpanic); \
285c293
< L64854_SCSR(sc,csr); \
---
> L64854_SCSR(sc, csr); \
290a299,300
> bus_dma_tag_t dmat;
> bus_dmamap_t dmam;
299,302c309,313
< bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
< (csr & D_WRITE) != 0 ? BUS_DMASYNC_PREREAD :
< BUS_DMASYNC_PREWRITE);
< bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
---
> dmat = sc->sc_buffer_dmat;
> dmam = sc->sc_dmamap;
> bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
> BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
> bus_dmamap_unload(dmat, dmam);
366a378,379
> if (error != 0)
> return;
371c384
< sc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
---
> sc->sc_datain != 0 ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
375d387
< #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ - 1)))
383a396
> int error;
395,401c408,409
< /*
< * The rules say we cannot transfer more than the limit
< * of this DMA chip (64k for old and 16Mb for new),
< * and we cannot cross a 16Mb boundary.
< */
< *dmasize = sc->sc_dmasize =
< ulmin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr));
---
> KASSERT(*dmasize <= sc->sc_maxdmasize,
> ("%s: transfer size %ld too large", __func__, (long)*dmasize));
403c411
< DPRINTF(LDB_ANY, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize));
---
> sc->sc_dmasize = *dmasize;
404a413,414
> DPRINTF(LDB_ANY, ("%s: dmasize=%ld\n", __func__, (long)*dmasize));
>
415,419c425,436
< /* Program the DMA address */
< if (sc->sc_dmasize != 0)
< if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
< *sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_scsi, sc, 0))
< panic("%s: cannot allocate DVMA address", __func__);
---
> /*
> * Load the transfer buffer and program the DMA address.
> * Note that the NCR53C9x core can't handle EINPROGRESS so we set
> * BUS_DMA_NOWAIT.
> */
> if (*dmasize != 0) {
> error = bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
> *sc->sc_dmaaddr, *dmasize, lsi64854_map_scsi, sc,
> BUS_DMA_NOWAIT);
> if (error != 0)
> return (error);
> }
423c440
< bcnt = sc->sc_dmasize;
---
> bcnt = *dmasize;
429c446
< /* Setup DMA control register */
---
> /* Setup the DMA control register. */
432c449
< if (datain)
---
> if (datain != 0)
458c475,478
< int trans, resid;
---
> bus_dma_tag_t dmat;
> bus_dmamap_t dmam;
> size_t dmasize;
> int lxfer, resid, trans;
464c484
< bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS));
---
> bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS));
466,468c486,489
< if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
< device_printf(sc->sc_dev, "error: csr=%b\n", csr, DDMACSR_BITS);
< csr &= ~D_EN_DMA; /* Stop DMA */
---
> if (csr & (D_ERR_PEND | D_SLAVE_ERR)) {
> device_printf(sc->sc_dev, "error: csr=%b\n", csr,
> DDMACSR_BITS);
> csr &= ~D_EN_DMA; /* Stop DMA. */
470c491
< csr |= D_INVALIDATE|D_SLAVE_ERR;
---
> csr |= D_INVALIDATE | D_SLAVE_ERR;
486,489c507,511
< if (sc->sc_dmasize == 0) {
< /* A "Transfer Pad" operation completed */
< DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, tcm=%d)\n",
< __func__, NCR_READ_REG(nsc, NCR_TCL) |
---
> dmasize = sc->sc_dmasize;
> if (dmasize == 0) {
> /* A "Transfer Pad" operation completed. */
> DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, "
> "tcm=%d)\n", __func__, NCR_READ_REG(nsc, NCR_TCL) |
502c524
< if (!(csr & D_WRITE) &&
---
> if ((csr & D_WRITE) == 0 &&
511a534
> lxfer = nsc->sc_features & NCR_F_LARGEXFER;
513c536
< * `Terminal count' is off, so read the residue
---
> * "Terminal count" is off, so read the residue
518,519c541
< ((nsc->sc_cfg2 & NCRCFG2_FE) ?
< (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
---
> (lxfer != 0 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
521,523c543,544
< if (resid == 0 && sc->sc_dmasize == 65536 &&
< (nsc->sc_cfg2 & NCRCFG2_FE) == 0)
< /* A transfer of 64K is encoded as `TCL=TCM=0' */
---
> if (resid == 0 && dmasize == 65536 && lxfer == 0)
> /* A transfer of 64k is encoded as TCL=TCM=0. */
527c548
< trans = sc->sc_dmasize - resid;
---
> trans = dmasize - resid;
536c557
< sc->sc_dmasize);
---
> dmasize);
538c559
< trans = sc->sc_dmasize;
---
> trans = dmasize;
543,544c564,565
< (nsc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(nsc, NCR_TCH) : 0,
< trans, resid));
---
> (nsc->sc_sc_features & NCR_F_LARGEXFER) != 0 ?
> NCR_READ_REG(nsc, NCR_TCH) : 0, trans, resid));
546,550c567,572
< if (sc->sc_dmasize != 0) {
< bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
< (csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD :
< BUS_DMASYNC_POSTWRITE);
< bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
---
> if (dmasize != 0) {
> dmat = sc->sc_buffer_dmat;
> dmam = sc->sc_dmamap;
> bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
> BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
> bus_dmamap_unload(dmat, dmam);
568c590
< * Pseudo (chained) interrupt to le driver to handle DMA errors.
---
> * Pseudo (chained) interrupt to le(4) driver to handle DMA errors
582,584c604,607
< if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
< device_printf(sc->sc_dev, "error: csr=%b\n", csr, EDMACSR_BITS);
< csr &= ~L64854_EN_DMA; /* Stop DMA */
---
> if (csr & (E_ERR_PEND | E_SLAVE_ERR)) {
> device_printf(sc->sc_dev, "error: csr=%b\n", csr,
> EDMACSR_BITS);
> csr &= ~L64854_EN_DMA; /* Stop DMA. */
586c609
< csr |= E_INVALIDATE|E_SLAVE_ERR;
---
> csr |= E_INVALIDATE | E_SLAVE_ERR;
612a636,637
> if (error != 0)
> return;
616,617c641,642
< bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ?
< BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
---
> bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
> sc->sc_datain != 0 ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
624c649
< * setup a DMA transfer
---
> * Setup a DMA transfer.
629a655
> int error;
639c665
< (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
---
> (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain != 0 ? 1 : 0));
641,647c667,668
< /*
< * the rules say we cannot transfer more than the limit
< * of this DMA chip (64k for old and 16Mb for new),
< * and we cannot cross a 16Mb boundary.
< */
< *dmasize = sc->sc_dmasize =
< ulmin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr));
---
> KASSERT(*dmasize <= sc->sc_maxdmasize,
> ("%s: transfer size %ld too large", __func__, (long)*dmasize));
649c670
< DPRINTF(LDB_PP, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize));
---
> sc->sc_dmasize = *dmasize;
651,655c672
< /* Program the DMA address */
< if (sc->sc_dmasize != 0)
< if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
< *sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_pp, sc, 0))
< panic("%s: pp cannot allocate DVMA address", __func__);
---
> DPRINTF(LDB_PP, ("%s: dmasize=%ld\n", __func__, (long)*dmasize));
657c674,683
< /* Setup DMA control register */
---
> /* Load the transfer buffer and program the DMA address. */
> if (*dmasize != 0) {
> error = bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
> *sc->sc_dmaaddr, *dmasize, lsi64854_map_pp, sc,
> BUS_DMA_NOWAIT);
> if (error != 0)
> return (error);
> }
>
> /* Setup the DMA control register. */
666c692
< csr |= P_EN_DMA|P_INT_EN|P_EN_CNT;
---
> csr |= P_EN_DMA | P_INT_EN | P_EN_CNT;
668,669c694,695
< /* This bit is read-only in PP csr register */
< if (datain)
---
> /* This bit is read-only in PP csr register. */
> if (datain != 0)
680c706
< * Parallel port DMA interrupt.
---
> * Parallel port DMA interrupt
685a712,714
> bus_dma_tag_t dmat;
> bus_dmamap_t dmam;
> size_t dmasize;
694c723
< if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
---
> if ((csr & (P_ERR_PEND | P_SLAVE_ERR)) != 0) {
698c727
< csr &= ~P_EN_DMA; /* Stop DMA */
---
> csr &= ~P_EN_DMA; /* Stop DMA. */
700c729
< csr |= P_INVALIDATE|P_SLAVE_ERR;
---
> csr |= P_INVALIDATE | P_SLAVE_ERR;
717c746,747
< trans = sc->sc_dmasize - resid;
---
> dmasize = sc->sc_dmasize;
> trans = dmasize - resid;
719c749
< trans = sc->sc_dmasize;
---
> trans = dmasize;
723,727c753,758
< if (sc->sc_dmasize != 0) {
< bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
< (csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD :
< BUS_DMASYNC_POSTWRITE);
< bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap);
---
> if (dmasize != 0) {
> dmat = sc->sc_buffer_dmat;
> dmam = sc->sc_dmamap;
> bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
> BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
> bus_dmamap_unload(dmat, dmam);