| psychoreg.h (86231) | psychoreg.h (90617) |
|---|---|
| 1/* 2 * Copyright (c) 1998, 1999 Eduardo E. Horvath 3 * Copyright (c) 1999 Matthew R. Green 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 14 unchanged lines hidden (view full) --- 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp 30 * | 1/* 2 * Copyright (c) 1998, 1999 Eduardo E. Horvath 3 * Copyright (c) 1999 Matthew R. Green 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 14 unchanged lines hidden (view full) --- 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp 30 * |
| 31 * $FreeBSD: head/sys/sparc64/pci/psychoreg.h 86231 2001-11-09 20:19:58Z tmm $ | 31 * $FreeBSD: head/sys/sparc64/pci/psychoreg.h 90617 2002-02-13 16:07:59Z tmm $ |
| 32 */ 33 34#ifndef _SPARC64_PCI_PSYCHOREG_H_ 35#define _SPARC64_PCI_PSYCHOREG_H_ 36 37/* 38 * Sun4u PCI definitions. Here's where we deal w/the machine 39 * dependencies of psycho and the PCI controller on the UltraIIi. 40 * 41 * All PCI registers are bit-swapped, however they are not byte-swapped. 42 * This means that they must be accessed using little-endian access modes, 43 * either map the pages little-endian or use little-endian ASIs. 44 * 45 * PSYCHO implements two PCI buses, A and B. 46 */ 47 | 32 */ 33 34#ifndef _SPARC64_PCI_PSYCHOREG_H_ 35#define _SPARC64_PCI_PSYCHOREG_H_ 36 37/* 38 * Sun4u PCI definitions. Here's where we deal w/the machine 39 * dependencies of psycho and the PCI controller on the UltraIIi. 40 * 41 * All PCI registers are bit-swapped, however they are not byte-swapped. 42 * This means that they must be accessed using little-endian access modes, 43 * either map the pages little-endian or use little-endian ASIs. 44 * 45 * PSYCHO implements two PCI buses, A and B. 46 */ 47 |
| 48struct psychoreg { 49 struct upareg { 50 /* UPA port ID register */ /* 1fe.0000.0000 */ 51 u_int64_t upa_portid; 52 /* UPA config register */ /* 1fe.0000.0008 */ 53 u_int64_t upa_config; 54 } sys_upa; | 48/* 49 * psycho register offset.s 50 * 51 * NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000 52 * respectively. 53 */ 54#define PSR_UPA_PORTID 0x0000 /* UPA port ID register */ 55#define PSR_UPA_CONFIG 0x0008 /* UPA config register */ 56#define PSR_CS 0x0010 /* PSYCHO control/status register */ 57#define PSR_ECCC 0x0020 /* ECC control register */ 58#define PSR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */ 59#define PSR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */ 60#define PSR_CE_AFS 0x0040 /* Correctable Error AFSR */ 61#define PSR_CE_AFA 0x0048 /* Correctable Error AFAR */ 62#define PSR_PM_CTL 0x0100 /* Performance monitor control reg */ 63#define PSR_PM_COUNT 0x0108 /* Performance monitor counter reg */ 64#define PSR_IOMMU 0x0200 /* IOMMU registers. */ 65#define PSR_PCIA0_INT_MAP 0x0c00 /* PCI bus a slot 0 irq map reg */ 66#define PSR_PCIA1_INT_MAP 0x0c08 /* PCI bus a slot 1 irq map reg */ 67#define PSR_PCIA2_INT_MAP 0x0c10 /* PCI bus a slot 2 irq map reg (IIi) */ 68#define PSR_PCIA3_INT_MAP 0x0c18 /* PCI bus a slot 3 irq map reg (IIi) */ 69#define PSR_PCIB0_INT_MAP 0x0c20 /* PCI bus b slot 0 irq map reg */ 70#define PSR_PCIB1_INT_MAP 0x0c28 /* PCI bus b slot 1 irq map reg */ 71#define PSR_PCIB2_INT_MAP 0x0c30 /* PCI bus b slot 2 irq map reg */ 72#define PSR_PCIB3_INT_MAP 0x0c38 /* PCI bus b slot 3 irq map reg */ 73#define PSR_SCSI_INT_MAP 0x1000 /* SCSI interrupt map reg */ 74#define PSR_ETHER_INT_MAP 0x1008 /* ethernet interrupt map reg */ 75#define PSR_BPP_INT_MAP 0x1010 /* parallel interrupt map reg */ 76#define PSR_AUDIOR_INT_MAP 0x1018 /* audio record interrupt map reg */ 77#define PSR_AUDIOP_INT_MAP 0x1020 /* audio playback interrupt map reg */ 78#define PSR_POWER_INT_MAP 0x1028 /* power fail interrupt map reg */ 79#define PSR_SKBDMS_INT_MAP 0x1030 /* serial/kbd/mouse interrupt map reg */ 80#define PSR_FD_INT_MAP 0x1038 /* floppy interrupt map reg */ 81#define PSR_SPARE_INT_MAP 0x1040 /* spare interrupt map reg */ 82#define PSR_KBD_INT_MAP 0x1048 /* kbd [unused] interrupt map reg */ 83#define PSR_MOUSE_INT_MAP 0x1050 /* mouse [unused] interrupt map reg */ 84#define PSR_SERIAL_INT_MAP 0x1058 /* second serial interrupt map reg */ 85#define PSR_TIMER0_INT_MAP 0x1060 /* timer 0 interrupt map reg */ 86#define PSR_TIMER1_INT_MAP 0x1068 /* timer 1 interrupt map reg */ 87#define PSR_UE_INT_MAP 0x1070 /* UE interrupt map reg */ 88#define PSR_CE_INT_MAP 0x1078 /* CE interrupt map reg */ 89#define PSR_PCIAERR_INT_MAP 0x1080 /* PCI bus a error interrupt map reg */ 90#define PSR_PCIBERR_INT_MAP 0x1088 /* PCI bus b error interrupt map reg */ 91#define PSR_PWRMGT_INT_MAP 0x1090 /* power mgmt wake interrupt map reg */ 92#define PSR_FFB0_INT_MAP 0x1098 /* FFB0 graphics interrupt map reg */ 93#define PSR_FFB1_INT_MAP 0x10a0 /* FFB1 graphics interrupt map reg */ 94/* Note: clear interrupt 0 registers are not really used */ 95#define PSR_PCIA0_INT_CLR 0x1400 /* PCI a slot 0 clear int regs 0..3 */ 96#define PSR_PCIA1_INT_CLR 0x1420 /* PCI a slot 1 clear int regs 0..3 */ 97#define PSR_PCIA2_INT_CLR 0x1440 /* PCI a slot 1 clear int regs 0..3 */ 98#define PSR_PCIA3_INT_CLR 0x1460 /* PCI a slot 1 clear int regs 0..3 */ 99#define PSR_PCIB0_INT_CLR 0x1480 /* PCI b slot 0 clear int regs 0..3 */ 100#define PSR_PCIB1_INT_CLR 0x14a0 /* PCI b slot 1 clear int regs 0..3 */ 101#define PSR_PCIB2_INT_CLR 0x14c0 /* PCI b slot 2 clear int regs 0..3 */ 102#define PSR_PCIB3_INT_CLR 0x14d0 /* PCI b slot 3 clear int regs 0..3 */ 103#define PSR_SCSI_INT_CLR 0x1800 /* SCSI clear int reg */ 104#define PSR_ETHER_INT_CLR 0x1808 /* ethernet clear int reg */ 105#define PSR_BPP_INT_CLR 0x1810 /* parallel clear int reg */ 106#define PSR_AUDIOR_INT_CLR 0x1818 /* audio record clear int reg */ 107#define PSR_AUDIOP_INT_CLR 0x1820 /* audio playback clear int reg */ 108#define PSR_POWER_INT_CLR 0x1828 /* power fail clear int reg */ 109#define PSR_SKBDMS_INT_CLR 0x1830 /* serial/kbd/mouse clear int reg */ 110#define PSR_FD_INT_CLR 0x1838 /* floppy clear int reg */ 111#define PSR_SPARE_INT_CLR 0x1840 /* spare clear int reg */ 112#define PSR_KBD_INT_CLR 0x1848 /* kbd [unused] clear int reg */ 113#define PSR_MOUSE_INT_CLR 0x1850 /* mouse [unused] clear int reg */ 114#define PSR_SERIAL_INT_CLR 0x1858 /* second serial clear int reg */ 115#define PSR_TIMER0_INT_CLR 0x1860 /* timer 0 clear int reg */ 116#define PSR_TIMER1_INT_CLR 0x1868 /* timer 1 clear int reg */ 117#define PSR_UE_INT_CLR 0x1870 /* UE clear int reg */ 118#define PSR_CE_INT_CLR 0x1878 /* CE clear int reg */ 119#define PSR_PCIAERR_INT_CLR 0x1880 /* PCI bus a error clear int reg */ 120#define PSR_PCIBERR_INT_CLR 0x1888 /* PCI bus b error clear int reg */ 121#define PSR_PWRMGT_INT_CLR 0x1890 /* power mgmt wake clr interrupt reg */ 122#define PSR_INTR_RETRY_TIM 0x1a00 /* interrupt retry timer */ 123#define PSR_TC0 0x1c00 /* timer/counter 0 */ 124#define PSR_TC1 0x1c10 /* timer/counter 1 */ 125#define PSR_DMA_WRITE_SYNC 0x1c20 /* PCI DMA write sync register (IIi) */ 126#define PSR_PCICTL0 0x2000 /* PCICTL registers for 1st psycho. */ 127#define PSR_PCICTL1 0x4000 /* PCICTL registers for 2nd psycho. */ 128#define PSR_DMA_SCB_DIAG0 0xa000 /* DMA scoreboard diag reg 0 */ 129#define PSR_DMA_SCB_DIAG1 0xa008 /* DMA scoreboard diag reg 1 */ 130#define PSR_IOMMU_SVADIAG 0xa400 /* IOMMU virtual addr diag reg */ 131#define PSR_IOMMU_TLB_CMP_DIAG 0xa408 /* IOMMU TLB tag compare diag reg */ 132#define PSR_IOMMU_QUEUE_DIAG 0xa500 /* IOMMU LRU queue diag regs 0..15 */ 133#define PSR_IOMMU_TLB_TAG_DIAG 0xa580 /* TLB tag diag regs 0..15 */ 134#define PSR_IOMMU_TLB_DATA_DIAG 0xa600 /* TLB data RAM diag regs 0..15 */ 135#define PSR_PCI_INT_DIAG 0xa800 /* PCI int state diag reg */ 136#define PSR_OBIO_INT_DIAG 0xa808 /* OBIO and misc int state diag reg */ 137#define PSR_STRBUF_DIAG 0xb000 /* Streaming buffer diag regs */ 138/* 139 * Here is the rest of the map, which we're not specifying: 140 * 141 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 142 * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header 143 * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header 144 * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space 145 * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space 146 * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space 147 * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space 148 * 149 * NB: config and I/O space can use 1-4 byte accesses, not 8 byte 150 * accesses. Memory space can use any sized accesses. 151 * 152 * Note that the SUNW,sabre/SUNW,simba combinations found on the 153 * Ultra5 and Ultra10 machines uses slightly differrent addresses 154 * than the above. This is mostly due to the fact that the APB is 155 * a multi-function PCI device with two PCI bridges, and the U2P is 156 * two separate PCI bridges. It uses the same PCI configuration 157 * space, though the configuration header for each PCI bus is 158 * located differently due to the SUNW,simba PCI busses being 159 * function 0 and function 1 of the APB, whereas the psycho's are 160 * each their own PCI device. The I/O and memory spaces are each 161 * split into 8 equally sized areas (8x2MB blocks for I/O space, 162 * and 8x512MB blocks for memory space). These are allocated in to 163 * either PCI A or PCI B, or neither in the APB's `I/O Address Map 164 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) 165 * registers of each simba. We must ensure that both of the 166 * following are correct (the prom should do this for us): 167 * 168 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 169 * 170 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 171 * 172 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 173 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header 174 * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header 175 * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided) 176 * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided) 177 */ |
| 55 | 178 |
| 56 /* PSYCHO control/status register */ /* 1fe.0000.0010 */ 57 u_int64_t psy_csr; 58 /* 59 * 63 59 55 50 45 4 3 2 1 0 60 * +------+------+------+------+--//---+--------+-------+-----+------+ 61 * | IMPL | VERS | MID | IGN | xxx | APCKEN | APERR | IAP | MODE | 62 * +------+------+------+------+--//---+--------+-------+-----+------+ 63 * 64 */ | 179/* 180 * PSR_CS defines: 181 * 182 * 63 59 55 50 45 4 3 2 1 0 183 * +------+------+------+------+--//---+--------+-------+-----+------+ 184 * | IMPL | VERS | MID | IGN | xxx | APCKEN | APERR | IAP | MODE | 185 * +------+------+------+------+--//---+--------+-------+-----+------+ 186 * 187 */ |
| 65#define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf)) 66#define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf)) 67#define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) 68#define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f)) 69#define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */ 70#define PSYCHO_CSR_APERR 4 /* UPA addr parity error */ 71#define PSYCHO_CSR_IAP 2 /* invert UPA address parity */ 72#define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */ 73 | 188#define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf)) 189#define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf)) 190#define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) 191#define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f)) 192#define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */ 193#define PSYCHO_CSR_APERR 4 /* UPA addr parity error */ 194#define PSYCHO_CSR_IAP 2 /* invert UPA address parity */ 195#define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */ 196 |
| 74 u_int64_t pad0; 75 /* ECC control register */ /* 1fe.0000.0020 */ 76 u_int64_t psy_ecccr; 77 /* 1fe.0000.0028 */ 78 u_int64_t reserved; 79 /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */ 80 u_int64_t psy_ue_afsr; 81 /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */ 82 u_int64_t psy_ue_afar; 83 /* Correctable Error AFSR */ /* 1fe.0000.0040 */ 84 u_int64_t psy_ce_afsr; 85 /* Correctable Error AFAR */ /* 1fe.0000.0048 */ 86 u_int64_t psy_ce_afar; | 197/* Offsets into the PSR_PCICTL* register block. */ 198#define PCR_CS 0x0000 /* PCI control/status register */ 199#define PCR_AFS 0x0010 /* PCI AFSR register */ 200#define PCR_AFA 0x0018 /* PCI AFAR register */ 201#define PCR_DIAG 0x0020 /* PCI diagnostic register */ 202#define PCR_TAS 0x0028 /* PCI target address space reg (IIi) */ 203#define PCR_STRBUF 0x0800 /* IOMMU streaming buffer registers. */ |
| 87 | 204 |
| 88 u_int64_t pad1[22]; 89 90 struct perfmon { 91 /* Performance monitor control reg */ /* 1fe.0000.0100 */ 92 u_int64_t pm_cr; 93 /* Performance monitor counter reg */ /* 1fe.0000.0108 */ 94 u_int64_t pm_count; 95 } psy_pm; 96 97 u_int64_t pad2[30]; 98 99 /* 1fe.0000.0200,0210 */ 100 struct iommureg psy_iommu; 101 102 u_int64_t pad3[317]; 103 104 /* PCI bus a slot 0 irq map reg */ /* 1fe.0000.0c00 */ 105 u_int64_t pcia0_int_map; 106 /* PCI bus a slot 1 irq map reg */ /* 1fe.0000.0c08 */ 107 u_int64_t pcia1_int_map; 108 /* PCI bus a slot 2 irq map reg (IIi) */ /* 1fe.0000.0c10 */ 109 u_int64_t pcia2_int_map; 110 /* PCI bus a slot 3 irq map reg (IIi) */ /* 1fe.0000.0c18 */ 111 u_int64_t pcia3_int_map; 112 /* PCI bus b slot 0 irq map reg */ /* 1fe.0000.0c20 */ 113 u_int64_t pcib0_int_map; 114 /* PCI bus b slot 1 irq map reg */ /* 1fe.0000.0c28 */ 115 u_int64_t pcib1_int_map; 116 /* PCI bus b slot 2 irq map reg */ /* 1fe.0000.0c30 */ 117 u_int64_t pcib2_int_map; 118 /* PCI bus b slot 3 irq map reg */ /* 1fe.0000.0c38 */ 119 u_int64_t pcib3_int_map; 120 121 u_int64_t pad4[120]; 122 123 /* SCSI interrupt map reg */ /* 1fe.0000.1000 */ 124 u_int64_t scsi_int_map; 125 /* ethernet interrupt map reg */ /* 1fe.0000.1008 */ 126 u_int64_t ether_int_map; 127 /* parallel interrupt map reg */ /* 1fe.0000.1010 */ 128 u_int64_t bpp_int_map; 129 /* audio record interrupt map reg */ /* 1fe.0000.1018 */ 130 u_int64_t audior_int_map; 131 /* audio playback interrupt map reg */ /* 1fe.0000.1020 */ 132 u_int64_t audiop_int_map; 133 /* power fail interrupt map reg */ /* 1fe.0000.1028 */ 134 u_int64_t power_int_map; 135 /* serial/kbd/mouse interrupt map reg */ /* 1fe.0000.1030 */ 136 u_int64_t ser_kbd_ms_int_map; 137 /* floppy interrupt map reg */ /* 1fe.0000.1038 */ 138 u_int64_t fd_int_map; 139 /* spare interrupt map reg */ /* 1fe.0000.1040 */ 140 u_int64_t spare_int_map; 141 /* kbd [unused] interrupt map reg */ /* 1fe.0000.1048 */ 142 u_int64_t kbd_int_map; 143 /* mouse [unused] interrupt map reg */ /* 1fe.0000.1050 */ 144 u_int64_t mouse_int_map; 145 /* second serial interrupt map reg */ /* 1fe.0000.1058 */ 146 u_int64_t serial_int_map; 147 /* timer 0 interrupt map reg */ /* 1fe.0000.1060 */ 148 u_int64_t timer0_int_map; 149 /* timer 1 interrupt map reg */ /* 1fe.0000.1068 */ 150 u_int64_t timer1_int_map; 151 /* UE interrupt map reg */ /* 1fe.0000.1070 */ 152 u_int64_t ue_int_map; 153 /* CE interrupt map reg */ /* 1fe.0000.1078 */ 154 u_int64_t ce_int_map; 155 /* PCI bus a error interrupt map reg */ /* 1fe.0000.1080 */ 156 u_int64_t pciaerr_int_map; 157 /* PCI bus b error interrupt map reg */ /* 1fe.0000.1088 */ 158 u_int64_t pciberr_int_map; 159 /* power mgmt wake interrupt map reg */ /* 1fe.0000.1090 */ 160 u_int64_t pwrmgt_int_map; 161 /* FFB0 graphics interrupt map reg */ /* 1fe.0000.1098 */ 162 u_int64_t ffb0_int_map; 163 /* FFB1 graphics interrupt map reg */ /* 1fe.0000.10a0 */ 164 u_int64_t ffb1_int_map; 165 166 u_int64_t pad5[107]; 167 168 /* Note: clear interrupt 0 registers are not really used */ 169 170 /* PCI a slot 0 clear int regs 0..7 */ /* 1fe.0000.1400-1418 */ 171 u_int64_t pcia0_int_clr[4]; 172 /* PCI a slot 1 clear int regs 0..7 */ /* 1fe.0000.1420-1438 */ 173 u_int64_t pcia1_int_clr[4]; 174 /* PCI a slot 2 clear int regs 0..7 */ /* 1fe.0000.1440-1458 */ 175 u_int64_t pcia2_int_clr[4]; 176 /* PCI a slot 3 clear int regs 0..7 */ /* 1fe.0000.1480-1478 */ 177 u_int64_t pcia3_int_clr[4]; 178 /* PCI b slot 0 clear int regs 0..7 */ /* 1fe.0000.1480-1498 */ 179 u_int64_t pcib0_int_clr[4]; 180 /* PCI b slot 1 clear int regs 0..7 */ /* 1fe.0000.14a0-14b8 */ 181 u_int64_t pcib1_int_clr[4]; 182 /* PCI b slot 2 clear int regs 0..7 */ /* 1fe.0000.14c0-14d8 */ 183 u_int64_t pcib2_int_clr[4]; 184 /* PCI b slot 3 clear int regs 0..7 */ /* 1fe.0000.14d0-14f8 */ 185 u_int64_t pcib3_int_clr[4]; 186 187 u_int64_t pad6[96]; 188 189 /* SCSI clear int reg */ /* 1fe.0000.1800 */ 190 u_int64_t scsi_int_clr; 191 /* ethernet clear int reg */ /* 1fe.0000.1808 */ 192 u_int64_t ether_int_clr; 193 /* parallel clear int reg */ /* 1fe.0000.1810 */ 194 u_int64_t bpp_int_clr; 195 /* audio record clear int reg */ /* 1fe.0000.1818 */ 196 u_int64_t audior_int_clr; 197 /* audio playback clear int reg */ /* 1fe.0000.1820 */ 198 u_int64_t audiop_int_clr; 199 /* power fail clear int reg */ /* 1fe.0000.1828 */ 200 u_int64_t power_int_clr; 201 /* serial/kbd/mouse clear int reg */ /* 1fe.0000.1830 */ 202 u_int64_t ser_kb_ms_int_clr; 203 /* floppy clear int reg */ /* 1fe.0000.1838 */ 204 u_int64_t fd_int_clr; 205 /* spare clear int reg */ /* 1fe.0000.1840 */ 206 u_int64_t spare_int_clr; 207 /* kbd [unused] clear int reg */ /* 1fe.0000.1848 */ 208 u_int64_t kbd_int_clr; 209 /* mouse [unused] clear int reg */ /* 1fe.0000.1850 */ 210 u_int64_t mouse_int_clr; 211 /* second serial clear int reg */ /* 1fe.0000.1858 */ 212 u_int64_t serial_clr; 213 /* timer 0 clear int reg */ /* 1fe.0000.1860 */ 214 u_int64_t timer0_int_clr; 215 /* timer 1 clear int reg */ /* 1fe.0000.1868 */ 216 u_int64_t timer1_int_clr; 217 /* UE clear int reg */ /* 1fe.0000.1870 */ 218 u_int64_t ue_int_clr; 219 /* CE clear int reg */ /* 1fe.0000.1878 */ 220 u_int64_t ce_int_clr; 221 /* PCI bus a error clear int reg */ /* 1fe.0000.1880 */ 222 u_int64_t pciaerr_int_clr; 223 /* PCI bus b error clear int reg */ /* 1fe.0000.1888 */ 224 u_int64_t pciberr_int_clr; 225 /* power mgmt wake clr interrupt reg */ /* 1fe.0000.1890 */ 226 u_int64_t pwrmgt_int_clr; 227 228 u_int64_t pad7[45]; 229 230 /* interrupt retry timer */ /* 1fe.0000.1a00 */ 231 u_int64_t intr_retry_timer; 232 233 u_int64_t pad8[63]; 234 235 struct timer_counter { 236 /* timer/counter 0/1 count register */ /* 1fe.0000.1c00,1c10 */ 237 u_int64_t tc_count; 238 /* timer/counter 0/1 limit register */ /* 1fe.0000.1c08,1c18 */ 239 u_int64_t tc_limit; 240 } tc[2]; 241 242 /* PCI DMA write sync register (IIi) */ /* 1fe.0000.1c20 */ 243 u_int64_t pci_dma_write_sync; 244 245 u_int64_t pad9[123]; 246 247 struct pci_ctl { 248 /* PCI a/b control/status register */ /* 1fe.0000.2000,4000 */ 249 u_int64_t pci_csr; 250 u_int64_t pad10; 251 /* PCI a/b AFSR register */ /* 1fe.0000.2010,4010 */ 252 u_int64_t pci_afsr; 253 /* PCI a/b AFAR register */ /* 1fe.0000.2018,4018 */ 254 u_int64_t pci_afar; 255 /* PCI a/b diagnostic register */ /* 1fe.0000.2020,4020 */ 256 u_int64_t pci_diag; 257 /* PCI target address space reg (IIi)*/ /* 1fe.0000.2028,4028 */ 258 u_int64_t pci_tasr; 259 260 u_int64_t pad11[250]; 261 262 /* This is really the IOMMU's, not the PCI bus's */ 263 /* 1fe.0000.2800-210 */ 264 struct iommu_strbuf pci_strbuf; 265#define psy_iommu_strbuf psy_pcictl[0].pci_strbuf 266 267 u_int64_t pad12[765]; 268 } psy_pcictl[2]; /* For PCI a and b */ 269 270 /* 271 * NB: FFB0 and FFB1 intr map regs also appear at 1fe.0000.6000 and 272 * 1fe.0000.8000 respectively 273 */ 274 u_int64_t pad13[2048]; 275 276 /* DMA scoreboard diag reg 0 */ /* 1fe.0000.a000 */ 277 u_int64_t dma_scb_diag0; 278 /* DMA scoreboard diag reg 1 */ /* 1fe.0000.a008 */ 279 u_int64_t dma_scb_diag1; 280 281 u_int64_t pad14[126]; 282 283 /* IOMMU virtual addr diag reg */ /* 1fe.0000.a400 */ 284 u_int64_t iommu_svadiag; 285 /* IOMMU TLB tag compare diag reg */ /* 1fe.0000.a408 */ 286 u_int64_t iommu_tlb_comp_diag; 287 288 u_int64_t pad15[30]; 289 290 /* IOMMU LRU queue diag */ /* 1fe.0000.a500-a578 */ 291 u_int64_t iommu_queue_diag[16]; 292 /* TLB tag diag */ /* 1fe.0000.a580-a5f8 */ 293 u_int64_t tlb_tag_diag[16]; 294 /* TLB data RAM diag */ /* 1fe.0000.a600-a678 */ 295 u_int64_t tlb_data_diag[16]; 296 297 u_int64_t pad16[48]; 298 299 /* PCI int state diag reg */ /* 1fe.0000.a800 */ 300 u_int64_t pci_int_diag; 301 /* OBIO and misc int state diag reg */ /* 1fe.0000.a808 */ 302 u_int64_t obio_int_diag; 303 304 u_int64_t pad17[254]; 305 306 struct strbuf_diag { 307 /* streaming buffer data RAM diag */ /* 1fe.0000.b000-b3f8 */ 308 u_int64_t strbuf_data_diag[128]; 309 /* streaming buffer error status diag *//* 1fe.0000.b400-b7f8 */ 310 u_int64_t strbuf_error_diag[128]; 311 /* streaming buffer page tag diag */ /* 1fe.0000.b800-b878 */ 312 u_int64_t strbuf_pg_tag_diag[16]; 313 u_int64_t pad18[16]; 314 /* streaming buffer line tag diag */ /* 1fe.0000.b900-b978 */ 315 u_int64_t strbuf_ln_tag_diag[16]; 316 u_int64_t pad19[208]; 317 } psy_strbufdiag[2]; /* For PCI a and b */ 318 319 /* 320 * Here is the rest of the map, which we're not specifying: 321 * 322 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 323 * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header 324 * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header 325 * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space 326 * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space 327 * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space 328 * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space 329 * 330 * NB: config and I/O space can use 1-4 byte accesses, not 8 byte 331 * accesses. Memory space can use any sized accesses. 332 * 333 * Note that the SUNW,sabre/SUNW,simba combinations found on the 334 * Ultra5 and Ultra10 machines uses slightly differrent addresses 335 * than the above. This is mostly due to the fact that the APB is 336 * a multi-function PCI device with two PCI bridges, and the U2P is 337 * two separate PCI bridges. It uses the same PCI configuration 338 * space, though the configuration header for each PCI bus is 339 * located differently due to the SUNW,simba PCI busses being 340 * function 0 and function 1 of the APB, whereas the psycho's are 341 * each their own PCI device. The I/O and memory spaces are each 342 * split into 8 equally sized areas (8x2MB blocks for I/O space, 343 * and 8x512MB blocks for memory space). These are allocated in to 344 * either PCI A or PCI B, or neither in the APB's `I/O Address Map 345 * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) 346 * registers of each simba. We must ensure that both of the 347 * following are correct (the prom should do this for us): 348 * 349 * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 350 * 351 * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 352 * 353 * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 354 * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header 355 * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header 356 * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided) 357 * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided) 358 */ 359}; 360 | 205/* Device space defines. */ |
| 361#define PSYCHO_CONF_SIZE 0x1000000 362#define PSYCHO_CONF_BUS_SHIFT 16 363#define PSYCHO_CONF_DEV_SHIFT 11 364#define PSYCHO_CONF_FUNC_SHIFT 8 365#define PSYCHO_CONF_REG_SHIFT 0 366#define PSYCHO_IO_SIZE 0x1000000 367#define PSYCHO_MEM_SIZE 0x100000000 368 --- 69 unchanged lines hidden --- | 206#define PSYCHO_CONF_SIZE 0x1000000 207#define PSYCHO_CONF_BUS_SHIFT 16 208#define PSYCHO_CONF_DEV_SHIFT 11 209#define PSYCHO_CONF_FUNC_SHIFT 8 210#define PSYCHO_CONF_REG_SHIFT 0 211#define PSYCHO_IO_SIZE 0x1000000 212#define PSYCHO_MEM_SIZE 0x100000000 213 --- 69 unchanged lines hidden --- |