1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org> 6 * Copyright (c) 2005 - 2009 Marius Strobl <marius@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h>
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94}; 95 96struct ofw_pcibus_devinfo { 97 struct pci_devinfo opd_dinfo; 98 struct ofw_bus_devinfo opd_obdinfo; 99}; 100 101static devclass_t pci_devclass; 102 103DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */, 104 pci_driver); 105EARLY_DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0, 106 BUS_PASS_BUS); 107MODULE_VERSION(ofw_pcibus, 1); 108MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1); 109 110static int 111ofw_pcibus_probe(device_t dev) 112{ 113 114 if (ofw_bus_get_node(dev) == 0) 115 return (ENXIO); 116 device_set_desc(dev, "OFW PCI bus"); 117 118 return (0); 119} 120 121/* 122 * Perform miscellaneous setups the firmware usually does not do for us. 123 */ 124static void 125ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno, 126 u_int slot, u_int func) 127{ 128#define CS_READ(n, w) \ 129 PCIB_READ_CONFIG(bridge, busno, slot, func, (n), (w)) 130#define CS_WRITE(n, v, w) \ 131 PCIB_WRITE_CONFIG(bridge, busno, slot, func, (n), (v), (w)) 132 133#ifndef SUN4V 134 uint32_t reg; 135 136 /* 137 * Initialize the latency timer register for busmaster devices to 138 * work properly. This is another task which the firmware doesn't 139 * always perform. The Min_Gnt register can be used to compute its 140 * recommended value: it contains the desired latency in units of 141 * 1/4 us assuming a clock rate of 33MHz. To calculate the correct 142 * latency timer value, the clock frequency of the bus (defaulting 143 * to 33MHz) should be used and no wait states assumed. 144 * For bridges, we additionally set up the bridge control and the 145 * secondary latency registers. 146 */ 147 if ((CS_READ(PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) == 148 PCIM_HDRTYPE_BRIDGE) { 149 reg = CS_READ(PCIR_BRIDGECTL_1, 1); 150 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE | 151 PCIB_BCR_PERR_ENABLE; 152#ifdef OFW_PCI_DEBUG 153 device_printf(bridge, 154 "bridge %d/%d/%d: control 0x%x -> 0x%x\n", 155 busno, slot, func, CS_READ(PCIR_BRIDGECTL_1, 1), reg); 156#endif /* OFW_PCI_DEBUG */ 157 CS_WRITE(PCIR_BRIDGECTL_1, reg, 1); 158 159 reg = OFW_PCI_LATENCY; 160#ifdef OFW_PCI_DEBUG 161 device_printf(bridge, 162 "bridge %d/%d/%d: latency timer %d -> %d\n", 163 busno, slot, func, CS_READ(PCIR_SECLAT_1, 1), reg); 164#endif /* OFW_PCI_DEBUG */ 165 CS_WRITE(PCIR_SECLAT_1, reg, 1); 166 } else { 167 reg = CS_READ(PCIR_MINGNT, 1); 168 if ((int)reg > 0) { 169 switch (clock) { 170 case 33000000: 171 reg *= 8; 172 break; 173 case 66000000: 174 reg *= 4; 175 break; 176 } 177 reg = min(reg, 255); 178 } else 179 reg = OFW_PCI_LATENCY; 180 } 181#ifdef OFW_PCI_DEBUG 182 device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n", 183 busno, slot, func, CS_READ(PCIR_LATTIMER, 1), reg); 184#endif /* OFW_PCI_DEBUG */ 185 CS_WRITE(PCIR_LATTIMER, reg, 1); 186 187 /* 188 * Compute a value to write into the cache line size register. 189 * The role of the streaming cache is unclear in write invalidate 190 * transfers, so it is made sure that it's line size is always 191 * reached. Generally, the cache line size is fixed at 64 bytes 192 * by Fireplane/Safari, JBus and UPA. 193 */ 194 CS_WRITE(PCIR_CACHELNSZ, STRBUF_LINESZ / sizeof(uint32_t), 1); 195#endif 196 197 /* 198 * Ensure that ALi M5229 report the actual content of PCIR_PROGIF 199 * and that IDE I/O is force enabled. The former is done in order 200 * to have unique behavior across revisions as some default to 201 * hiding bits 4-6 for compliance with PCI 2.3. The latter is done 202 * as at least revision 0xc8 requires the PCIM_CMD_PORTEN bypass 203 * to be always enabled as otherwise even enabling PCIM_CMD_PORTEN 204 * results in an instant data access trap on Fire-based machines. 205 * Thus these quirks have to be handled before pci(4) adds the maps. 206 * Note that for older revisions bit 0 of register 0x50 enables the 207 * internal IDE function instead of force enabling IDE I/O. 208 */ 209 if ((CS_READ(PCIR_VENDOR, 2) == 0x10b9 && 210 CS_READ(PCIR_DEVICE, 2) == 0x5229)) 211 CS_WRITE(0x50, CS_READ(0x50, 1) | 0x3, 1); 212 213 /* 214 * The preset in the intline register is usually wrong. Reset 215 * it to 255, so that the PCI code will reroute the interrupt if 216 * needed. 217 */ 218 CS_WRITE(PCIR_INTLINE, PCI_INVALID_IRQ, 1); 219 220#undef CS_READ 221#undef CS_WRITE 222} 223 224static int 225ofw_pcibus_attach(device_t dev) 226{ 227 device_t pcib; 228 struct ofw_pci_register pcir; 229 struct ofw_pcibus_devinfo *dinfo; 230 phandle_t node, child; 231 uint32_t clock; 232 u_int busno, domain, func, slot; 233 234 pcib = device_get_parent(dev); 235 domain = pcib_get_domain(dev); 236 busno = pcib_get_bus(dev); 237 if (bootverbose) 238 device_printf(dev, "domain=%d, physical bus=%d\n", 239 domain, busno); 240 node = ofw_bus_get_node(dev); 241 242 /* 243 * Add the PCI side of the host-PCI bridge itself to the bus. 244 * Note that we exclude the host-PCIe bridges here as these 245 * have no configuration space implemented themselves. 246 */ 247 if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 && 248 ofw_bus_get_type(pcib) != NULL && 249 strcmp(ofw_bus_get_type(pcib), OFW_TYPE_PCIE) != 0 && 250 (dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, 251 domain, busno, 0, 0, sizeof(*dinfo))) != NULL) { 252 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0) 253 pci_freecfg((struct pci_devinfo *)dinfo); 254 else 255 pci_add_child(dev, (struct pci_devinfo *)dinfo); 256 } 257 258 if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock, 259 sizeof(clock)) == -1) 260 clock = 33000000; 261 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 262 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1) 263 continue; 264 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi); 265 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi); 266 /* Some OFW device trees contain dupes. */ 267 if (pci_find_dbsf(domain, busno, slot, func) != NULL) 268 continue; 269 ofw_pcibus_setup_device(pcib, clock, busno, slot, func); 270 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, 271 domain, busno, slot, func, sizeof(*dinfo)); 272 if (dinfo == NULL) 273 continue; 274 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 275 0) { 276 pci_freecfg((struct pci_devinfo *)dinfo); 277 continue; 278 } 279 pci_add_child(dev, (struct pci_devinfo *)dinfo); 280 OFW_PCI_SETUP_DEVICE(pcib, dinfo->opd_dinfo.cfg.dev); 281 } 282 283 return (bus_generic_attach(dev)); 284} 285 286static int 287ofw_pcibus_assign_interrupt(device_t dev, device_t child) 288{ 289 ofw_pci_intr_t intr; 290 int isz; 291 292 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr, 293 sizeof(intr)); 294 if (isz != sizeof(intr)) { 295 /* No property; our best guess is the intpin. */ 296 intr = pci_get_intpin(child); 297#ifndef SUN4V 298 } else if (intr >= 255) { 299 /* 300 * A fully specified interrupt (including IGN), as present on 301 * SPARCengine Ultra AX and E450. Extract the INO and return 302 * it. 303 */ 304 return (INTINO(intr)); 305#endif 306 } 307 /* 308 * If we got intr from a property, it may or may not be an intpin. 309 * For on-board devices, it frequently is not, and is completely out 310 * of the valid intpin range. For PCI slots, it hopefully is, 311 * otherwise we will have trouble interfacing with non-OFW buses 312 * such as cardbus. 313 * Since we cannot tell which it is without violating layering, we 314 * will always use the route_interrupt method, and treat exceptions 315 * on the level they become apparent. 316 */ 317 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr)); 318} 319 320static const struct ofw_bus_devinfo * 321ofw_pcibus_get_devinfo(device_t bus, device_t dev) 322{ 323 struct ofw_pcibus_devinfo *dinfo; 324 325 dinfo = device_get_ivars(dev); 326 return (&dinfo->opd_obdinfo); 327} 328 329static int 330ofw_pcibus_pnpinfo_str(device_t dev, device_t child, char *buf, 331 size_t buflen) 332{ 333 334 pci_child_pnpinfo_str_method(dev, child, buf, buflen); 335 if (ofw_bus_get_node(child) != -1) { 336 strlcat(buf, " ", buflen); /* Separate info. */ 337 ofw_bus_gen_child_pnpinfo_str(dev, child, buf, buflen); 338 } 339 340 return (0); 341}
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