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tlb.h (91616) tlb.h (91782)
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 91616 2002-03-04 07:07:10Z jake $
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 91782 2002-03-07 05:25:15Z jake $
27 */
28
29#ifndef _MACHINE_TLB_H_
30#define _MACHINE_TLB_H_
31
32#define TLB_SLOT_COUNT 64
33
34#define TLB_SLOT_TSB_KERNEL_MIN 62 /* XXX */

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99static __inline void
100tlb_dtlb_context_primary_demap(void)
101{
102 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
103 membar(Sync);
104}
105
106static __inline void
27 */
28
29#ifndef _MACHINE_TLB_H_
30#define _MACHINE_TLB_H_
31
32#define TLB_SLOT_COUNT 64
33
34#define TLB_SLOT_TSB_KERNEL_MIN 62 /* XXX */

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99static __inline void
100tlb_dtlb_context_primary_demap(void)
101{
102 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
103 membar(Sync);
104}
105
106static __inline void
107tlb_dtlb_page_demap(u_long ctx, vm_offset_t va)
107tlb_dtlb_page_demap(struct pmap *pm, vm_offset_t va)
108{
108{
109 u_int ctx;
110
111 ctx = pm->pm_context[PCPU_GET(cpuid)];
109 if (ctx == TLB_CTX_KERNEL) {
110 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
111 ASI_DMMU_DEMAP, 0);
112 membar(Sync);
113 } else if (ctx != -1) {
114 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
115 ASI_DMMU_DEMAP, 0);
116 membar(Sync);

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145static __inline void
146tlb_itlb_context_primary_demap(void)
147{
148 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
149 membar(Sync);
150}
151
152static __inline void
112 if (ctx == TLB_CTX_KERNEL) {
113 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
114 ASI_DMMU_DEMAP, 0);
115 membar(Sync);
116 } else if (ctx != -1) {
117 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
118 ASI_DMMU_DEMAP, 0);
119 membar(Sync);

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148static __inline void
149tlb_itlb_context_primary_demap(void)
150{
151 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
152 membar(Sync);
153}
154
155static __inline void
153tlb_itlb_page_demap(u_long ctx, vm_offset_t va)
156tlb_itlb_page_demap(struct pmap *pm, vm_offset_t va)
154{
157{
158 u_int ctx;
159
160 ctx = pm->pm_context[PCPU_GET(cpuid)];
155 if (ctx == TLB_CTX_KERNEL) {
156 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
157 ASI_IMMU_DEMAP, 0);
158 flush(KERNBASE);
159 } else if (ctx != -1) {
160 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
161 ASI_IMMU_DEMAP, 0);
162 membar(Sync);

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179 * user page.
180 */
181 membar(Sync);
182 }
183 intr_restore(pst);
184}
185
186static __inline void
161 if (ctx == TLB_CTX_KERNEL) {
162 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
163 ASI_IMMU_DEMAP, 0);
164 flush(KERNBASE);
165 } else if (ctx != -1) {
166 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
167 ASI_IMMU_DEMAP, 0);
168 membar(Sync);

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185 * user page.
186 */
187 membar(Sync);
188 }
189 intr_restore(pst);
190}
191
192static __inline void
187tlb_context_demap(u_int ctx)
193tlb_context_demap(struct pmap *pm)
188{
194{
195 u_int ctx;
196
197 ctx = pm->pm_context[PCPU_GET(cpuid)];
189 if (ctx != -1) {
190 tlb_dtlb_context_primary_demap();
191 tlb_itlb_context_primary_demap();
192 }
193}
194
195static __inline void
196tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
197{
198 u_long pst;
199
200 pst = intr_disable();
201 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
202 stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
203 flush(va);
204 intr_restore(pst);
205}
206
207static __inline void
198 if (ctx != -1) {
199 tlb_dtlb_context_primary_demap();
200 tlb_itlb_context_primary_demap();
201 }
202}
203
204static __inline void
205tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
206{
207 u_long pst;
208
209 pst = intr_disable();
210 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
211 stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
212 flush(va);
213 intr_restore(pst);
214}
215
216static __inline void
208tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
217tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va)
209{
210 if (tlb & TLB_DTLB)
218{
219 if (tlb & TLB_DTLB)
211 tlb_dtlb_page_demap(ctx, va);
220 tlb_dtlb_page_demap(pm, va);
212 if (tlb & TLB_ITLB)
221 if (tlb & TLB_ITLB)
213 tlb_itlb_page_demap(ctx, va);
222 tlb_itlb_page_demap(pm, va);
214}
215
216static __inline void
223}
224
225static __inline void
217tlb_range_demap(u_int ctx, vm_offset_t start, vm_offset_t end)
226tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
218{
219 for (; start < end; start += PAGE_SIZE)
227{
228 for (; start < end; start += PAGE_SIZE)
220 tlb_page_demap(TLB_DTLB | TLB_ITLB, ctx, start);
229 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, start);
221}
222
223static __inline void
230}
231
232static __inline void
224tlb_tte_demap(struct tte tte, u_int ctx)
233tlb_tte_demap(struct tte tte, struct pmap *pm)
225{
234{
226 tlb_page_demap(TD_GET_TLB(tte.tte_data), ctx, TV_GET_VA(tte.tte_vpn));
235 tlb_page_demap(TD_GET_TLB(tte.tte_data), pm, TV_GET_VA(tte.tte_vpn));
227}
228
229static __inline void
230tlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte)
231{
232 KASSERT(ctx != -1, ("tlb_store: invalid context"));
233 if (tlb & TLB_DTLB)
234 tlb_dtlb_store(va, ctx, tte);

--- 15 unchanged lines hidden --- 		236}
237
238static __inline void
239tlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte)
240{
241 KASSERT(ctx != -1, ("tlb_store: invalid context"));
242 if (tlb & TLB_DTLB)
243 tlb_dtlb_store(va, ctx, tte);

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