Deleted Added
sdiff udiff text old ( 88629 ) new ( 91170 )
full compact
tlb.h (88629) tlb.h (91170)
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 88629 2001-12-29 07:07:35Z jake $
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 91170 2002-02-23 20:59:35Z jake $
27 */
28
29#ifndef _MACHINE_TLB_H_
30#define _MACHINE_TLB_H_
31
32#define TLB_SLOT_COUNT 64
33
34#define TLB_SLOT_TSB_KERNEL_MIN 60 /* XXX */

--- 49 unchanged lines hidden (view full) ---

84
85/*
86 * Some tlb operations must be atomical, so no interrupt or trap can be allowed
87 * while they are in progress. Traps should not happen, but interrupts need to
88 * be explicitely disabled. critical_enter() cannot be used here, since it only
89 * disables soft interrupts.
90 * XXX: is something like this needed elsewhere, too?
91 */
27 */
28
29#ifndef _MACHINE_TLB_H_
30#define _MACHINE_TLB_H_
31
32#define TLB_SLOT_COUNT 64
33
34#define TLB_SLOT_TSB_KERNEL_MIN 60 /* XXX */

--- 49 unchanged lines hidden (view full) ---

84
85/*
86 * Some tlb operations must be atomical, so no interrupt or trap can be allowed
87 * while they are in progress. Traps should not happen, but interrupts need to
88 * be explicitely disabled. critical_enter() cannot be used here, since it only
89 * disables soft interrupts.
90 * XXX: is something like this needed elsewhere, too?
91 */
92#define TLB_ATOMIC_START(s) do { \
93 (s) = rdpr(pstate); \
94 wrpr(pstate, (s) & ~PSTATE_IE, 0); \
95} while (0)
96#define TLB_ATOMIC_END(s) wrpr(pstate, (s), 0)
97
98static __inline void
99tlb_dtlb_context_primary_demap(void)
100{
101 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
102 membar(Sync);
103}
104

--- 15 unchanged lines hidden (view full) ---

120 }
121}
122
123static __inline void
124tlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte)
125{
126 u_long pst;
127
92
93static __inline void
94tlb_dtlb_context_primary_demap(void)
95{
96 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
97 membar(Sync);
98}
99

--- 15 unchanged lines hidden (view full) ---

115 }
116}
117
118static __inline void
119tlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte)
120{
121 u_long pst;
122
128 TLB_ATOMIC_START(pst);
123 pst = intr_disable();
129 stxa(AA_DMMU_TAR, ASI_DMMU,
130 TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
131 stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
132 membar(Sync);
124 stxa(AA_DMMU_TAR, ASI_DMMU,
125 TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
126 stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
127 membar(Sync);
133 TLB_ATOMIC_END(pst);
128 intr_restore(pst);
134}
135
136static __inline void
137tlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
138{
139 u_long pst;
140
129}
130
131static __inline void
132tlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
133{
134 u_long pst;
135
141 TLB_ATOMIC_START(pst);
136 pst = intr_disable();
142 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
143 stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
144 membar(Sync);
137 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
138 stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
139 membar(Sync);
145 TLB_ATOMIC_END(pst);
140 intr_restore(pst);
146}
147
148static __inline void
149tlb_itlb_context_primary_demap(void)
150{
151 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
152 membar(Sync);
153}

--- 17 unchanged lines hidden (view full) ---

171 }
172}
173
174static __inline void
175tlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte)
176{
177 u_long pst;
178
141}
142
143static __inline void
144tlb_itlb_context_primary_demap(void)
145{
146 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
147 membar(Sync);
148}

--- 17 unchanged lines hidden (view full) ---

166 }
167}
168
169static __inline void
170tlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte)
171{
172 u_long pst;
173
179 TLB_ATOMIC_START(pst);
174 pst = intr_disable();
180 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
181 stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data);
182 if (ctx == TLB_CTX_KERNEL)
183 flush(va);
184 else {
185 /*
186 * flush probably not needed and impossible here, no access to
187 * user page.
188 */
189 membar(Sync);
190 }
175 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
176 stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data);
177 if (ctx == TLB_CTX_KERNEL)
178 flush(va);
179 else {
180 /*
181 * flush probably not needed and impossible here, no access to
182 * user page.
183 */
184 membar(Sync);
185 }
191 TLB_ATOMIC_END(pst);
186 intr_restore(pst);
192}
193
194static __inline void
195tlb_context_primary_demap(u_int tlb)
196{
197 if (tlb & TLB_DTLB)
198 tlb_dtlb_context_primary_demap();
199 if (tlb & TLB_ITLB)
200 tlb_itlb_context_primary_demap();
201}
202
203static __inline void
204tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
205{
206 u_long pst;
207
187}
188
189static __inline void
190tlb_context_primary_demap(u_int tlb)
191{
192 if (tlb & TLB_DTLB)
193 tlb_dtlb_context_primary_demap();
194 if (tlb & TLB_ITLB)
195 tlb_itlb_context_primary_demap();
196}
197
198static __inline void
199tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
200{
201 u_long pst;
202
208 TLB_ATOMIC_START(pst);
203 pst = intr_disable();
209 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
210 stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
211 flush(va);
204 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
205 stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
206 flush(va);
212 TLB_ATOMIC_END(pst);
207 intr_restore(pst);
213}
214
215static __inline void
216tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
217{
218 if (tlb & TLB_DTLB)
219 tlb_dtlb_page_demap(ctx, va);
220 if (tlb & TLB_ITLB)

--- 22 unchanged lines hidden --- 		208}
209
210static __inline void
211tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
212{
213 if (tlb & TLB_DTLB)
214 tlb_dtlb_page_demap(ctx, va);
215 if (tlb & TLB_ITLB)

--- 22 unchanged lines hidden ---