1/*-
2 * Copyright (c) 2001 Jake Burkholder.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/sparc64/include/tlb.h 85234 2001-10-20 15:58:31Z jake $
27 */
28
29#ifndef _MACHINE_TLB_H_
30#define _MACHINE_TLB_H_
31
32#define TLB_SLOT_COUNT 64
33
34#define TLB_SLOT_TSB_KERNEL_MIN 60 /* XXX */

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77#define MMU_SFSR_FV_SHIFT (0)
78
79#define MMU_SFSR_ASI_SIZE (8)
80#define MMU_SFSR_FT_SIZE (6)
81#define MMU_SFSR_CT_SIZE (2)
82
83#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT)
84
85static __inline void
86tlb_dtlb_page_demap(u_long ctx, vm_offset_t va)
87{
88 if (ctx == TLB_CTX_KERNEL) {
89 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
90 ASI_DMMU_DEMAP, 0);
91 membar(Sync);
92 } else {
93 stxa(AA_DMMU_SCXR, ASI_DMMU, ctx);
94 membar(Sync);
95 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE,
96 ASI_DMMU_DEMAP, 0);
97 stxa(AA_DMMU_SCXR, ASI_DMMU, 0);
98 membar(Sync);
99 }
100}
101
102static __inline void
103tlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte)
104{
105 stxa(AA_DMMU_TAR, ASI_DMMU,
106 TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
107 stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
108 membar(Sync);
109}
110
111static __inline void
112tlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
113{
114 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
115 stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
116 membar(Sync);
117}
118
119static __inline void
120tlb_itlb_page_demap(u_long ctx, vm_offset_t va)
121{
122 if (ctx == TLB_CTX_KERNEL) {
123 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
124 ASI_IMMU_DEMAP, 0);
125 flush(KERNBASE);
126 } else {
127 stxa(AA_DMMU_SCXR, ASI_DMMU, ctx);
128 membar(Sync);
129 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_SECONDARY | TLB_DEMAP_PAGE,
130 ASI_IMMU_DEMAP, 0);
131 stxa(AA_DMMU_SCXR, ASI_DMMU, 0);
132 /* flush probably not needed. */
133 membar(Sync);
134 }
135}
136
137static __inline void
138tlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte)
139{
140 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
141 stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data);
142 if (ctx == TLB_CTX_KERNEL)
143 flush(va);
144 else {
145 /*
146 * flush probably not needed and impossible here, no access to
147 * user page.
148 */
149 membar(Sync);
150 }
151}
152
153static __inline void
154tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
155{
156 stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
157 stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
158 flush(va);
159}
160
161static __inline void
162tlb_page_demap(u_int tlb, u_int ctx, vm_offset_t va)
163{
164 if (tlb & TLB_DTLB)
165 tlb_dtlb_page_demap(ctx, va);
166 if (tlb & TLB_ITLB)

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