| iommureg.h (200923) | iommureg.h (218909) |
|---|---|
| 1/*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * --- 19 unchanged lines hidden (view full) --- 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 35 * | 1/*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * --- 19 unchanged lines hidden (view full) --- 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 35 * |
| 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 200923 2009-12-23 22:02:34Z marius $ | 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 218909 2011-02-21 09:01:34Z brucec $ |
| 37 */ 38 39#ifndef _MACHINE_IOMMUREG_H_ 40#define _MACHINE_IOMMUREG_H_ 41 42/* 43 * UltraSPARC IOMMU registers, common to both the PCI and SBus 44 * controllers. --- 144 unchanged lines hidden (view full) --- 189 * 128MB f8000000 128K 4 190 * 256MB f0000000 256K 5 191 * 512MB e0000000 512K 6 192 * 1GB c0000000 1MB 7 193 * 194 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 195 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 196 * used to check against the Target Address Space register in the IIi and | 37 */ 38 39#ifndef _MACHINE_IOMMUREG_H_ 40#define _MACHINE_IOMMUREG_H_ 41 42/* 43 * UltraSPARC IOMMU registers, common to both the PCI and SBus 44 * controllers. --- 144 unchanged lines hidden (view full) --- 189 * 128MB f8000000 128K 4 190 * 256MB f0000000 256K 5 191 * 512MB e0000000 512K 6 192 * 1GB c0000000 1MB 7 193 * 194 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 195 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 196 * used to check against the Target Address Space register in the IIi and |
| 197 * the the IOMMU is used if they hit. God knows what goes on in the IIe. | 197 * the IOMMU is used if they hit. God knows what goes on in the IIe. |
| 198 * 199 */ 200 201#define IOTSB_BASESZ (1024 << IOTTE_SHIFT) 202#define IOTSB_VEND (~IO_PAGE_MASK) 203#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) 204 205#define MAKEIOTTE(pa, w, c, s) \ 206 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 207 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 208 (IOTTE_V | IOTTE_8K)) 209#define IOTSBSLOT(va) \ 210 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT) 211 212#endif /* !_MACHINE_IOMMUREG_H_ */ | 198 * 199 */ 200 201#define IOTSB_BASESZ (1024 << IOTTE_SHIFT) 202#define IOTSB_VEND (~IO_PAGE_MASK) 203#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) 204 205#define MAKEIOTTE(pa, w, c, s) \ 206 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 207 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 208 (IOTTE_V | IOTTE_8K)) 209#define IOTSBSLOT(va) \ 210 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT) 211 212#endif /* !_MACHINE_IOMMUREG_H_ */ |