1/*-
2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
4 *
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
35 *
|
36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 200923 2009-12-23 22:02:34Z marius $
|
| 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 218909 2011-02-21 09:01:34Z brucec $ |
37 */
38
39#ifndef _MACHINE_IOMMUREG_H_
40#define _MACHINE_IOMMUREG_H_
41
42/*
43 * UltraSPARC IOMMU registers, common to both the PCI and SBus
44 * controllers.
45 */
46
47/* IOMMU registers */
48#define IMR_CTL 0x0000 /* IOMMU control register */
49#define IMR_TSB 0x0008 /* IOMMU TSB base register */
50#define IMR_FLUSH 0x0010 /* IOMMU flush register */
51/* The TTE Cache is Fire and Oberon only. */
52#define IMR_CACHE_FLUSH 0x0100 /* IOMMU TTE cache flush address register */
53#define IMR_CACHE_INVAL 0x0108 /* IOMMU TTE cache invalidate register */
54
55/* streaming buffer registers */
56#define ISR_CTL 0x0000 /* streaming buffer control reg */
57#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */
58#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */
59
60/* streaming buffer diagnostics registers */
61#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */
62#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */
63#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */
64#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */
65
66/* streaming buffer control register */
67#define STRBUF_EN 0x0000000000000001UL
68#define STRBUF_D 0x0000000000000002UL
69#define STRBUF_RR_DIS 0x0000000000000004UL
70
71#define IOMMU_MAXADDR(bits) ((1UL << (bits)) - 1)
72
73/*
74 * control register bits
75 */
76/* Nummber of entries in the IOTSB - pre-Fire only */
77#define IOMMUCR_TSBSZ_MASK 0x0000000000070000UL
78#define IOMMUCR_TSBSZ_SHIFT 16
79/* TSB cache snoop enable */
80#define IOMMUCR_SE 0x0000000000000400UL
81/* Cache modes - Fire and Oberon */
82#define IOMMUCR_CM_NC_TLB_TBW 0x0000000000000000UL
83#define IOMMUCR_CM_LC_NTLB_NTBW 0x0000000000000100UL
84#define IOMMUCR_CM_LC_TLB_TBW 0x0000000000000200UL
85#define IOMMUCR_CM_C_TLB_TBW 0x0000000000000300UL
86/* IOMMU page size - pre-Fire only */
87#define IOMMUCR_8KPG 0x0000000000000000UL
88#define IOMMUCR_64KPG 0x0000000000000004UL
89/* Bypass enable - Fire and Oberon */
90#define IOMMUCR_BE 0x0000000000000002UL
91/* Diagnostic mode enable - pre-Fire only */
92#define IOMMUCR_DE 0x0000000000000002UL
93/* IOMMU/translation enable */
94#define IOMMUCR_EN 0x0000000000000001UL
95
96/*
97 * TSB base register bits
98 */
99 /* TSB base address */
100#define IOMMUTB_TB_MASK 0x000007ffffffe000UL
101#define IOMMUTB_TB_SHIFT 13
102/* IOMMU page size - Fire and Oberon */
103#define IOMMUTB_8KPG 0x0000000000000000UL
104#define IOMMUTB_64KPG 0x0000000000000100UL
105/* Nummber of entries in the IOTSB - Fire and Oberon */
106#define IOMMUTB_TSBSZ_MASK 0x0000000000000004UL
107#define IOMMUTB_TSBSZ_SHIFT 0
108
109/*
110 * TSB size definitions for both control and TSB base register */
111#define IOMMU_TSB1K 0
112#define IOMMU_TSB2K 1
113#define IOMMU_TSB4K 2
114#define IOMMU_TSB8K 3
115#define IOMMU_TSB16K 4
116#define IOMMU_TSB32K 5
117#define IOMMU_TSB64K 6
118#define IOMMU_TSB128K 7
119/* Fire and Oberon */
120#define IOMMU_TSB256K 8
121/* Fire and Oberon */
122#define IOMMU_TSB512K 9
123#define IOMMU_TSBENTRIES(tsbsz) \
124 ((1 << (tsbsz)) << (IO_PAGE_SHIFT - IOTTE_SHIFT))
125
126/*
127 * Diagnostic register definitions
128 */
129#define IOMMU_DTAG_VPNBITS 19
130#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1)
131#define IOMMU_DTAG_VPNSHIFT 13
132#define IOMMU_DTAG_ERRBITS 3
133#define IOMMU_DTAG_ERRSHIFT 22
134#define IOMMU_DTAG_ERRMASK \
135 (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT)
136
137#define IOMMU_DDATA_PGBITS 21
138#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1)
139#define IOMMU_DDATA_PGSHIFT 13
140#define IOMMU_DDATA_C (1 << 28)
141#define IOMMU_DDATA_V (1 << 30)
142
143/*
144 * IOMMU stuff
145 */
146/* Entry valid */
147#define IOTTE_V 0x8000000000000000UL
148/* Page size - pre-Fire only */
149#define IOTTE_64K 0x2000000000000000UL
150#define IOTTE_8K 0x0000000000000000UL
151/* Streamable page - streaming buffer equipped variants only */
152#define IOTTE_STREAM 0x1000000000000000UL
153/* Accesses to the same bus segment - SBus only */
154#define IOTTE_LOCAL 0x0800000000000000UL
155/* Physical address mask (based on Oberon) */
156#define IOTTE_PAMASK 0x00007fffffffe000UL
157/* Accesses to cacheable space - pre-Fire only */
158#define IOTTE_C 0x0000000000000010UL
159/* Writeable */
160#define IOTTE_W 0x0000000000000002UL
161
162/* log2 of the IOMMU TTE size */
163#define IOTTE_SHIFT 3
164
165/* Streaming buffer line size */
166#define STRBUF_LINESZ 64
167
168/*
169 * Number of bytes written by a stream buffer flushsync operation to indicate
170 * completion.
171 */
172#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ
173
174/*
175 * On sun4u each bus controller has a separate IOMMU. The IOMMU has
176 * a TSB which must be page aligned and physically contiguous. Mappings
177 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
178 * with the CPU's MMU.
179 *
180 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
181 * following size segments:
182 *
183 * VA size VA base TSB size tsbsize
184 * -------- -------- --------- -------
185 * 8MB ff800000 8K 0
186 * 16MB ff000000 16K 1
187 * 32MB fe000000 32K 2
188 * 64MB fc000000 64K 3
189 * 128MB f8000000 128K 4
190 * 256MB f0000000 256K 5
191 * 512MB e0000000 512K 6
192 * 1GB c0000000 1MB 7
193 *
194 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
195 * this scheme to determine the IOVA base address. Instead, bits 31-29 are
196 * used to check against the Target Address Space register in the IIi and
|
197 * the the IOMMU is used if they hit. God knows what goes on in the IIe.
|
| 197 * the IOMMU is used if they hit. God knows what goes on in the IIe. |
198 *
199 */
200
201#define IOTSB_BASESZ (1024 << IOTTE_SHIFT)
202#define IOTSB_VEND (~IO_PAGE_MASK)
203#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10))
204
205#define MAKEIOTTE(pa, w, c, s) \
206 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \
207 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \
208 (IOTTE_V | IOTTE_8K))
209#define IOTSBSLOT(va) \
210 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT)
211
212#endif /* !_MACHINE_IOMMUREG_H_ */
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