1/*-
2 * Copyright (C) 2002 Benno Rice.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 10 unchanged lines hidden (view full) ---
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/powerpc/powermac/uninorthpci.c 230993 2012-02-04 19:54:13Z nwhitehorn $");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/module.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35
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44#include <machine/bus.h>
45#include <machine/intr_machdep.h>
46#include <machine/md_var.h>
47#include <machine/pio.h>
48#include <machine/resource.h>
49
50#include <sys/rman.h>
51
52#include <powerpc/ofw/ofw_pci.h>
53#include <powerpc/powermac/uninorthvar.h>
54
55#include <vm/vm.h>
56#include <vm/pmap.h>
57
58#include "pcib_if.h"
59
60#define UNINORTH_DEBUG 0
61
62/*
63 * Device interface.
64 */
65static int uninorth_probe(device_t);
66static int uninorth_attach(device_t);
67
68/*
69 * pcib interface.
70 */
71static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
72 u_int, int);
73static void uninorth_write_config(device_t, u_int, u_int, u_int,
74 u_int, u_int32_t, int);
75
76/*
77 * Local routines.
78 */
79static int uninorth_enable_config(struct uninorth_softc *, u_int,
80 u_int, u_int, u_int);
81
82/*
83 * Driver methods.
84 */
85static device_method_t uninorth_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_probe, uninorth_probe),
88 DEVMETHOD(device_attach, uninorth_attach),
89
90 /* pcib interface */
91 DEVMETHOD(pcib_read_config, uninorth_read_config),
92 DEVMETHOD(pcib_write_config, uninorth_write_config),
93
94 DEVMETHOD_END
95};
96
97static devclass_t uninorth_devclass;
98
99DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
100 sizeof(struct uninorth_softc), ofw_pci_driver);
101DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
102
103static int
104uninorth_probe(device_t dev)
105{
106 const char *type, *compatible;
107
108 type = ofw_bus_get_type(dev);
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129}
130
131static int
132uninorth_attach(device_t dev)
133{
134 struct uninorth_softc *sc;
135 const char *compatible;
136 phandle_t node;
137 u_int32_t reg[3];
138
139 node = ofw_bus_get_node(dev);
140 sc = device_get_softc(dev);
141
142 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
143 return (ENXIO);
144
145 sc->sc_ver = 0;
146 compatible = ofw_bus_get_compat(dev);
147 if (strcmp(compatible, "u3-agp") == 0)
148 sc->sc_ver = 3;
149 if (strcmp(compatible, "u4-pcie") == 0)
150 sc->sc_ver = 4;
151
152 if (sc->sc_ver >= 3) {
153 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
154 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
155 } else {
156 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
157 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
158 }
159
160 return (ofw_pci_attach(dev));
161}
162
163static u_int32_t
164uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
165 int width)
166{
167 struct uninorth_softc *sc;
168 vm_offset_t caoff;
169
170 sc = device_get_softc(dev);
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208 case 4:
209 out32rb(caoff, val);
210 break;
211 }
212 }
213}
214
215static int
216uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
217 u_int func, u_int reg)
218{
219 uint32_t cfgval;
220 uint32_t pass;
221
222 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev),
223 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) {
224 if (pass == slot)
225 return (0);
226 }
227
228 /*
229 * Issue type 0 configuration space accesses for the root bus.
230 *
231 * NOTE: On U4, issue only type 1 accesses. There is a secret
232 * PCI Express <-> PCI Express bridge not present in the device tree,
233 * and we need to route all of our configuration space through it.
234 */
235 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
236 /*
237 * No slots less than 11 on the primary bus on U3 and lower
238 */
239 if (slot < 11)
240 return (0);
241
242 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
243 } else {
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251
252 do {
253 out32rb(sc->sc_addr, cfgval);
254 } while (in32rb(sc->sc_addr) != cfgval);
255
256 return (1);
257}
258
2 * Copyright (C) 2002 Benno Rice.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 10 unchanged lines hidden (view full) ---
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/powerpc/powermac/uninorthpci.c 230993 2012-02-04 19:54:13Z nwhitehorn $");
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/module.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35
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44#include <machine/bus.h>
45#include <machine/intr_machdep.h>
46#include <machine/md_var.h>
47#include <machine/pio.h>
48#include <machine/resource.h>
49
50#include <sys/rman.h>
51
52#include <powerpc/ofw/ofw_pci.h>
53#include <powerpc/powermac/uninorthvar.h>
54
55#include <vm/vm.h>
56#include <vm/pmap.h>
57
58#include "pcib_if.h"
59
60#define UNINORTH_DEBUG 0
61
62/*
63 * Device interface.
64 */
65static int uninorth_probe(device_t);
66static int uninorth_attach(device_t);
67
68/*
69 * pcib interface.
70 */
71static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
72 u_int, int);
73static void uninorth_write_config(device_t, u_int, u_int, u_int,
74 u_int, u_int32_t, int);
75
76/*
77 * Local routines.
78 */
79static int uninorth_enable_config(struct uninorth_softc *, u_int,
80 u_int, u_int, u_int);
81
82/*
83 * Driver methods.
84 */
85static device_method_t uninorth_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_probe, uninorth_probe),
88 DEVMETHOD(device_attach, uninorth_attach),
89
90 /* pcib interface */
91 DEVMETHOD(pcib_read_config, uninorth_read_config),
92 DEVMETHOD(pcib_write_config, uninorth_write_config),
93
94 DEVMETHOD_END
95};
96
97static devclass_t uninorth_devclass;
98
99DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
100 sizeof(struct uninorth_softc), ofw_pci_driver);
101DRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0);
102
103static int
104uninorth_probe(device_t dev)
105{
106 const char *type, *compatible;
107
108 type = ofw_bus_get_type(dev);
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129}
130
131static int
132uninorth_attach(device_t dev)
133{
134 struct uninorth_softc *sc;
135 const char *compatible;
136 phandle_t node;
137 u_int32_t reg[3];
138
139 node = ofw_bus_get_node(dev);
140 sc = device_get_softc(dev);
141
142 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
143 return (ENXIO);
144
145 sc->sc_ver = 0;
146 compatible = ofw_bus_get_compat(dev);
147 if (strcmp(compatible, "u3-agp") == 0)
148 sc->sc_ver = 3;
149 if (strcmp(compatible, "u4-pcie") == 0)
150 sc->sc_ver = 4;
151
152 if (sc->sc_ver >= 3) {
153 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[1] + 0x800000, PAGE_SIZE);
154 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1] + 0xc00000, PAGE_SIZE);
155 } else {
156 sc->sc_addr = (vm_offset_t)pmap_mapdev(reg[0] + 0x800000, PAGE_SIZE);
157 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[0] + 0xc00000, PAGE_SIZE);
158 }
159
160 return (ofw_pci_attach(dev));
161}
162
163static u_int32_t
164uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
165 int width)
166{
167 struct uninorth_softc *sc;
168 vm_offset_t caoff;
169
170 sc = device_get_softc(dev);
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208 case 4:
209 out32rb(caoff, val);
210 break;
211 }
212 }
213}
214
215static int
216uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
217 u_int func, u_int reg)
218{
219 uint32_t cfgval;
220 uint32_t pass;
221
222 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev),
223 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) {
224 if (pass == slot)
225 return (0);
226 }
227
228 /*
229 * Issue type 0 configuration space accesses for the root bus.
230 *
231 * NOTE: On U4, issue only type 1 accesses. There is a secret
232 * PCI Express <-> PCI Express bridge not present in the device tree,
233 * and we need to route all of our configuration space through it.
234 */
235 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
236 /*
237 * No slots less than 11 on the primary bus on U3 and lower
238 */
239 if (slot < 11)
240 return (0);
241
242 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
243 } else {
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251
252 do {
253 out32rb(sc->sc_addr, cfgval);
254 } while (in32rb(sc->sc_addr) != cfgval);
255
256 return (1);
257}
258