| platform_powermac.c (259082) | platform_powermac.c (259284) |
|---|---|
| 1/*- 2 * Copyright (c) 2008 Marcel Moolenaar 3 * Copyright (c) 2009 Nathan Whitehorn 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2008 Marcel Moolenaar 3 * Copyright (c) 2009 Nathan Whitehorn 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 12 unchanged lines hidden (view full) --- 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> |
| 29__FBSDID("$FreeBSD: head/sys/powerpc/powermac/platform_powermac.c 259082 2013-12-07 22:25:07Z jhibbits $"); | 29__FBSDID("$FreeBSD: head/sys/powerpc/powermac/platform_powermac.c 259284 2013-12-13 02:37:35Z jhibbits $"); |
| 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/pcpu.h> 36#include <sys/proc.h> 37#include <sys/smp.h> --- 333 unchanged lines hidden (view full) --- 371 372 return ((pc->pc_awake) ? 0 : EBUSY); 373#else 374 /* No SMP support */ 375 return (ENXIO); 376#endif 377} 378 | 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/bus.h> 35#include <sys/pcpu.h> 36#include <sys/proc.h> 37#include <sys/smp.h> --- 333 unchanged lines hidden (view full) --- 371 372 return ((pc->pc_awake) ? 0 : EBUSY); 373#else 374 /* No SMP support */ 375 return (ENXIO); 376#endif 377} 378 |
| 379/* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */ 380void 381flush_disable_caches(void) 382{ 383 register_t msr; 384 register_t msscr0; 385 register_t cache_reg; 386 volatile uint32_t *memp; 387 uint32_t temp; 388 int i; 389 int x; 390 391 msr = mfmsr(); 392 powerpc_sync(); 393 mtmsr(msr & ~(PSL_EE | PSL_DR)); 394 msscr0 = mfspr(SPR_MSSCR0); 395 msscr0 &= ~MSSCR0_L2PFE; 396 mtspr(SPR_MSSCR0, msscr0); 397 powerpc_sync(); 398 isync(); 399 __asm__ __volatile__("dssall; sync"); 400 powerpc_sync(); 401 isync(); 402 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 403 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 404 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 405 406 /* Lock the L1 Data cache. */ 407 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); 408 powerpc_sync(); 409 isync(); 410 411 mtspr(SPR_LDSTCR, 0); 412 413 /* 414 * Perform this in two stages: Flush the cache starting in RAM, then do it 415 * from ROM. 416 */ 417 memp = (volatile uint32_t *)0x00000000; 418 for (i = 0; i < 128 * 1024; i++) { 419 temp = *memp; 420 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 421 memp += 32/sizeof(*memp); 422 } 423 424 memp = (volatile uint32_t *)0xfff00000; 425 x = 0xfe; 426 427 for (; x != 0xff;) { 428 mtspr(SPR_LDSTCR, x); 429 for (i = 0; i < 128; i++) { 430 temp = *memp; 431 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 432 memp += 32/sizeof(*memp); 433 } 434 x = ((x << 1) | 1) & 0xff; 435 } 436 mtspr(SPR_LDSTCR, 0); 437 438 cache_reg = mfspr(SPR_L2CR); 439 if (cache_reg & L2CR_L2E) { 440 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450); 441 mtspr(SPR_L2CR, cache_reg); 442 powerpc_sync(); 443 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); 444 while (mfspr(SPR_L2CR) & L2CR_L2HWF) 445 ; /* Busy wait for cache to flush */ 446 powerpc_sync(); 447 cache_reg &= ~L2CR_L2E; 448 mtspr(SPR_L2CR, cache_reg); 449 powerpc_sync(); 450 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); 451 powerpc_sync(); 452 while (mfspr(SPR_L2CR) & L2CR_L2I) 453 ; /* Busy wait for L2 cache invalidate */ 454 powerpc_sync(); 455 } 456 457 cache_reg = mfspr(SPR_L3CR); 458 if (cache_reg & L3CR_L3E) { 459 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO); 460 mtspr(SPR_L3CR, cache_reg); 461 powerpc_sync(); 462 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF); 463 while (mfspr(SPR_L3CR) & L3CR_L3HWF) 464 ; /* Busy wait for cache to flush */ 465 powerpc_sync(); 466 cache_reg &= ~L3CR_L3E; 467 mtspr(SPR_L3CR, cache_reg); 468 powerpc_sync(); 469 mtspr(SPR_L3CR, cache_reg | L3CR_L3I); 470 powerpc_sync(); 471 while (mfspr(SPR_L3CR) & L3CR_L3I) 472 ; /* Busy wait for L3 cache invalidate */ 473 powerpc_sync(); 474 } 475 476 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); 477 powerpc_sync(); 478 isync(); 479 480 mtmsr(msr); 481} 482 |
|
| 379static void 380powermac_reset(platform_t platform) 381{ 382 OF_reboot(); 383} 384 | 483static void 484powermac_reset(platform_t platform) 485{ 486 OF_reboot(); 487} 488 |