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platform_mpc85xx.c (287011) platform_mpc85xx.c (292903)
1/*-
2 * Copyright (c) 2008-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
1/*-
2 * Copyright (c) 2008-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include "opt_platform.h"
27#include <sys/cdefs.h>
28#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/platform_mpc85xx.c 287011 2015-08-22 03:29:12Z jhibbits $");
29__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/platform_mpc85xx.c 292903 2015-12-30 03:43:25Z jhibbits $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <sys/pcpu.h>
35#include <sys/proc.h>
36#include <sys/smp.h>
37
38#include <machine/bus.h>
39#include <machine/cpu.h>
40#include <machine/hid.h>
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/bus.h>
35#include <sys/pcpu.h>
36#include <sys/proc.h>
37#include <sys/smp.h>
38
39#include <machine/bus.h>
40#include <machine/cpu.h>
41#include <machine/hid.h>
42#include <machine/machdep.h>
41#include <machine/platform.h>
42#include <machine/platformvar.h>
43#include <machine/smp.h>
44#include <machine/spr.h>
45#include <machine/vmparam.h>
46
47#include <dev/fdt/fdt_common.h>
48#include <dev/ofw/ofw_bus.h>

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170 ccsrbar |= ranges[i];
171 }
172 for (i = acells + pacells; i < acells + pacells + scells; i++) {
173 ccsrsize <<= 32;
174 ccsrsize |= ranges[i];
175 }
176 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
177
43#include <machine/platform.h>
44#include <machine/platformvar.h>
45#include <machine/smp.h>
46#include <machine/spr.h>
47#include <machine/vmparam.h>
48
49#include <dev/fdt/fdt_common.h>
50#include <dev/ofw/ofw_bus.h>

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172 ccsrbar |= ranges[i];
173 }
174 for (i = acells + pacells; i < acells + pacells + scells; i++) {
175 ccsrsize <<= 32;
176 ccsrsize |= ranges[i];
177 }
178 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
179
180 mpc85xx_fix_errata(ccsrbar_va);
181 mpc85xx_enable_l3_cache();
182
178 /*
179 * Clear local access windows. Skip DRAM entries, so we don't shoot
180 * ourselves in the foot.
181 */
182 law_max = law_getmax();
183 for (i = 0; i < law_max; i++) {
184 sr = ccsr_read4(OCP85XX_LAWSR(i));
183 /*
184 * Clear local access windows. Skip DRAM entries, so we don't shoot
185 * ourselves in the foot.
186 */
187 law_max = law_getmax();
188 for (i = 0; i < law_max; i++) {
189 sr = ccsr_read4(OCP85XX_LAWSR(i));
185 if ((sr & 0x80000000) == 0)
190 if ((sr & OCP85XX_ENA_MASK) == 0)
186 continue;
187 tgt = (sr & 0x01f00000) >> 20;
188 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
189 tgt == OCP85XX_TGTIF_RAM_INTL)
190 continue;
191
191 continue;
192 tgt = (sr & 0x01f00000) >> 20;
193 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
194 tgt == OCP85XX_TGTIF_RAM_INTL)
195 continue;
196
192 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
197 ccsr_write4(OCP85XX_LAWSR(i), sr & OCP85XX_DIS_MASK);
193 }
194
195 return (0);
196}
197
198void
199mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
200 struct mem_region *avail, int *availsz)

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251 sizeof(freq)) <= 0)
252 goto out;
253
254 /*
255 * Time Base and Decrementer are updated every 8 CCB bus clocks.
256 * HID0[SEL_TBCLK] = 0
257 */
258 if (freq != 0)
198 }
199
200 return (0);
201}
202
203void
204mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
205 struct mem_region *avail, int *availsz)

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256 sizeof(freq)) <= 0)
257 goto out;
258
259 /*
260 * Time Base and Decrementer are updated every 8 CCB bus clocks.
261 * HID0[SEL_TBCLK] = 0
262 */
263 if (freq != 0)
264#ifdef QORIQ_DPAA
265 ticks = freq / 32;
266#else
259 ticks = freq / 8;
267 ticks = freq / 8;
268#endif
260
261out:
262 if (ticks <= 0)
263 panic("Unable to determine timebase frequency!");
264
265 return (ticks);
266}
267

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304 return (0);
305}
306
307static int
308mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
309{
310#ifdef SMP
311 uint32_t *tlb1;
269
270out:
271 if (ticks <= 0)
272 panic("Unable to determine timebase frequency!");
273
274 return (ticks);
275}
276

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313 return (0);
314}
315
316static int
317mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
318{
319#ifdef SMP
320 uint32_t *tlb1;
312 uint32_t bptr, eebpcr;
321 vm_paddr_t bptr;
322 uint32_t reg;
313 int i, timeout;
323 int i, timeout;
324 uintptr_t brr;
325 int cpuid;
314
326
315 eebpcr = ccsr_read4(OCP85XX_EEBPCR);
316 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
327#ifdef QORIQ_DPAA
328 uint32_t tgt;
329
330 reg = ccsr_read4(OCP85XX_COREDISR);
331 cpuid = pc->pc_cpuid;
332
333 if ((reg & cpuid) != 0) {
334 printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
335 return (-1);
336 }
337
338 brr = OCP85XX_BRR;
339#else /* QORIQ_DPAA */
340 brr = OCP85XX_EEBPCR;
341 cpuid = pc->pc_cpuid + 24;
342#endif
343 reg = ccsr_read4(brr);
344 if ((reg & (1 << cpuid)) != 0) {
317 printf("SMP: CPU %d already out of hold-off state!\n",
318 pc->pc_cpuid);
319 return (ENXIO);
320 }
321
322 ap_pcpu = pc;
345 printf("SMP: CPU %d already out of hold-off state!\n",
346 pc->pc_cpuid);
347 return (ENXIO);
348 }
349
350 ap_pcpu = pc;
351 __asm __volatile("msync; isync");
323
324 i = 0;
325 tlb1 = bp_tlb1;
326 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
327 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
328 __asm __volatile("isync; tlbre");
329 tlb1[0] = mfspr(SPR_MAS1);
330 tlb1[1] = mfspr(SPR_MAS2);
331 tlb1[2] = mfspr(SPR_MAS3);
332 i++;
333 tlb1 += 3;
334 }
335 if (i < bp_ntlb1s)
336 bp_ntlb1s = i;
337
352
353 i = 0;
354 tlb1 = bp_tlb1;
355 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
356 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
357 __asm __volatile("isync; tlbre");
358 tlb1[0] = mfspr(SPR_MAS1);
359 tlb1[1] = mfspr(SPR_MAS2);
360 tlb1[2] = mfspr(SPR_MAS3);
361 i++;
362 tlb1 += 3;
363 }
364 if (i < bp_ntlb1s)
365 bp_ntlb1s = i;
366
367 /* Flush caches to have our changes hit DRAM. */
368 cpu_flush_dcache(__boot_page, 4096);
369
370 bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
371 KASSERT((bptr & 0xfff) == 0,
372 ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
373#ifdef QORIQ_DPAA
374
338 /*
375 /*
376 * Read DDR controller configuration to select proper BPTR target ID.
377 *
378 * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
379 * interleaving. If this bit is set, we have to use
380 * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
381 * this bit is reserved and always 0.
382 */
383
384 reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
385 if (reg & (1 << 29))
386 tgt = OCP85XX_TGTIF_RAM_INTL;
387 else
388 tgt = OCP85XX_TGTIF_RAM1;
389
390 /*
391 * Set BSTR to the physical address of the boot page
392 */
393 ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
394 ccsr_write4(OCP85XX_BSTRL, bptr);
395 ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
396 (tgt << OCP85XX_TRGT_SHIFT) | (ffsl(PAGE_SIZE) - 2));
397
398 /* Read back OCP85XX_BSTAR to synchronize write */
399 ccsr_read4(OCP85XX_BSTAR);
400
401 /*
402 * Enable and configure time base on new CPU.
403 */
404
405 /* Set TB clock source to platform clock / 32 */
406 reg = ccsr_read4(CCSR_CTBCKSELR);
407 ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
408
409 /* Enable TB */
410 reg = ccsr_read4(CCSR_CTBENR);
411 ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
412#else
413
414 /*
339 * Set BPTR to the physical address of the boot page
340 */
415 * Set BPTR to the physical address of the boot page
416 */
341 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
342 KASSERT((bptr & 0xfff) == 0,
343 ("%s: boot page is not aligned (%#x)", __func__, bptr));
344 bptr = (bptr >> 12) | 0x80000000u;
345 ccsr_write4(OCP85XX_BPTR, bptr);
346 __asm __volatile("isync; msync");
347
417 bptr = (bptr >> 12) | 0x80000000u;
418 ccsr_write4(OCP85XX_BPTR, bptr);
419 __asm __volatile("isync; msync");
420
348 /* Flush caches to have our changes hit DRAM. */
349 cpu_flush_dcache(__boot_page, 4096);
421#endif /* QORIQ_DPAA */
350
351 /*
352 * Release AP from hold-off state
353 */
422
423 /*
424 * Release AP from hold-off state
425 */
354 eebpcr |= (1 << (pc->pc_cpuid + 24));
355 ccsr_write4(OCP85XX_EEBPCR, eebpcr);
426 reg = ccsr_read4(brr);
427 ccsr_write4(brr, reg | (1 << cpuid));
356 __asm __volatile("isync; msync");
357
358 timeout = 500;
359 while (!pc->pc_awake && timeout--)
360 DELAY(1000); /* wait 1ms */
361
362 /*
363 * Disable boot page translation so that the 4K page at the default
364 * address (= 0xfffff000) isn't permanently remapped and thus not
365 * usable otherwise.
366 */
428 __asm __volatile("isync; msync");
429
430 timeout = 500;
431 while (!pc->pc_awake && timeout--)
432 DELAY(1000); /* wait 1ms */
433
434 /*
435 * Disable boot page translation so that the 4K page at the default
436 * address (= 0xfffff000) isn't permanently remapped and thus not
437 * usable otherwise.
438 */
439#ifdef QORIQ_DPAA
440 ccsr_write4(OCP85XX_BSTAR, 0);
441#else
367 ccsr_write4(OCP85XX_BPTR, 0);
442 ccsr_write4(OCP85XX_BPTR, 0);
443#endif
368 __asm __volatile("isync; msync");
369
370 if (!pc->pc_awake)
371 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
372 return ((pc->pc_awake) ? 0 : EBUSY);
373#else
374 /* No SMP support */
375 return (ENXIO);

--- 29 unchanged lines hidden --- 		444 __asm __volatile("isync; msync");
445
446 if (!pc->pc_awake)
447 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
448 return ((pc->pc_awake) ? 0 : EBUSY);
449#else
450 /* No SMP support */
451 return (ENXIO);

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