26a27
> #include "opt_platform.h"
28c29
< __FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/platform_mpc85xx.c 287011 2015-08-22 03:29:12Z jhibbits $");
---
> __FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/platform_mpc85xx.c 292903 2015-12-30 03:43:25Z jhibbits $");
40a42
> #include <machine/machdep.h>
177a180,182
> mpc85xx_fix_errata(ccsrbar_va);
> mpc85xx_enable_l3_cache();
>
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< if ((sr & 0x80000000) == 0)
---
> if ((sr & OCP85XX_ENA_MASK) == 0)
192c197
< ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
---
> ccsr_write4(OCP85XX_LAWSR(i), sr & OCP85XX_DIS_MASK);
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> #ifdef QORIQ_DPAA
> ticks = freq / 32;
> #else
259a268
> #endif
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< uint32_t bptr, eebpcr;
---
> vm_paddr_t bptr;
> uint32_t reg;
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> uintptr_t brr;
> int cpuid;
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< eebpcr = ccsr_read4(OCP85XX_EEBPCR);
< if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
---
> #ifdef QORIQ_DPAA
> uint32_t tgt;
>
> reg = ccsr_read4(OCP85XX_COREDISR);
> cpuid = pc->pc_cpuid;
>
> if ((reg & cpuid) != 0) {
> printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
> return (-1);
> }
>
> brr = OCP85XX_BRR;
> #else /* QORIQ_DPAA */
> brr = OCP85XX_EEBPCR;
> cpuid = pc->pc_cpuid + 24;
> #endif
> reg = ccsr_read4(brr);
> if ((reg & (1 << cpuid)) != 0) {
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> __asm __volatile("msync; isync");
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> /* Flush caches to have our changes hit DRAM. */
> cpu_flush_dcache(__boot_page, 4096);
>
> bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
> KASSERT((bptr & 0xfff) == 0,
> ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
> #ifdef QORIQ_DPAA
>
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> * Read DDR controller configuration to select proper BPTR target ID.
> *
> * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
> * interleaving. If this bit is set, we have to use
> * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
> * this bit is reserved and always 0.
> */
>
> reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
> if (reg & (1 << 29))
> tgt = OCP85XX_TGTIF_RAM_INTL;
> else
> tgt = OCP85XX_TGTIF_RAM1;
>
> /*
> * Set BSTR to the physical address of the boot page
> */
> ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
> ccsr_write4(OCP85XX_BSTRL, bptr);
> ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
> (tgt << OCP85XX_TRGT_SHIFT) | (ffsl(PAGE_SIZE) - 2));
>
> /* Read back OCP85XX_BSTAR to synchronize write */
> ccsr_read4(OCP85XX_BSTAR);
>
> /*
> * Enable and configure time base on new CPU.
> */
>
> /* Set TB clock source to platform clock / 32 */
> reg = ccsr_read4(CCSR_CTBCKSELR);
> ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
>
> /* Enable TB */
> reg = ccsr_read4(CCSR_CTBENR);
> ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
> #else
>
> /*
341,343d416
< bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
< KASSERT((bptr & 0xfff) == 0,
< ("%s: boot page is not aligned (%#x)", __func__, bptr));
348,349c421
< /* Flush caches to have our changes hit DRAM. */
< cpu_flush_dcache(__boot_page, 4096);
---
> #endif /* QORIQ_DPAA */
354,355c426,427
< eebpcr |= (1 << (pc->pc_cpuid + 24));
< ccsr_write4(OCP85XX_EEBPCR, eebpcr);
---
> reg = ccsr_read4(brr);
> ccsr_write4(brr, reg | (1 << cpuid));
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> #ifdef QORIQ_DPAA
> ccsr_write4(OCP85XX_BSTAR, 0);
> #else
367a443
> #endif