1/*-
2 * Copyright (c) 2008-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
| 1/*-
2 * Copyright (c) 2008-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
|
| 27#include "opt_platform.h"
|
27#include <sys/cdefs.h>
| 28#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/platform_mpc85xx.c 287011 2015-08-22 03:29:12Z jhibbits $");
| 29__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/platform_mpc85xx.c 292903 2015-12-30 03:43:25Z jhibbits $");
|
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <sys/pcpu.h>
35#include <sys/proc.h>
36#include <sys/smp.h>
37
38#include <machine/bus.h>
39#include <machine/cpu.h>
40#include <machine/hid.h>
| 30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/kernel.h>
34#include <sys/bus.h>
35#include <sys/pcpu.h>
36#include <sys/proc.h>
37#include <sys/smp.h>
38
39#include <machine/bus.h>
40#include <machine/cpu.h>
41#include <machine/hid.h>
|
| 42#include <machine/machdep.h>
|
41#include <machine/platform.h>
42#include <machine/platformvar.h>
43#include <machine/smp.h>
44#include <machine/spr.h>
45#include <machine/vmparam.h>
46
47#include <dev/fdt/fdt_common.h>
48#include <dev/ofw/ofw_bus.h>
49#include <dev/ofw/ofw_bus_subr.h>
50#include <dev/ofw/openfirm.h>
51
52#include <vm/vm.h>
53#include <vm/pmap.h>
54
55#include <powerpc/mpc85xx/mpc85xx.h>
56
57#include "platform_if.h"
58
59#ifdef SMP
60extern void *ap_pcpu;
61extern vm_paddr_t kernload; /* Kernel physical load address */
62extern uint8_t __boot_page[]; /* Boot page body */
63extern uint32_t bp_ntlb1s;
64extern uint32_t bp_tlb1[];
65extern uint32_t bp_tlb1_end[];
66#endif
67
68extern uint32_t *bootinfo;
69vm_offset_t ccsrbar_va;
70
71static int cpu, maxcpu;
72
73static int mpc85xx_probe(platform_t);
74static void mpc85xx_mem_regions(platform_t, struct mem_region *phys,
75 int *physsz, struct mem_region *avail, int *availsz);
76static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
77static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
78static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
79static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
80static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
81
82static void mpc85xx_reset(platform_t);
83
84static platform_method_t mpc85xx_methods[] = {
85 PLATFORMMETHOD(platform_probe, mpc85xx_probe),
86 PLATFORMMETHOD(platform_attach, mpc85xx_attach),
87 PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions),
88 PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq),
89
90 PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu),
91 PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu),
92 PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp),
93 PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu),
94
95 PLATFORMMETHOD(platform_reset, mpc85xx_reset),
96
97 PLATFORMMETHOD_END
98};
99
100DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0);
101
102PLATFORM_DEF(mpc85xx_platform);
103
104static int
105mpc85xx_probe(platform_t plat)
106{
107 u_int pvr = mfpvr() >> 16;
108
109 if ((pvr & 0xfff0) == FSL_E500v1)
110 return (BUS_PROBE_DEFAULT);
111
112 return (ENXIO);
113}
114
115int
116mpc85xx_attach(platform_t plat)
117{
118 phandle_t cpus, child, ccsr;
119 const char *soc_name_guesses[] = {"/soc", "soc", NULL};
120 const char **name;
121 pcell_t ranges[6], acells, pacells, scells;
122 uint32_t sr;
123 uint64_t ccsrbar, ccsrsize;
124 int i, law_max, tgt;
125
126 if ((cpus = OF_finddevice("/cpus")) != -1) {
127 for (maxcpu = 0, child = OF_child(cpus); child != 0;
128 child = OF_peer(child), maxcpu++)
129 ;
130 } else
131 maxcpu = 1;
132
133 /*
134 * Locate CCSR region. Irritatingly, there is no way to find it
135 * unless you already know where it is. Try to infer its location
136 * from the device tree.
137 */
138
139 ccsr = -1;
140 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
141 ccsr = OF_finddevice(*name);
142 if (ccsr == -1) {
143 char type[64];
144
145 /* That didn't work. Search for devices of type "soc" */
146 child = OF_child(OF_peer(0));
147 for (OF_child(child); child != 0; child = OF_peer(child)) {
148 if (OF_getprop(child, "device_type", type, sizeof(type))
149 <= 0)
150 continue;
151
152 if (strcmp(type, "soc") == 0) {
153 ccsr = child;
154 break;
155 }
156 }
157 }
158
159 if (ccsr == -1)
160 panic("Could not locate CCSR window!");
161
162 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
163 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
164 OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
165 sizeof(pacells));
166 OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
167 ccsrbar = ccsrsize = 0;
168 for (i = acells; i < acells + pacells; i++) {
169 ccsrbar <<= 32;
170 ccsrbar |= ranges[i];
171 }
172 for (i = acells + pacells; i < acells + pacells + scells; i++) {
173 ccsrsize <<= 32;
174 ccsrsize |= ranges[i];
175 }
176 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
177
| 43#include <machine/platform.h>
44#include <machine/platformvar.h>
45#include <machine/smp.h>
46#include <machine/spr.h>
47#include <machine/vmparam.h>
48
49#include <dev/fdt/fdt_common.h>
50#include <dev/ofw/ofw_bus.h>
51#include <dev/ofw/ofw_bus_subr.h>
52#include <dev/ofw/openfirm.h>
53
54#include <vm/vm.h>
55#include <vm/pmap.h>
56
57#include <powerpc/mpc85xx/mpc85xx.h>
58
59#include "platform_if.h"
60
61#ifdef SMP
62extern void *ap_pcpu;
63extern vm_paddr_t kernload; /* Kernel physical load address */
64extern uint8_t __boot_page[]; /* Boot page body */
65extern uint32_t bp_ntlb1s;
66extern uint32_t bp_tlb1[];
67extern uint32_t bp_tlb1_end[];
68#endif
69
70extern uint32_t *bootinfo;
71vm_offset_t ccsrbar_va;
72
73static int cpu, maxcpu;
74
75static int mpc85xx_probe(platform_t);
76static void mpc85xx_mem_regions(platform_t, struct mem_region *phys,
77 int *physsz, struct mem_region *avail, int *availsz);
78static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref);
79static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref);
80static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref);
81static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref);
82static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu);
83
84static void mpc85xx_reset(platform_t);
85
86static platform_method_t mpc85xx_methods[] = {
87 PLATFORMMETHOD(platform_probe, mpc85xx_probe),
88 PLATFORMMETHOD(platform_attach, mpc85xx_attach),
89 PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions),
90 PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq),
91
92 PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu),
93 PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu),
94 PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp),
95 PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu),
96
97 PLATFORMMETHOD(platform_reset, mpc85xx_reset),
98
99 PLATFORMMETHOD_END
100};
101
102DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0);
103
104PLATFORM_DEF(mpc85xx_platform);
105
106static int
107mpc85xx_probe(platform_t plat)
108{
109 u_int pvr = mfpvr() >> 16;
110
111 if ((pvr & 0xfff0) == FSL_E500v1)
112 return (BUS_PROBE_DEFAULT);
113
114 return (ENXIO);
115}
116
117int
118mpc85xx_attach(platform_t plat)
119{
120 phandle_t cpus, child, ccsr;
121 const char *soc_name_guesses[] = {"/soc", "soc", NULL};
122 const char **name;
123 pcell_t ranges[6], acells, pacells, scells;
124 uint32_t sr;
125 uint64_t ccsrbar, ccsrsize;
126 int i, law_max, tgt;
127
128 if ((cpus = OF_finddevice("/cpus")) != -1) {
129 for (maxcpu = 0, child = OF_child(cpus); child != 0;
130 child = OF_peer(child), maxcpu++)
131 ;
132 } else
133 maxcpu = 1;
134
135 /*
136 * Locate CCSR region. Irritatingly, there is no way to find it
137 * unless you already know where it is. Try to infer its location
138 * from the device tree.
139 */
140
141 ccsr = -1;
142 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++)
143 ccsr = OF_finddevice(*name);
144 if (ccsr == -1) {
145 char type[64];
146
147 /* That didn't work. Search for devices of type "soc" */
148 child = OF_child(OF_peer(0));
149 for (OF_child(child); child != 0; child = OF_peer(child)) {
150 if (OF_getprop(child, "device_type", type, sizeof(type))
151 <= 0)
152 continue;
153
154 if (strcmp(type, "soc") == 0) {
155 ccsr = child;
156 break;
157 }
158 }
159 }
160
161 if (ccsr == -1)
162 panic("Could not locate CCSR window!");
163
164 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells));
165 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells));
166 OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells,
167 sizeof(pacells));
168 OF_getprop(ccsr, "ranges", ranges, sizeof(ranges));
169 ccsrbar = ccsrsize = 0;
170 for (i = acells; i < acells + pacells; i++) {
171 ccsrbar <<= 32;
172 ccsrbar |= ranges[i];
173 }
174 for (i = acells + pacells; i < acells + pacells + scells; i++) {
175 ccsrsize <<= 32;
176 ccsrsize |= ranges[i];
177 }
178 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
179
|
| 180 mpc85xx_fix_errata(ccsrbar_va);
181 mpc85xx_enable_l3_cache();
182
|
178 /*
179 * Clear local access windows. Skip DRAM entries, so we don't shoot
180 * ourselves in the foot.
181 */
182 law_max = law_getmax();
183 for (i = 0; i < law_max; i++) {
184 sr = ccsr_read4(OCP85XX_LAWSR(i));
| 183 /*
184 * Clear local access windows. Skip DRAM entries, so we don't shoot
185 * ourselves in the foot.
186 */
187 law_max = law_getmax();
188 for (i = 0; i < law_max; i++) {
189 sr = ccsr_read4(OCP85XX_LAWSR(i));
|
185 if ((sr & 0x80000000) == 0)
| 190 if ((sr & OCP85XX_ENA_MASK) == 0)
|
186 continue;
187 tgt = (sr & 0x01f00000) >> 20;
188 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
189 tgt == OCP85XX_TGTIF_RAM_INTL)
190 continue;
191
| 191 continue;
192 tgt = (sr & 0x01f00000) >> 20;
193 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
194 tgt == OCP85XX_TGTIF_RAM_INTL)
195 continue;
196
|
192 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
| 197 ccsr_write4(OCP85XX_LAWSR(i), sr & OCP85XX_DIS_MASK);
|
193 }
194
195 return (0);
196}
197
198void
199mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
200 struct mem_region *avail, int *availsz)
201{
202
203 ofw_mem_regions(phys, physsz, avail, availsz);
204}
205
206static u_long
207mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
208{
209 u_long ticks;
210 phandle_t cpus, child;
211 pcell_t freq;
212
213 if (bootinfo != NULL) {
214 if (bootinfo[0] == 1) {
215 /* Backward compatibility. See 8-STABLE. */
216 ticks = bootinfo[3] >> 3;
217 } else {
218 /* Compatibility with Juniper's loader. */
219 ticks = bootinfo[5] >> 3;
220 }
221 } else
222 ticks = 0;
223
224 if ((cpus = OF_finddevice("/cpus")) == -1)
225 goto out;
226
227 if ((child = OF_child(cpus)) == 0)
228 goto out;
229
230 switch (OF_getproplen(child, "timebase-frequency")) {
231 case 4:
232 {
233 uint32_t tbase;
234 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
235 ticks = tbase;
236 return (ticks);
237 }
238 case 8:
239 {
240 uint64_t tbase;
241 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
242 ticks = tbase;
243 return (ticks);
244 }
245 default:
246 break;
247 }
248
249 freq = 0;
250 if (OF_getprop(child, "bus-frequency", (void *)&freq,
251 sizeof(freq)) <= 0)
252 goto out;
253
254 /*
255 * Time Base and Decrementer are updated every 8 CCB bus clocks.
256 * HID0[SEL_TBCLK] = 0
257 */
258 if (freq != 0)
| 198 }
199
200 return (0);
201}
202
203void
204mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
205 struct mem_region *avail, int *availsz)
206{
207
208 ofw_mem_regions(phys, physsz, avail, availsz);
209}
210
211static u_long
212mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref)
213{
214 u_long ticks;
215 phandle_t cpus, child;
216 pcell_t freq;
217
218 if (bootinfo != NULL) {
219 if (bootinfo[0] == 1) {
220 /* Backward compatibility. See 8-STABLE. */
221 ticks = bootinfo[3] >> 3;
222 } else {
223 /* Compatibility with Juniper's loader. */
224 ticks = bootinfo[5] >> 3;
225 }
226 } else
227 ticks = 0;
228
229 if ((cpus = OF_finddevice("/cpus")) == -1)
230 goto out;
231
232 if ((child = OF_child(cpus)) == 0)
233 goto out;
234
235 switch (OF_getproplen(child, "timebase-frequency")) {
236 case 4:
237 {
238 uint32_t tbase;
239 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
240 ticks = tbase;
241 return (ticks);
242 }
243 case 8:
244 {
245 uint64_t tbase;
246 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase));
247 ticks = tbase;
248 return (ticks);
249 }
250 default:
251 break;
252 }
253
254 freq = 0;
255 if (OF_getprop(child, "bus-frequency", (void *)&freq,
256 sizeof(freq)) <= 0)
257 goto out;
258
259 /*
260 * Time Base and Decrementer are updated every 8 CCB bus clocks.
261 * HID0[SEL_TBCLK] = 0
262 */
263 if (freq != 0)
|
| 264#ifdef QORIQ_DPAA
265 ticks = freq / 32;
266#else
|
259 ticks = freq / 8;
| 267 ticks = freq / 8;
|
| 268#endif
|
260
261out:
262 if (ticks <= 0)
263 panic("Unable to determine timebase frequency!");
264
265 return (ticks);
266}
267
268static int
269mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
270{
271
272 cpu = 0;
273 cpuref->cr_cpuid = cpu;
274 cpuref->cr_hwref = cpuref->cr_cpuid;
275 if (bootverbose)
276 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
277 cpu++;
278
279 return (0);
280}
281
282static int
283mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
284{
285
286 if (cpu >= maxcpu)
287 return (ENOENT);
288
289 cpuref->cr_cpuid = cpu++;
290 cpuref->cr_hwref = cpuref->cr_cpuid;
291 if (bootverbose)
292 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
293
294 return (0);
295}
296
297static int
298mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
299{
300
301 cpuref->cr_cpuid = mfspr(SPR_PIR);
302 cpuref->cr_hwref = cpuref->cr_cpuid;
303
304 return (0);
305}
306
307static int
308mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
309{
310#ifdef SMP
311 uint32_t *tlb1;
| 269
270out:
271 if (ticks <= 0)
272 panic("Unable to determine timebase frequency!");
273
274 return (ticks);
275}
276
277static int
278mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
279{
280
281 cpu = 0;
282 cpuref->cr_cpuid = cpu;
283 cpuref->cr_hwref = cpuref->cr_cpuid;
284 if (bootverbose)
285 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
286 cpu++;
287
288 return (0);
289}
290
291static int
292mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
293{
294
295 if (cpu >= maxcpu)
296 return (ENOENT);
297
298 cpuref->cr_cpuid = cpu++;
299 cpuref->cr_hwref = cpuref->cr_cpuid;
300 if (bootverbose)
301 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
302
303 return (0);
304}
305
306static int
307mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
308{
309
310 cpuref->cr_cpuid = mfspr(SPR_PIR);
311 cpuref->cr_hwref = cpuref->cr_cpuid;
312
313 return (0);
314}
315
316static int
317mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
318{
319#ifdef SMP
320 uint32_t *tlb1;
|
312 uint32_t bptr, eebpcr;
| 321 vm_paddr_t bptr;
322 uint32_t reg;
|
313 int i, timeout;
| 323 int i, timeout;
|
| 324 uintptr_t brr;
325 int cpuid;
|
314
| 326
|
315 eebpcr = ccsr_read4(OCP85XX_EEBPCR);
316 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
| 327#ifdef QORIQ_DPAA
328 uint32_t tgt;
329
330 reg = ccsr_read4(OCP85XX_COREDISR);
331 cpuid = pc->pc_cpuid;
332
333 if ((reg & cpuid) != 0) {
334 printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
335 return (-1);
336 }
337
338 brr = OCP85XX_BRR;
339#else /* QORIQ_DPAA */
340 brr = OCP85XX_EEBPCR;
341 cpuid = pc->pc_cpuid + 24;
342#endif
343 reg = ccsr_read4(brr);
344 if ((reg & (1 << cpuid)) != 0) {
|
317 printf("SMP: CPU %d already out of hold-off state!\n",
318 pc->pc_cpuid);
319 return (ENXIO);
320 }
321
322 ap_pcpu = pc;
| 345 printf("SMP: CPU %d already out of hold-off state!\n",
346 pc->pc_cpuid);
347 return (ENXIO);
348 }
349
350 ap_pcpu = pc;
|
| 351 __asm __volatile("msync; isync");
|
323
324 i = 0;
325 tlb1 = bp_tlb1;
326 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
327 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
328 __asm __volatile("isync; tlbre");
329 tlb1[0] = mfspr(SPR_MAS1);
330 tlb1[1] = mfspr(SPR_MAS2);
331 tlb1[2] = mfspr(SPR_MAS3);
332 i++;
333 tlb1 += 3;
334 }
335 if (i < bp_ntlb1s)
336 bp_ntlb1s = i;
337
| 352
353 i = 0;
354 tlb1 = bp_tlb1;
355 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
356 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
357 __asm __volatile("isync; tlbre");
358 tlb1[0] = mfspr(SPR_MAS1);
359 tlb1[1] = mfspr(SPR_MAS2);
360 tlb1[2] = mfspr(SPR_MAS3);
361 i++;
362 tlb1 += 3;
363 }
364 if (i < bp_ntlb1s)
365 bp_ntlb1s = i;
366
|
| 367 /* Flush caches to have our changes hit DRAM. */
368 cpu_flush_dcache(__boot_page, 4096);
369
370 bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
371 KASSERT((bptr & 0xfff) == 0,
372 ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
373#ifdef QORIQ_DPAA
374
|
338 /*
| 375 /*
|
| 376 * Read DDR controller configuration to select proper BPTR target ID.
377 *
378 * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
379 * interleaving. If this bit is set, we have to use
380 * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
381 * this bit is reserved and always 0.
382 */
383
384 reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
385 if (reg & (1 << 29))
386 tgt = OCP85XX_TGTIF_RAM_INTL;
387 else
388 tgt = OCP85XX_TGTIF_RAM1;
389
390 /*
391 * Set BSTR to the physical address of the boot page
392 */
393 ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
394 ccsr_write4(OCP85XX_BSTRL, bptr);
395 ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
396 (tgt << OCP85XX_TRGT_SHIFT) | (ffsl(PAGE_SIZE) - 2));
397
398 /* Read back OCP85XX_BSTAR to synchronize write */
399 ccsr_read4(OCP85XX_BSTAR);
400
401 /*
402 * Enable and configure time base on new CPU.
403 */
404
405 /* Set TB clock source to platform clock / 32 */
406 reg = ccsr_read4(CCSR_CTBCKSELR);
407 ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
408
409 /* Enable TB */
410 reg = ccsr_read4(CCSR_CTBENR);
411 ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
412#else
413
414 /*
|
339 * Set BPTR to the physical address of the boot page
340 */
| 415 * Set BPTR to the physical address of the boot page
416 */
|
341 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
342 KASSERT((bptr & 0xfff) == 0,
343 ("%s: boot page is not aligned (%#x)", __func__, bptr));
| |
344 bptr = (bptr >> 12) | 0x80000000u;
345 ccsr_write4(OCP85XX_BPTR, bptr);
346 __asm __volatile("isync; msync");
347
| 417 bptr = (bptr >> 12) | 0x80000000u;
418 ccsr_write4(OCP85XX_BPTR, bptr);
419 __asm __volatile("isync; msync");
420
|
348 /* Flush caches to have our changes hit DRAM. */
349 cpu_flush_dcache(__boot_page, 4096);
| 421#endif /* QORIQ_DPAA */
|
350
351 /*
352 * Release AP from hold-off state
353 */
| 422
423 /*
424 * Release AP from hold-off state
425 */
|
354 eebpcr |= (1 << (pc->pc_cpuid + 24));
355 ccsr_write4(OCP85XX_EEBPCR, eebpcr);
| 426 reg = ccsr_read4(brr);
427 ccsr_write4(brr, reg | (1 << cpuid));
|
356 __asm __volatile("isync; msync");
357
358 timeout = 500;
359 while (!pc->pc_awake && timeout--)
360 DELAY(1000); /* wait 1ms */
361
362 /*
363 * Disable boot page translation so that the 4K page at the default
364 * address (= 0xfffff000) isn't permanently remapped and thus not
365 * usable otherwise.
366 */
| 428 __asm __volatile("isync; msync");
429
430 timeout = 500;
431 while (!pc->pc_awake && timeout--)
432 DELAY(1000); /* wait 1ms */
433
434 /*
435 * Disable boot page translation so that the 4K page at the default
436 * address (= 0xfffff000) isn't permanently remapped and thus not
437 * usable otherwise.
438 */
|
| 439#ifdef QORIQ_DPAA
440 ccsr_write4(OCP85XX_BSTAR, 0);
441#else
|
367 ccsr_write4(OCP85XX_BPTR, 0);
| 442 ccsr_write4(OCP85XX_BPTR, 0);
|
| 443#endif
|
368 __asm __volatile("isync; msync");
369
370 if (!pc->pc_awake)
371 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
372 return ((pc->pc_awake) ? 0 : EBUSY);
373#else
374 /* No SMP support */
375 return (ENXIO);
376#endif
377}
378
379static void
380mpc85xx_reset(platform_t plat)
381{
382
383 /*
384 * Try the dedicated reset register first.
385 * If the SoC doesn't have one, we'll fall
386 * back to using the debug control register.
387 */
388 ccsr_write4(OCP85XX_RSTCR, 2);
389
390 /* Clear DBCR0, disables debug interrupts and events. */
391 mtspr(SPR_DBCR0, 0);
392 __asm __volatile("isync");
393
394 /* Enable Debug Interrupts in MSR. */
395 mtmsr(mfmsr() | PSL_DE);
396
397 /* Enable debug interrupts and issue reset. */
398 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
399
400 printf("Reset failed...\n");
401 while (1)
402 ;
403}
404
| 444 __asm __volatile("isync; msync");
445
446 if (!pc->pc_awake)
447 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
448 return ((pc->pc_awake) ? 0 : EBUSY);
449#else
450 /* No SMP support */
451 return (ENXIO);
452#endif
453}
454
455static void
456mpc85xx_reset(platform_t plat)
457{
458
459 /*
460 * Try the dedicated reset register first.
461 * If the SoC doesn't have one, we'll fall
462 * back to using the debug control register.
463 */
464 ccsr_write4(OCP85XX_RSTCR, 2);
465
466 /* Clear DBCR0, disables debug interrupts and events. */
467 mtspr(SPR_DBCR0, 0);
468 __asm __volatile("isync");
469
470 /* Enable Debug Interrupts in MSR. */
471 mtmsr(mfmsr() | PSL_DE);
472
473 /* Enable debug interrupts and issue reset. */
474 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
475
476 printf("Reset failed...\n");
477 while (1)
478 ;
479}
480
|