1/*-
2 * Copyright (c) 2008-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/platform_mpc85xx.c 287011 2015-08-22 03:29:12Z jhibbits $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/bus.h>
34#include <sys/pcpu.h>
35#include <sys/proc.h>
36#include <sys/smp.h>
37
38#include <machine/bus.h>
39#include <machine/cpu.h>
40#include <machine/hid.h>
41#include <machine/platform.h>
42#include <machine/platformvar.h>
43#include <machine/smp.h>
44#include <machine/spr.h>
45#include <machine/vmparam.h>
46
47#include <dev/fdt/fdt_common.h>
48#include <dev/ofw/ofw_bus.h>

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170 ccsrbar |= ranges[i];
171 }
172 for (i = acells + pacells; i < acells + pacells + scells; i++) {
173 ccsrsize <<= 32;
174 ccsrsize |= ranges[i];
175 }
176 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize);
177
178 /*
179 * Clear local access windows. Skip DRAM entries, so we don't shoot
180 * ourselves in the foot.
181 */
182 law_max = law_getmax();
183 for (i = 0; i < law_max; i++) {
184 sr = ccsr_read4(OCP85XX_LAWSR(i));
185 if ((sr & 0x80000000) == 0)
186 continue;
187 tgt = (sr & 0x01f00000) >> 20;
188 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
189 tgt == OCP85XX_TGTIF_RAM_INTL)
190 continue;
191
192 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
193 }
194
195 return (0);
196}
197
198void
199mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz,
200 struct mem_region *avail, int *availsz)

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251 sizeof(freq)) <= 0)
252 goto out;
253
254 /*
255 * Time Base and Decrementer are updated every 8 CCB bus clocks.
256 * HID0[SEL_TBCLK] = 0
257 */
258 if (freq != 0)
259 ticks = freq / 8;
260
261out:
262 if (ticks <= 0)
263 panic("Unable to determine timebase frequency!");
264
265 return (ticks);
266}
267

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304 return (0);
305}
306
307static int
308mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc)
309{
310#ifdef SMP
311 uint32_t *tlb1;
312 uint32_t bptr, eebpcr;
313 int i, timeout;
314
315 eebpcr = ccsr_read4(OCP85XX_EEBPCR);
316 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) {
317 printf("SMP: CPU %d already out of hold-off state!\n",
318 pc->pc_cpuid);
319 return (ENXIO);
320 }
321
322 ap_pcpu = pc;
323
324 i = 0;
325 tlb1 = bp_tlb1;
326 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) {
327 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i));
328 __asm __volatile("isync; tlbre");
329 tlb1[0] = mfspr(SPR_MAS1);
330 tlb1[1] = mfspr(SPR_MAS2);
331 tlb1[2] = mfspr(SPR_MAS3);
332 i++;
333 tlb1 += 3;
334 }
335 if (i < bp_ntlb1s)
336 bp_ntlb1s = i;
337
338 /*
339 * Set BPTR to the physical address of the boot page
340 */
341 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
342 KASSERT((bptr & 0xfff) == 0,
343 ("%s: boot page is not aligned (%#x)", __func__, bptr));
344 bptr = (bptr >> 12) | 0x80000000u;
345 ccsr_write4(OCP85XX_BPTR, bptr);
346 __asm __volatile("isync; msync");
347
348 /* Flush caches to have our changes hit DRAM. */
349 cpu_flush_dcache(__boot_page, 4096);
350
351 /*
352 * Release AP from hold-off state
353 */
354 eebpcr |= (1 << (pc->pc_cpuid + 24));
355 ccsr_write4(OCP85XX_EEBPCR, eebpcr);
356 __asm __volatile("isync; msync");
357
358 timeout = 500;
359 while (!pc->pc_awake && timeout--)
360 DELAY(1000); /* wait 1ms */
361
362 /*
363 * Disable boot page translation so that the 4K page at the default
364 * address (= 0xfffff000) isn't permanently remapped and thus not
365 * usable otherwise.
366 */
367 ccsr_write4(OCP85XX_BPTR, 0);
368 __asm __volatile("isync; msync");
369
370 if (!pc->pc_awake)
371 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
372 return ((pc->pc_awake) ? 0 : EBUSY);
373#else
374 /* No SMP support */
375 return (ENXIO);

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