| mpc85xx.h (287011) | mpc85xx.h (291008) |
|---|---|
| 1/*- 2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski 3 * Copyright 2006 by Juniper Networks. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * | 1/*- 2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski 3 * Copyright 2006 by Juniper Networks. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
| 27 * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 287011 2015-08-22 03:29:12Z jhibbits $ | 27 * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 291008 2015-11-18 01:54:19Z jhibbits $ |
| 28 */ 29 30#ifndef _MPC85XX_H_ 31#define _MPC85XX_H_ 32 33#include <machine/platformvar.h> 34 35/* --- 7 unchanged lines hidden (view full) --- 43/* 44 * E500 Coherency Module registers 45 */ 46#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010) 47 48/* 49 * Local access registers 50 */ | 28 */ 29 30#ifndef _MPC85XX_H_ 31#define _MPC85XX_H_ 32 33#include <machine/platformvar.h> 34 35/* --- 7 unchanged lines hidden (view full) --- 43/* 44 * E500 Coherency Module registers 45 */ 46#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010) 47 48/* 49 * Local access registers 50 */ |
| 51#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n)) 52#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n)) | 51#if defined(QORIQ_DPAA) 52/* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */ 53#define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n)) 54#define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n)) 55#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) 56#else 57#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) 58#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n)) 59#endif |
| 53 | 60 |
| 54#define OCP85XX_TGTIF_LBC 4 55#define OCP85XX_TGTIF_RAM_INTL 11 56#define OCP85XX_TGTIF_RIO 12 57#define OCP85XX_TGTIF_RAM1 15 58#define OCP85XX_TGTIF_RAM2 22 | 61/* Attribute register */ 62#define OCP85XX_ENA_MASK 0x80000000 63#define OCP85XX_DIS_MASK 0x7fffffff |
| 59 | 64 |
| 65#if defined(QORIQ_DPAA) 66#define OCP85XX_TGTIF_LBC 0x1f 67#define OCP85XX_TGTIF_RAM_INTL 0x14 68#define OCP85XX_TGTIF_RAM1 0x10 69#define OCP85XX_TGTIF_RAM2 0x11 70#define OCP85XX_TGTIF_BMAN 0x18 71#define OCP85XX_TGTIF_QMAN 0x3C 72#define OCP85XX_TRGT_SHIFT 20 73#else 74#define OCP85XX_TGTIF_LBC 0x04 75#define OCP85XX_TGTIF_RAM_INTL 0x0b 76#define OCP85XX_TGTIF_RIO 0x0c 77#define OCP85XX_TGTIF_RAM1 0x0f 78#define OCP85XX_TGTIF_RAM2 0x16 79#endif 80 |
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| 60/* 61 * L2 cache registers 62 */ 63#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000) 64 65/* 66 * Power-On Reset configuration 67 */ --- 8 unchanged lines hidden (view full) --- 76 */ 77#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0) 78 79/* 80 * Prototypes. 81 */ 82uint32_t ccsr_read4(uintptr_t addr); 83void ccsr_write4(uintptr_t addr, uint32_t val); | 81/* 82 * L2 cache registers 83 */ 84#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000) 85 86/* 87 * Power-On Reset configuration 88 */ --- 8 unchanged lines hidden (view full) --- 97 */ 98#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0) 99 100/* 101 * Prototypes. 102 */ 103uint32_t ccsr_read4(uintptr_t addr); 104void ccsr_write4(uintptr_t addr, uint32_t val); |
| 84int law_enable(int trgt, u_long addr, u_long size); 85int law_disable(int trgt, u_long addr, u_long size); | 105int law_enable(int trgt, uint64_t bar, uint32_t size); 106int law_disable(int trgt, uint64_t bar, uint32_t size); |
| 86int law_getmax(void); 87int law_pci_target(struct resource *, int *, int *); 88 89DECLARE_CLASS(mpc85xx_platform); 90int mpc85xx_attach(platform_t); 91 92#endif /* _MPC85XX_H_ */ | 107int law_getmax(void); 108int law_pci_target(struct resource *, int *, int *); 109 110DECLARE_CLASS(mpc85xx_platform); 111int mpc85xx_attach(platform_t); 112 113#endif /* _MPC85XX_H_ */ |