27c27
< * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 291008 2015-11-18 01:54:19Z jhibbits $
---
> * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 292903 2015-12-30 03:43:25Z jhibbits $
42a43,49
> #define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
> #define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
> #define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
>
> #define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
> #define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
>
43a51,62
> * Run Control and Power Management registers
> */
> #define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
> #define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
> #define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
>
> /*
> * DDR Memory controller.
> */
> #define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080)
>
> /*
70a90
> #define OCP85XX_TGTIF_DCSR 0x1D
86a107,120
> * L3 CoreNet platform cache (CPC) registers
> */
> #define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000)
> #define OCP85XX_CPC_CSR0_CE 0x80000000
> #define OCP85XX_CPC_CSR0_PE 0x40000000
> #define OCP85XX_CPC_CSR0_FI 0x00200000
> #define OCP85XX_CPC_CSR0_WT 0x00080000
> #define OCP85XX_CPC_CSR0_FL 0x00000800
> #define OCP85XX_CPC_CSR0_LFC 0x00000400
> #define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008)
> #define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff
> #define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
>
> /*
112a147,150
> void mpc85xx_enable_l3_cache(void);
> void mpc85xx_fix_errata(vm_offset_t);
> void dataloss_erratum_access(vm_offset_t, uint32_t);
>