2a3
> * Copyright 2006 by Juniper Networks.
26c27
< * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 189757 2009-03-13 06:28:20Z raj $
---
> * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 209908 2010-07-11 21:08:29Z raj $
31a33,82
> /*
> * Configuration control and status registers
> */
> #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
> #define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
>
> /*
> * E500 Coherency Module registers
> */
> #define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
>
> /*
> * Local access registers
> */
> #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n))
> #define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n))
>
> #define OCP85XX_TGTIF_LBC 4
> #define OCP85XX_TGTIF_RAM_INTL 11
> #define OCP85XX_TGTIF_RIO 12
> #define OCP85XX_TGTIF_RAM1 15
> #define OCP85XX_TGTIF_RAM2 22
>
> /*
> * L2 cache registers
> */
> #define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
>
> /*
> * Power-On Reset configuration
> */
> #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
> #define OCP85XX_PORDEVSR_IO_SEL 0x00780000
> #define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
>
> #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
>
> #define OCP85XX_DEVDISR (CCSRBAR_VA + 0xe0070)
> #define OCP85XX_DEVDISR_PCIE0 0x20000000
> #define OCP85XX_DEVDISR_PCIE1 0x04000000
> #define OCP85XX_DEVDISR_PCIE2 0x02000000
>
> /*
> * Status Registers.
> */
> #define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
>
> /*
> * Prototypes.
> */
36a88
> int law_pci_target(struct resource *, int *, int *);