1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * Copyright 2006 by Juniper Networks.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
| 1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * Copyright 2006 by Juniper Networks.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
|
27 * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 291008 2015-11-18 01:54:19Z jhibbits $
| 27 * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 292903 2015-12-30 03:43:25Z jhibbits $
|
28 */
29
30#ifndef _MPC85XX_H_
31#define _MPC85XX_H_
32
33#include <machine/platformvar.h>
34
35/*
36 * Configuration control and status registers
37 */
38extern vm_offset_t ccsrbar_va;
39#define CCSRBAR_VA ccsrbar_va
40#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
41#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
42
| 28 */
29
30#ifndef _MPC85XX_H_
31#define _MPC85XX_H_
32
33#include <machine/platformvar.h>
34
35/*
36 * Configuration control and status registers
37 */
38extern vm_offset_t ccsrbar_va;
39#define CCSRBAR_VA ccsrbar_va
40#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
41#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
42
|
| 43#define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
44#define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
45#define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
46
47#define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
48#define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
49
|
43/*
| 50/*
|
| 51 * Run Control and Power Management registers
52 */
53#define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
54#define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
55#define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
56
57/*
58 * DDR Memory controller.
59 */
60#define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080)
61
62/*
|
44 * E500 Coherency Module registers
45 */
46#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
47
48/*
49 * Local access registers
50 */
51#if defined(QORIQ_DPAA)
52/* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */
53#define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n))
54#define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n))
55#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
56#else
57#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
58#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n))
59#endif
60
61/* Attribute register */
62#define OCP85XX_ENA_MASK 0x80000000
63#define OCP85XX_DIS_MASK 0x7fffffff
64
65#if defined(QORIQ_DPAA)
66#define OCP85XX_TGTIF_LBC 0x1f
67#define OCP85XX_TGTIF_RAM_INTL 0x14
68#define OCP85XX_TGTIF_RAM1 0x10
69#define OCP85XX_TGTIF_RAM2 0x11
70#define OCP85XX_TGTIF_BMAN 0x18
| 63 * E500 Coherency Module registers
64 */
65#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
66
67/*
68 * Local access registers
69 */
70#if defined(QORIQ_DPAA)
71/* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */
72#define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n))
73#define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n))
74#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
75#else
76#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
77#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n))
78#endif
79
80/* Attribute register */
81#define OCP85XX_ENA_MASK 0x80000000
82#define OCP85XX_DIS_MASK 0x7fffffff
83
84#if defined(QORIQ_DPAA)
85#define OCP85XX_TGTIF_LBC 0x1f
86#define OCP85XX_TGTIF_RAM_INTL 0x14
87#define OCP85XX_TGTIF_RAM1 0x10
88#define OCP85XX_TGTIF_RAM2 0x11
89#define OCP85XX_TGTIF_BMAN 0x18
|
| 90#define OCP85XX_TGTIF_DCSR 0x1D
|
71#define OCP85XX_TGTIF_QMAN 0x3C
72#define OCP85XX_TRGT_SHIFT 20
73#else
74#define OCP85XX_TGTIF_LBC 0x04
75#define OCP85XX_TGTIF_RAM_INTL 0x0b
76#define OCP85XX_TGTIF_RIO 0x0c
77#define OCP85XX_TGTIF_RAM1 0x0f
78#define OCP85XX_TGTIF_RAM2 0x16
79#endif
80
81/*
82 * L2 cache registers
83 */
84#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
85
86/*
| 91#define OCP85XX_TGTIF_QMAN 0x3C
92#define OCP85XX_TRGT_SHIFT 20
93#else
94#define OCP85XX_TGTIF_LBC 0x04
95#define OCP85XX_TGTIF_RAM_INTL 0x0b
96#define OCP85XX_TGTIF_RIO 0x0c
97#define OCP85XX_TGTIF_RAM1 0x0f
98#define OCP85XX_TGTIF_RAM2 0x16
99#endif
100
101/*
102 * L2 cache registers
103 */
104#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
105
106/*
|
| 107 * L3 CoreNet platform cache (CPC) registers
108 */
109#define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000)
110#define OCP85XX_CPC_CSR0_CE 0x80000000
111#define OCP85XX_CPC_CSR0_PE 0x40000000
112#define OCP85XX_CPC_CSR0_FI 0x00200000
113#define OCP85XX_CPC_CSR0_WT 0x00080000
114#define OCP85XX_CPC_CSR0_FL 0x00000800
115#define OCP85XX_CPC_CSR0_LFC 0x00000400
116#define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008)
117#define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff
118#define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
119
120/*
|
87 * Power-On Reset configuration
88 */
89#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
90#define OCP85XX_PORDEVSR_IO_SEL 0x00780000
91#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
92
93#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
94
95/*
96 * Status Registers.
97 */
98#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
99
100/*
101 * Prototypes.
102 */
103uint32_t ccsr_read4(uintptr_t addr);
104void ccsr_write4(uintptr_t addr, uint32_t val);
105int law_enable(int trgt, uint64_t bar, uint32_t size);
106int law_disable(int trgt, uint64_t bar, uint32_t size);
107int law_getmax(void);
108int law_pci_target(struct resource *, int *, int *);
109
110DECLARE_CLASS(mpc85xx_platform);
111int mpc85xx_attach(platform_t);
112
| 121 * Power-On Reset configuration
122 */
123#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
124#define OCP85XX_PORDEVSR_IO_SEL 0x00780000
125#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
126
127#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
128
129/*
130 * Status Registers.
131 */
132#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
133
134/*
135 * Prototypes.
136 */
137uint32_t ccsr_read4(uintptr_t addr);
138void ccsr_write4(uintptr_t addr, uint32_t val);
139int law_enable(int trgt, uint64_t bar, uint32_t size);
140int law_disable(int trgt, uint64_t bar, uint32_t size);
141int law_getmax(void);
142int law_pci_target(struct resource *, int *, int *);
143
144DECLARE_CLASS(mpc85xx_platform);
145int mpc85xx_attach(platform_t);
146
|
| 147void mpc85xx_enable_l3_cache(void);
148void mpc85xx_fix_errata(vm_offset_t);
149void dataloss_erratum_access(vm_offset_t, uint32_t);
150
|
113#endif /* _MPC85XX_H_ */
| 151#endif /* _MPC85XX_H_ */
|