1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * Copyright 2006 by Juniper Networks.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 287011 2015-08-22 03:29:12Z jhibbits $
28 */
29
30#ifndef _MPC85XX_H_
31#define _MPC85XX_H_
32
33#include <machine/platformvar.h>
34
35/*

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43/*
44 * E500 Coherency Module registers
45 */
46#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
47
48/*
49 * Local access registers
50 */
51#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x20 * (n))
52#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x20 * (n))
53
54#define OCP85XX_TGTIF_LBC 4
55#define OCP85XX_TGTIF_RAM_INTL 11
56#define OCP85XX_TGTIF_RIO 12
57#define OCP85XX_TGTIF_RAM1 15
58#define OCP85XX_TGTIF_RAM2 22
59
60/*
61 * L2 cache registers
62 */
63#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
64
65/*
66 * Power-On Reset configuration
67 */

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76 */
77#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
78
79/*
80 * Prototypes.
81 */
82uint32_t ccsr_read4(uintptr_t addr);
83void ccsr_write4(uintptr_t addr, uint32_t val);
84int law_enable(int trgt, u_long addr, u_long size);
85int law_disable(int trgt, u_long addr, u_long size);
86int law_getmax(void);
87int law_pci_target(struct resource *, int *, int *);
88
89DECLARE_CLASS(mpc85xx_platform);
90int mpc85xx_attach(platform_t);
91
92#endif /* _MPC85XX_H_ */