1/*-
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * Copyright 2006 by Juniper Networks.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
--- 10 unchanged lines hidden (view full) ---
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 292903 2015-12-30 03:43:25Z jhibbits $
28 */
29
30#ifndef _MPC85XX_H_
31#define _MPC85XX_H_
32
33#include <machine/platformvar.h>
34
35/*
36 * Configuration control and status registers
37 */
38extern vm_offset_t ccsrbar_va;
39#define CCSRBAR_VA ccsrbar_va
40#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
41#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
42
43#define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
44#define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
45#define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
46
47#define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
48#define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
49
50/*
51 * Run Control and Power Management registers
52 */
53#define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
54#define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
55#define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
56
57/*
58 * DDR Memory controller.
59 */
60#define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080)
61
62/*
63 * E500 Coherency Module registers
64 */
65#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
66
67/*
68 * Local access registers
69 */
70#if defined(QORIQ_DPAA)
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82#define OCP85XX_DIS_MASK 0x7fffffff
83
84#if defined(QORIQ_DPAA)
85#define OCP85XX_TGTIF_LBC 0x1f
86#define OCP85XX_TGTIF_RAM_INTL 0x14
87#define OCP85XX_TGTIF_RAM1 0x10
88#define OCP85XX_TGTIF_RAM2 0x11
89#define OCP85XX_TGTIF_BMAN 0x18
90#define OCP85XX_TGTIF_DCSR 0x1D
91#define OCP85XX_TGTIF_QMAN 0x3C
92#define OCP85XX_TRGT_SHIFT 20
93#else
94#define OCP85XX_TGTIF_LBC 0x04
95#define OCP85XX_TGTIF_RAM_INTL 0x0b
96#define OCP85XX_TGTIF_RIO 0x0c
97#define OCP85XX_TGTIF_RAM1 0x0f
98#define OCP85XX_TGTIF_RAM2 0x16
99#endif
100
101/*
102 * L2 cache registers
103 */
104#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
105
106/*
107 * L3 CoreNet platform cache (CPC) registers
108 */
109#define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000)
110#define OCP85XX_CPC_CSR0_CE 0x80000000
111#define OCP85XX_CPC_CSR0_PE 0x40000000
112#define OCP85XX_CPC_CSR0_FI 0x00200000
113#define OCP85XX_CPC_CSR0_WT 0x00080000
114#define OCP85XX_CPC_CSR0_FL 0x00000800
115#define OCP85XX_CPC_CSR0_LFC 0x00000400
116#define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008)
117#define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff
118#define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
119
120/*
121 * Power-On Reset configuration
122 */
123#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
124#define OCP85XX_PORDEVSR_IO_SEL 0x00780000
125#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
126
127#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
128
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139int law_enable(int trgt, uint64_t bar, uint32_t size);
140int law_disable(int trgt, uint64_t bar, uint32_t size);
141int law_getmax(void);
142int law_pci_target(struct resource *, int *, int *);
143
144DECLARE_CLASS(mpc85xx_platform);
145int mpc85xx_attach(platform_t);
146
147void mpc85xx_enable_l3_cache(void);
148void mpc85xx_fix_errata(vm_offset_t);
149void dataloss_erratum_access(vm_offset_t, uint32_t);
150
151#endif /* _MPC85XX_H_ */
2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski
3 * Copyright 2006 by Juniper Networks.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
--- 10 unchanged lines hidden (view full) ---
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.h 292903 2015-12-30 03:43:25Z jhibbits $
28 */
29
30#ifndef _MPC85XX_H_
31#define _MPC85XX_H_
32
33#include <machine/platformvar.h>
34
35/*
36 * Configuration control and status registers
37 */
38extern vm_offset_t ccsrbar_va;
39#define CCSRBAR_VA ccsrbar_va
40#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
41#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
42
43#define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
44#define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
45#define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
46
47#define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
48#define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
49
50/*
51 * Run Control and Power Management registers
52 */
53#define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
54#define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
55#define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
56
57/*
58 * DDR Memory controller.
59 */
60#define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080)
61
62/*
63 * E500 Coherency Module registers
64 */
65#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
66
67/*
68 * Local access registers
69 */
70#if defined(QORIQ_DPAA)
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82#define OCP85XX_DIS_MASK 0x7fffffff
83
84#if defined(QORIQ_DPAA)
85#define OCP85XX_TGTIF_LBC 0x1f
86#define OCP85XX_TGTIF_RAM_INTL 0x14
87#define OCP85XX_TGTIF_RAM1 0x10
88#define OCP85XX_TGTIF_RAM2 0x11
89#define OCP85XX_TGTIF_BMAN 0x18
90#define OCP85XX_TGTIF_DCSR 0x1D
91#define OCP85XX_TGTIF_QMAN 0x3C
92#define OCP85XX_TRGT_SHIFT 20
93#else
94#define OCP85XX_TGTIF_LBC 0x04
95#define OCP85XX_TGTIF_RAM_INTL 0x0b
96#define OCP85XX_TGTIF_RIO 0x0c
97#define OCP85XX_TGTIF_RAM1 0x0f
98#define OCP85XX_TGTIF_RAM2 0x16
99#endif
100
101/*
102 * L2 cache registers
103 */
104#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
105
106/*
107 * L3 CoreNet platform cache (CPC) registers
108 */
109#define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000)
110#define OCP85XX_CPC_CSR0_CE 0x80000000
111#define OCP85XX_CPC_CSR0_PE 0x40000000
112#define OCP85XX_CPC_CSR0_FI 0x00200000
113#define OCP85XX_CPC_CSR0_WT 0x00080000
114#define OCP85XX_CPC_CSR0_FL 0x00000800
115#define OCP85XX_CPC_CSR0_LFC 0x00000400
116#define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008)
117#define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff
118#define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
119
120/*
121 * Power-On Reset configuration
122 */
123#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
124#define OCP85XX_PORDEVSR_IO_SEL 0x00780000
125#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
126
127#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
128
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139int law_enable(int trgt, uint64_t bar, uint32_t size);
140int law_disable(int trgt, uint64_t bar, uint32_t size);
141int law_getmax(void);
142int law_pci_target(struct resource *, int *, int *);
143
144DECLARE_CLASS(mpc85xx_platform);
145int mpc85xx_attach(platform_t);
146
147void mpc85xx_enable_l3_cache(void);
148void mpc85xx_fix_errata(vm_offset_t);
149void dataloss_erratum_access(vm_offset_t, uint32_t);
150
151#endif /* _MPC85XX_H_ */