1/*- 2 * Copyright (C) 2008 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 14 unchanged lines hidden (view full) --- 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> |
31__FBSDID("$FreeBSD: head/sys/powerpc/mpc85xx/mpc85xx.c 178597 2008-04-26 18:03:00Z raj $"); |
32 33#include <sys/param.h> 34#include <sys/systm.h> 35 |
36#include <vm/vm.h> 37#include <vm/vm_param.h> 38 |
39#include <machine/cpu.h> 40#include <machine/cpufunc.h> |
41#include <machine/pio.h> |
42#include <machine/spr.h> 43 |
44#include <powerpc/mpc85xx/ocpbus.h> 45 |
46/* 47 * MPC85xx system specific routines 48 */ 49 50void 51cpu_reset() 52{ |
53 uint32_t svr = mfsvr(); |
54 |
55 if (svr == SVR_MPC8572E || svr == SVR_MPC8572) 56 /* Systems with dedicated reset register */ 57 out32(OCP85XX_RSTCR, 2); 58 else { 59 /* Clear DBCR0, disables debug interrupts and events. */ 60 mtspr(SPR_DBCR0, 0); 61 __asm volatile("isync"); |
62 |
63 /* Enable Debug Interrupts in MSR. */ 64 mtmsr(mfmsr() | PSL_DE); |
65 |
66 /* Enable debug interrupts and issue reset. */ 67 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 68 } 69 |
70 printf("Reset failed...\n"); 71 while (1); 72} |