1/*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $
| 1/*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $
|
33 */
34
35#ifndef _POWERPC_TRAP_H_
36#define _POWERPC_TRAP_H_
37
38#define EXC_RSVD 0x0000 /* Reserved */
39#define EXC_RST 0x0100 /* Reset; all but IBM4xx */
40#define EXC_MCHK 0x0200 /* Machine Check */
41#define EXC_DSI 0x0300 /* Data Storage Interrupt */
42#define EXC_DSE 0x0380 /* Data Segment Interrupt */
43#define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
44#define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
45#define EXC_EXI 0x0500 /* External Interrupt */
46#define EXC_ALI 0x0600 /* Alignment Interrupt */
47#define EXC_PGM 0x0700 /* Program Interrupt */
48#define EXC_FPU 0x0800 /* Floating-point Unavailable */
49#define EXC_DECR 0x0900 /* Decrementer Interrupt */
50#define EXC_SC 0x0c00 /* System Call */
51#define EXC_TRC 0x0d00 /* Trace */
52#define EXC_FPA 0x0e00 /* Floating-point Assist */
53
54/* The following is only available on the 601: */
55#define EXC_RUNMODETRC 0x2000 /* Run Mode/Trace Exception */
56
57/* The following are only available on 970(G5): */
58#define EXC_VECAST_G5 0x1700 /* AltiVec Assist */
59
60/* The following are only available on 7400(G4): */
61#define EXC_VEC 0x0f20 /* AltiVec Unavailable */
62#define EXC_VECAST_G4 0x1600 /* AltiVec Assist */
63
64/* The following are only available on 604/750/7400: */
65#define EXC_PERF 0x0f00 /* Performance Monitoring */
66#define EXC_BPT 0x1300 /* Instruction Breakpoint */
67#define EXC_SMI 0x1400 /* System Managment Interrupt */
68
69/* The following are only available on 750/7400: */
70#define EXC_THRM 0x1700 /* Thermal Management Interrupt */
71
72/* And these are only on the 603: */
73#define EXC_IMISS 0x1000 /* Instruction translation miss */
74#define EXC_DLMISS 0x1100 /* Data load translation miss */
75#define EXC_DSMISS 0x1200 /* Data store translation miss */
76
77/* The following are available on 4xx and 85xx */
78#define EXC_CRIT 0x0100 /* Critical Input Interrupt */
79#define EXC_PIT 0x1000 /* Programmable Interval Timer */
80#define EXC_FIT 0x1010 /* Fixed Interval Timer */
81#define EXC_WDOG 0x1020 /* Watchdog Timer */
82#define EXC_DTMISS 0x1100 /* Data TLB Miss */
83#define EXC_ITMISS 0x1200 /* Instruction TLB Miss */
84#define EXC_APU 0x1300 /* Auxiliary Processing Unit */
85#define EXC_DEBUG 0x2000 /* Debug trap */
86
87#define EXC_LAST 0x2f00 /* Last possible exception vector */
88
89#define EXC_AST 0x3000 /* Fake AST vector */
90
91/* Trap was in user mode */
92#define EXC_USER 0x10000
93
94
95/*
96 * EXC_ALI sets bits in the DSISR and DAR to provide enough
97 * information to recover from the unaligned access without needing to
98 * parse the offending instruction. This includes certain bits of the
99 * opcode, and information about what registers are used. The opcode
100 * indicator values below come from Appendix F of Book III of "The
101 * PowerPC Architecture".
102 */
103
104#define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
105#define EXC_ALI_LFD 0x09
106#define EXC_ALI_STFD 0x0b
107
108/* Macros to extract register information */
109#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */
110#define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
111
112/*
113 * SRR1 bits for program exception traps. These identify what caused
114 * the program exception. See section 6.5.9 of the Power ISA Version
115 * 2.05.
116 */
117
118#define EXC_PGM_FPENABLED (1UL << 20)
119#define EXC_PGM_ILLEGAL (1UL << 19)
120#define EXC_PGM_PRIV (1UL << 18)
121#define EXC_PGM_TRAP (1UL << 17)
122
123/* DTrace trap opcode. */
124#define EXC_DTRACE 0x7c810808
125
| 33 */
34
35#ifndef _POWERPC_TRAP_H_
36#define _POWERPC_TRAP_H_
37
38#define EXC_RSVD 0x0000 /* Reserved */
39#define EXC_RST 0x0100 /* Reset; all but IBM4xx */
40#define EXC_MCHK 0x0200 /* Machine Check */
41#define EXC_DSI 0x0300 /* Data Storage Interrupt */
42#define EXC_DSE 0x0380 /* Data Segment Interrupt */
43#define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
44#define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
45#define EXC_EXI 0x0500 /* External Interrupt */
46#define EXC_ALI 0x0600 /* Alignment Interrupt */
47#define EXC_PGM 0x0700 /* Program Interrupt */
48#define EXC_FPU 0x0800 /* Floating-point Unavailable */
49#define EXC_DECR 0x0900 /* Decrementer Interrupt */
50#define EXC_SC 0x0c00 /* System Call */
51#define EXC_TRC 0x0d00 /* Trace */
52#define EXC_FPA 0x0e00 /* Floating-point Assist */
53
54/* The following is only available on the 601: */
55#define EXC_RUNMODETRC 0x2000 /* Run Mode/Trace Exception */
56
57/* The following are only available on 970(G5): */
58#define EXC_VECAST_G5 0x1700 /* AltiVec Assist */
59
60/* The following are only available on 7400(G4): */
61#define EXC_VEC 0x0f20 /* AltiVec Unavailable */
62#define EXC_VECAST_G4 0x1600 /* AltiVec Assist */
63
64/* The following are only available on 604/750/7400: */
65#define EXC_PERF 0x0f00 /* Performance Monitoring */
66#define EXC_BPT 0x1300 /* Instruction Breakpoint */
67#define EXC_SMI 0x1400 /* System Managment Interrupt */
68
69/* The following are only available on 750/7400: */
70#define EXC_THRM 0x1700 /* Thermal Management Interrupt */
71
72/* And these are only on the 603: */
73#define EXC_IMISS 0x1000 /* Instruction translation miss */
74#define EXC_DLMISS 0x1100 /* Data load translation miss */
75#define EXC_DSMISS 0x1200 /* Data store translation miss */
76
77/* The following are available on 4xx and 85xx */
78#define EXC_CRIT 0x0100 /* Critical Input Interrupt */
79#define EXC_PIT 0x1000 /* Programmable Interval Timer */
80#define EXC_FIT 0x1010 /* Fixed Interval Timer */
81#define EXC_WDOG 0x1020 /* Watchdog Timer */
82#define EXC_DTMISS 0x1100 /* Data TLB Miss */
83#define EXC_ITMISS 0x1200 /* Instruction TLB Miss */
84#define EXC_APU 0x1300 /* Auxiliary Processing Unit */
85#define EXC_DEBUG 0x2000 /* Debug trap */
86
87#define EXC_LAST 0x2f00 /* Last possible exception vector */
88
89#define EXC_AST 0x3000 /* Fake AST vector */
90
91/* Trap was in user mode */
92#define EXC_USER 0x10000
93
94
95/*
96 * EXC_ALI sets bits in the DSISR and DAR to provide enough
97 * information to recover from the unaligned access without needing to
98 * parse the offending instruction. This includes certain bits of the
99 * opcode, and information about what registers are used. The opcode
100 * indicator values below come from Appendix F of Book III of "The
101 * PowerPC Architecture".
102 */
103
104#define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
105#define EXC_ALI_LFD 0x09
106#define EXC_ALI_STFD 0x0b
107
108/* Macros to extract register information */
109#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */
110#define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
111
112/*
113 * SRR1 bits for program exception traps. These identify what caused
114 * the program exception. See section 6.5.9 of the Power ISA Version
115 * 2.05.
116 */
117
118#define EXC_PGM_FPENABLED (1UL << 20)
119#define EXC_PGM_ILLEGAL (1UL << 19)
120#define EXC_PGM_PRIV (1UL << 18)
121#define EXC_PGM_TRAP (1UL << 17)
122
123/* DTrace trap opcode. */
124#define EXC_DTRACE 0x7c810808
125
|