| spr.h (96249) | spr.h (110385) |
|---|---|
| 1/* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * | 1/* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * |
| 33 * $FreeBSD: head/sys/powerpc/include/spr.h 96249 2002-05-09 14:04:43Z benno $ | 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ 34 * $FreeBSD: head/sys/powerpc/include/spr.h 110385 2003-02-05 12:04:29Z benno $ |
| 34 */ 35#ifndef _POWERPC_SPR_H_ 36#define _POWERPC_SPR_H_ 37 38#ifndef _LOCORE 39#define mtspr(reg, val) \ 40 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 41#define mfspr(reg) \ | 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ |
| 42 ( { u_int32_t val; \ | 43 ( { register_t val; \ |
| 43 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 44 val; } ) 45#endif /* _LOCORE */ 46 47/* 48 * Special Purpose Register declarations. 49 * 50 * The first column in the comments indicates which PowerPC --- 18 unchanged lines hidden (view full) --- 69#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 70#define SPR_DAR 0x013 /* .68 Data Address Register */ 71#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 72#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 73#define SPR_DEC 0x016 /* .68 DECrementer register */ 74#define SPR_SDR1 0x019 /* .68 Page table base address register */ 75#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 76#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ | 44 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 45 val; } ) 46#endif /* _LOCORE */ 47 48/* 49 * Special Purpose Register declarations. 50 * 51 * The first column in the comments indicates which PowerPC --- 18 unchanged lines hidden (view full) --- 70#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 71#define SPR_DAR 0x013 /* .68 Data Address Register */ 72#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 73#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 74#define SPR_DEC 0x016 /* .68 DECrementer register */ 75#define SPR_SDR1 0x019 /* .68 Page table base address register */ 76#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 77#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ |
| 78#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ 79#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ 80#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ |
|
| 77#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ | 81#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ |
| 82#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ |
|
| 78#define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 79#define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 80#define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 81#define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 82#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 83#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 84#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 85#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ | 83#define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 84#define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 85#define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 86#define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 87#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 88#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 89#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 90#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ |
| 91#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ |
|
| 86#define SPR_EAR 0x11a /* .68 External Access Register */ 87#define SPR_TBL 0x11c /* 468 Time Base Lower */ 88#define SPR_TBU 0x11d /* 468 Time Base Upper */ 89#define SPR_PVR 0x11f /* 468 Processor Version Register */ | 92#define SPR_EAR 0x11a /* .68 External Access Register */ 93#define SPR_TBL 0x11c /* 468 Time Base Lower */ 94#define SPR_TBU 0x11d /* 468 Time Base Upper */ 95#define SPR_PVR 0x11f /* 468 Processor Version Register */ |
| 90#define PVR_MPC601 0x0001 91#define PVR_MPC603 0x0003 92#define PVR_MPC604 0x0004 93#define PVR_MPC602 0x0005 94#define PVR_MPC603e 0x0006 95#define PVR_MPC603ev 0x0007 96#define PVR_MPC750 0x0008 97#define PVR_MPC604ev 0x0009 98#define PVR_MPC7400 0x000c 99#define PVR_MPC620 0x0014 100#define PVR_MPC860 0x0050 101#define PVR_MPC8240 0x0081 102#define PVR_MPC7450 0x8000 103#define PVR_MPC7455 0x8001 104#define PVR_MPC7410 0x800c 105#define PVR_IBM405GP 0x4011 106#define PVR_IBM405L 0x4161 | 96#define MPC601 0x0001 97#define MPC603 0x0003 98#define MPC604 0x0004 99#define MPC602 0x0005 100#define MPC603e 0x0006 101#define MPC603ev 0x0007 102#define MPC750 0x0008 103#define MPC604ev 0x0009 104#define MPC7400 0x000c 105#define MPC620 0x0014 106#define IBM403 0x0020 107#define IBM401A1 0x0021 108#define IBM401B2 0x0022 109#define IBM401C2 0x0023 110#define IBM401D2 0x0024 111#define IBM401E2 0x0025 112#define IBM401F2 0x0026 113#define IBM401G2 0x0027 114#define IBMPOWER3 0x0041 115#define MPC860 0x0050 116#define MPC8240 0x0081 117#define IBM405GP 0x4011 118#define IBM405L 0x4161 119#define IBM750FX 0x7000 120#define MPC7450 0x8000 121#define MPC7455 0x8001 122#define MPC7410 0x800c 123#define MPC8245 0x8081 124 |
| 107#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ | 125#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ |
| 108#define SPR_IBAT0L 0x211 /* .68 Instruction BAT Reg 0 Lower */ 109#define SPR_IBAT1U 0x212 /* .68 Instruction BAT Reg 1 Upper */ 110#define SPR_IBAT1L 0x213 /* .68 Instruction BAT Reg 1 Lower */ 111#define SPR_IBAT2U 0x214 /* .68 Instruction BAT Reg 2 Upper */ 112#define SPR_IBAT2L 0x215 /* .68 Instruction BAT Reg 2 Lower */ 113#define SPR_IBAT3U 0x216 /* .68 Instruction BAT Reg 3 Upper */ 114#define SPR_IBAT3L 0x217 /* .68 Instruction BAT Reg 3 Lower */ 115#define SPR_DBAT0U 0x218 /* .68 Data BAT Reg 0 Upper */ 116#define SPR_DBAT0L 0x219 /* .68 Data BAT Reg 0 Lower */ 117#define SPR_DBAT1U 0x21a /* .68 Data BAT Reg 1 Upper */ 118#define SPR_DBAT1L 0x21b /* .68 Data BAT Reg 1 Lower */ 119#define SPR_DBAT2U 0x21c /* .68 Data BAT Reg 2 Upper */ 120#define SPR_DBAT2L 0x21d /* .68 Data BAT Reg 2 Lower */ 121#define SPR_DBAT3U 0x21e /* .68 Data BAT Reg 3 Upper */ 122#define SPR_DBAT3L 0x21f /* .68 Data BAT Reg 3 Lower */ 123#define SPI_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 124#define SPI_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 125#define SPI_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 126#define SPI_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 127#define SPI_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 128#define SPI_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 129#define SPI_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 130#define SPI_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 131#define SPI_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 132#define SPI_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 133#define SPI_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 134#define SPI_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 135#define SPI_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 136#define SPI_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 137#define SPI_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 138#define SPI_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ | 126#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ 127#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ 128#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ 129#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ 130#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ 131#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ 132#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ 133#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ 134#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ 135#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ 136#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ 137#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ 138#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ 139#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ 140#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ 141#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ 142#define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ 143#define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ 144#define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ 145#define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ 146#define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ 147#define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ 148#define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ 149#define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ 150#define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ 151#define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ 152#define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ 153#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 154#define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ 155#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 156#define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ 157#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 158#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 159#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 160#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 161#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 162#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 163#define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */ 164#define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ 165#define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ 166#define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ 167#define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ 168#define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ 169#define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ 170#define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ 171#define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ 172#define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ 173#define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ 174#define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ 175#define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ 176#define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ 177#define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ 178#define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ 179#define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ 180#define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ 181#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 182#define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */ 183#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 184#define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */ 185#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 186#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 187#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 188#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 189#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 190#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ 191#define SPR_MI_CTR 0x310 /* ..8 IMMU control */ 192#define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ 193#define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ 194#define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ 195#define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ 196#define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ 197#define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ 198#define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ 199#define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ 200#define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ 201#define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ 202#define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ 203#define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ 204#define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ 205#define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ 206#define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ 207#define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ 208#define Mx_EPN_EV 0x00000020 /* Entry Valid */ 209#define Mx_EPN_ASID 0x0000000f /* Address Space ID */ 210#define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ 211#define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ 212#define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ 213#define Mx_TWC_G 0x00000010 /* Guarded memory */ 214#define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ 215#define MD_TWC_WT 0x00000002 /* Write-Through */ 216#define Mx_TWC_V 0x00000001 /* Entry Valid */ 217#define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ 218#define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ 219#define Mx_RPN_PP 0x00000ff0 /* Page Protection */ 220#define Mx_RPN_SPS 0x00000008 /* Small Page Size */ 221#define Mx_RPN_SH 0x00000004 /* SHared page */ 222#define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ 223#define Mx_RPN_V 0x00000001 /* Valid */ 224#define SPR_MD_CTR 0x318 /* ..8 DMMU control */ 225#define SPR_M_CASID 0x319 /* ..8 CASID */ 226#define M_CASID 0x0000000f /* Current AS Id */ 227#define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ 228#define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ 229#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ 230#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ 231#define M_TWB_L1INDX 0x00000ffc /* level-1 index */ 232#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ 233#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ 234#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ 235#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ 236#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ 237#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ 238#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ 239#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ 240#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ |
| 139#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 140#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 141#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 142#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 143#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 144#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 145#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 146#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ --- 136 unchanged lines hidden (view full) --- 283#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 284#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 285#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 286#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 287#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 288#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 289#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 290#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ | 241#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 242#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 243#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 244#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 245#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 246#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 247#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 248#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ --- 136 unchanged lines hidden (view full) --- 385#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 386#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 387#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 388#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 389#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 390#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 391#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 392#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ |
| 393#define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ 394#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ 395#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 396#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 397#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 398#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 399#define MSSCR0_MBO 0x00400000 /* 9: must be one */ 400#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 401#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 402#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ |
|
| 291#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 292#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 293#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ | 403#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 404#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 405#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ |
| 294#define L2CR_L2E 0x80000000 /* 0: L2 enable */ 295#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 296#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 297#define L2SIZ_2M 0x00000000 298#define L2SIZ_256K 0x10000000 299#define L2SIZ_512K 0x20000000 300#define L2SIZ_1M 0x30000000 301#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 302#define L2CLK_DIS 0x00000000 /* disable L2 clock */ 303#define L2CLK_10 0x02000000 /* core clock / 1 */ 304#define L2CLK_15 0x04000000 /* / 1.5 */ 305#define L2CLK_20 0x08000000 /* / 2 */ 306#define L2CLK_25 0x0a000000 /* / 2.5 */ 307#define L2CLK_30 0x0c000000 /* / 3 */ 308#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 309#define L2RAM_FLOWTHRU_BURST 0x00000000 310#define L2RAM_PIPELINE_BURST 0x01000000 311#define L2RAM_PIPELINE_LATE 0x01800000 312#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. | 406#define L2CR_L2E 0x80000000 /* 0: L2 enable */ 407#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 408#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 409#define L2SIZ_2M 0x00000000 410#define L2SIZ_256K 0x10000000 411#define L2SIZ_512K 0x20000000 412#define L2SIZ_1M 0x30000000 413#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 414#define L2CLK_DIS 0x00000000 /* disable L2 clock */ 415#define L2CLK_10 0x02000000 /* core clock / 1 */ 416#define L2CLK_15 0x04000000 /* / 1.5 */ 417#define L2CLK_20 0x08000000 /* / 2 */ 418#define L2CLK_25 0x0a000000 /* / 2.5 */ 419#define L2CLK_30 0x0c000000 /* / 3 */ 420#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 421#define L2RAM_FLOWTHRU_BURST 0x00000000 422#define L2RAM_PIPELINE_BURST 0x01000000 423#define L2RAM_PIPELINE_LATE 0x01800000 424#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. |
| 313 Setting this bit disables instruction 314 caching. */ | 425 Setting this bit disables instruction 426 caching. */ |
| 315#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 316#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). | 427#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 428#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). |
| 317 Enables automatic operation of the 318 L2ZZ (low-power mode) signal. */ | 429 Enables automatic operation of the 430 L2ZZ (low-power mode) signal. */ |
| 319#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 320#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 321#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 322#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 323#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 324#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 325#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ | 431#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 432#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 433#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 434#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 435#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 436#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 437#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 438#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 439#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 440#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 441#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ 442#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ |
| 326 /* progress (read only). */ 327#define SPR_L3CR 0x3fa /* .6. L3 Control Register */ | 443 /* progress (read only). */ 444#define SPR_L3CR 0x3fa /* .6. L3 Control Register */ |
| 328#define L3CR_L3E 0x80000000 /* 0: L3 enable */ 329#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ | 445#define L3CR_L3E 0x80000000 /* 0: L3 enable */ 446#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ |
| 330#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 331#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 332#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 333#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 334#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 335#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 336#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 337#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ --- 23 unchanged lines hidden --- | 447#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 448#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 449#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 450#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 451#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 452#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 453#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 454#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ --- 23 unchanged lines hidden --- |