| spr.h (255640) | spr.h (259284) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ | 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ |
| 27 * $FreeBSD: head/sys/powerpc/include/spr.h 255640 2013-09-17 17:29:56Z nwhitehorn $ | 27 * $FreeBSD: head/sys/powerpc/include/spr.h 259284 2013-12-13 02:37:35Z jhibbits $ |
| 28 */ 29#ifndef _POWERPC_SPR_H_ 30#define _POWERPC_SPR_H_ 31 32#ifndef _LOCORE 33#define mtspr(reg, val) \ 34 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 35#define mfspr(reg) \ --- 478 unchanged lines hidden (view full) --- 514#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 515#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 516#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 517#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 518#define MSSCR0_MBO 0x00400000 /* 9: must be one */ 519#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 520#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 521#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ | 28 */ 29#ifndef _POWERPC_SPR_H_ 30#define _POWERPC_SPR_H_ 31 32#ifndef _LOCORE 33#define mtspr(reg, val) \ 34 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 35#define mfspr(reg) \ --- 478 unchanged lines hidden (view full) --- 514#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 515#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 516#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 517#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 518#define MSSCR0_MBO 0x00400000 /* 9: must be one */ 519#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 520#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 521#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ |
| 522#define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ 523#define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ |
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| 522#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 523#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 524#define L2CR_L2E 0x80000000 /* 0: L2 enable */ 525#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 526#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 527#define L2SIZ_2M 0x00000000 528#define L2SIZ_256K 0x10000000 529#define L2SIZ_512K 0x20000000 --- 8 unchanged lines hidden (view full) --- 538#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 539#define L2RAM_FLOWTHRU_BURST 0x00000000 540#define L2RAM_PIPELINE_BURST 0x01000000 541#define L2RAM_PIPELINE_LATE 0x01800000 542#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 543 Setting this bit disables instruction 544 caching. */ 545#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ | 524#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 525#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 526#define L2CR_L2E 0x80000000 /* 0: L2 enable */ 527#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 528#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 529#define L2SIZ_2M 0x00000000 530#define L2SIZ_256K 0x10000000 531#define L2SIZ_512K 0x20000000 --- 8 unchanged lines hidden (view full) --- 540#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 541#define L2RAM_FLOWTHRU_BURST 0x00000000 542#define L2RAM_PIPELINE_BURST 0x01000000 543#define L2RAM_PIPELINE_LATE 0x01800000 544#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 545 Setting this bit disables instruction 546 caching. */ 547#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ |
| 548#define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */ |
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| 546#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 547 Enables automatic operation of the 548 L2ZZ (low-power mode) signal. */ 549#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 550#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 551#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ | 549#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 550 Enables automatic operation of the 551 L2ZZ (low-power mode) signal. */ 552#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 553#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 554#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ |
| 555#define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */ |
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| 552#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 553#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 554#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 555#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 556#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 557#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 558#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 559#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ --- 213 unchanged lines hidden --- | 556#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 557#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 558#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 559#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 560#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 561#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 562#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 563#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ --- 213 unchanged lines hidden --- |