| spr.h (190681) | spr.h (190953) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ | 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 17 unchanged lines hidden (view full) --- 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ |
| 34 * $FreeBSD: head/sys/powerpc/include/spr.h 190681 2009-04-04 00:22:44Z nwhitehorn $ | 34 * $FreeBSD: head/sys/powerpc/include/spr.h 190953 2009-04-12 03:03:55Z nwhitehorn $ |
| 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ --- 343 unchanged lines hidden (view full) --- 386#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 387#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 388 389#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 390#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 391#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 392#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 393#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ | 35 */ 36#ifndef _POWERPC_SPR_H_ 37#define _POWERPC_SPR_H_ 38 39#ifndef _LOCORE 40#define mtspr(reg, val) \ 41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 42#define mfspr(reg) \ --- 343 unchanged lines hidden (view full) --- 386#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 387#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 388 389#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 390#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 391#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 392#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 393#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ |
| 394#define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ 395#define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ |
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| 394 395#if defined(AIM) 396#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 397#define DBSR_IC 0x80000000 /* Instruction completion debug event */ 398#define DBSR_BT 0x40000000 /* Branch Taken debug event */ 399#define DBSR_EDE 0x20000000 /* Exception debug event */ 400#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 401#define DBSR_UDE 0x08000000 /* Unconditional debug event */ --- 270 unchanged lines hidden --- | 396 397#if defined(AIM) 398#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 399#define DBSR_IC 0x80000000 /* Instruction completion debug event */ 400#define DBSR_BT 0x40000000 /* Branch Taken debug event */ 401#define DBSR_EDE 0x20000000 /* Exception debug event */ 402#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 403#define DBSR_UDE 0x08000000 /* Unconditional debug event */ --- 270 unchanged lines hidden --- |