1/*-
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the NetBSD
16 * Foundation, Inc. and its contributors.
17 * 4. Neither the name of The NetBSD Foundation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $
| 1/*-
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the NetBSD
16 * Foundation, Inc. and its contributors.
17 * 4. Neither the name of The NetBSD Foundation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $
|
35 */
36#ifndef _POWERPC_SPR_H_
37#define _POWERPC_SPR_H_
38
39#ifndef _LOCORE
40#define mtspr(reg, val) \
41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
42#define mfspr(reg) \
43 ( { register_t val; \
44 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
45 val; } )
46#endif /* _LOCORE */
47
48/*
49 * Special Purpose Register declarations.
50 *
51 * The first column in the comments indicates which PowerPC
52 * architectures the SPR is valid on - 4 for 4xx series,
53 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series.
54 */
55
56#define SPR_MQ 0x000 /* .6. 601 MQ register */
57#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */
58#define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */
59#define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */
60#define SPR_LR 0x008 /* 468 Link Register */
61#define SPR_CTR 0x009 /* 468 Count Register */
62#define SPR_DSISR 0x012 /* .68 DSI exception source */
63#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
64#define DSISR_NOTFOUND 0x40000000 /* Translation not found */
65#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */
66#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */
67#define DSISR_STORE 0x02000000 /* Store operation */
68#define DSISR_DABR 0x00400000 /* DABR match */
69#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */
70#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
71#define SPR_DAR 0x013 /* .68 Data Address Register */
72#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */
73#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */
74#define SPR_DEC 0x016 /* .68 DECrementer register */
75#define SPR_SDR1 0x019 /* .68 Page table base address register */
76#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
77#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
78#define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */
79#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */
80#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
81#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */
82#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
83#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
84#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
85#define SPR_SPRG1 0x111 /* 468 SPR General 1 */
86#define SPR_SPRG2 0x112 /* 468 SPR General 2 */
87#define SPR_SPRG3 0x113 /* 468 SPR General 3 */
88#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */
89#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */
90#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */
91#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */
92#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */
93#define SPR_EAR 0x11a /* .68 External Access Register */
94#define SPR_TBL 0x11c /* 468 Time Base Lower */
95#define SPR_TBU 0x11d /* 468 Time Base Upper */
96#define SPR_PVR 0x11f /* 468 Processor Version Register */
97#define MPC601 0x0001
98#define MPC603 0x0003
99#define MPC604 0x0004
100#define MPC602 0x0005
101#define MPC603e 0x0006
102#define MPC603ev 0x0007
103#define MPC750 0x0008
104#define MPC604ev 0x0009
105#define MPC7400 0x000c
106#define MPC620 0x0014
107#define IBM403 0x0020
108#define IBM401A1 0x0021
109#define IBM401B2 0x0022
110#define IBM401C2 0x0023
111#define IBM401D2 0x0024
112#define IBM401E2 0x0025
113#define IBM401F2 0x0026
114#define IBM401G2 0x0027
115#define IBMPOWER3 0x0041
116#define MPC860 0x0050
117#define MPC8240 0x0081
118#define IBM405GP 0x4011
119#define IBM405L 0x4161
120#define IBM750FX 0x7000
121#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000)
122#define MPC7450 0x8000
123#define MPC7455 0x8001
124#define MPC7457 0x8002
125#define MPC7447A 0x8003
126#define MPC7448 0x8004
127#define MPC7410 0x800c
128#define MPC8245 0x8081
129#define FSL_E500v1 0x8020
130#define FSL_E500v2 0x8021
131
132#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
133#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */
134#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */
135#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */
136#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */
137#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */
138#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */
139#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */
140#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */
141#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */
142#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */
143#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */
144#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */
145#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */
146#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */
147#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */
148#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */
149#define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */
150#define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */
151#define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */
152#define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */
153#define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */
154#define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */
155#define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */
156#define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */
157#define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */
158#define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */
159#define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */
160#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
161#define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */
162#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
163#define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */
164#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
165#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
166#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
167#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
168#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
169#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
170#define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */
171#define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */
172#define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */
173#define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */
174#define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */
175#define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */
176#define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */
177#define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */
178#define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */
179#define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */
180#define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */
181#define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */
182#define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */
183#define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */
184#define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */
185#define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */
186#define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */
187#define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */
188#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
189#define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */
190#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
191#define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */
192#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
193#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
194#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
195#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
196#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
197#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
198#define SPR_MI_CTR 0x310 /* ..8 IMMU control */
199#define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */
200#define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */
201#define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */
202#define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */
203#define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */
204#define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */
205#define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */
206#define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */
207#define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */
208#define SPR_MI_AP 0x312 /* ..8 IMMU access protection */
209#define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */
210#define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */
211#define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */
212#define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */
213#define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */
214#define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */
215#define Mx_EPN_EV 0x00000020 /* Entry Valid */
216#define Mx_EPN_ASID 0x0000000f /* Address Space ID */
217#define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */
218#define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */
219#define Mx_TWC_APG 0x000001e0 /* Access Protection Group */
220#define Mx_TWC_G 0x00000010 /* Guarded memory */
221#define Mx_TWC_PS 0x0000000c /* Page Size (L1) */
222#define MD_TWC_WT 0x00000002 /* Write-Through */
223#define Mx_TWC_V 0x00000001 /* Entry Valid */
224#define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */
225#define Mx_RPN_RPN 0xfffff000 /* Real Page Number */
226#define Mx_RPN_PP 0x00000ff0 /* Page Protection */
227#define Mx_RPN_SPS 0x00000008 /* Small Page Size */
228#define Mx_RPN_SH 0x00000004 /* SHared page */
229#define Mx_RPN_CI 0x00000002 /* Cache Inhibit */
230#define Mx_RPN_V 0x00000001 /* Valid */
231#define SPR_MD_CTR 0x318 /* ..8 DMMU control */
232#define SPR_M_CASID 0x319 /* ..8 CASID */
233#define M_CASID 0x0000000f /* Current AS Id */
234#define SPR_MD_AP 0x31a /* ..8 DMMU access protection */
235#define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */
236#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */
237#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */
238#define M_TWB_L1INDX 0x00000ffc /* level-1 index */
239#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */
240#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */
241#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */
242#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */
243#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */
244#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */
245#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */
246#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */
247#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */
248#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */
249#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */
250#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */
251#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */
252#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */
253#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */
254#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */
255#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */
256#define SPR_PID 0x3b1 /* 4.. Process ID */
257#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */
258#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */
259#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */
260#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */
261#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */
262#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */
263#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */
264#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */
265#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */
266#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */
267#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */
268#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */
269#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */
270#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */
271#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */
272#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */
273#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */
274#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */
275#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */
276#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */
277#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */
278#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */
279#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */
280#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */
281#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */
282#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */
283#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */
284#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */
285#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */
286#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */
287#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */
288#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */
289#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */
290#define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */
291#define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */
292#define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */
293#define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */
294
295#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */
296#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */
297#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */
298#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */
299#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */
300#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */
301#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */
302#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */
303#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */
304#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */
305#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */
306#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */
307#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */
308#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */
309#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */
310#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */
311
312#define SPR_TSR 0x150 /* ..8 Timer Status Register */
313#define SPR_TCR 0x154 /* ..8 Timer Control Register */
314
315#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
316#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */
317#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */
318#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */
319#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */
320#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */
321#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */
322#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
323#define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */
324#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
325
326#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */
327#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */
328#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */
329#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */
330#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */
331#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */
332#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */
333#define TCR_WRC_CORE 0x10000000 /* Core reset */
334#define TCR_WRC_CHIP 0x20000000 /* Chip reset */
335#define TCR_WRC_SYSTEM 0x30000000 /* System reset */
336#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
337#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
338#define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */
339#define TCR_FP_MASK 0x03000000 /* FIT Period */
340#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */
341#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */
342#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */
343#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */
344#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
345#define TCR_ARE 0x00400000 /* Auto Reload Enable */
346
347#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */
348#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */
349#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */
350#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */
351#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */
352
353#if defined(AIM)
354#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */
355#define DBSR_IC 0x80000000 /* Instruction completion debug event */
356#define DBSR_BT 0x40000000 /* Branch Taken debug event */
357#define DBSR_EDE 0x20000000 /* Exception debug event */
358#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */
359#define DBSR_UDE 0x08000000 /* Unconditional debug event */
360#define DBSR_IA1 0x04000000 /* IAC1 debug event */
361#define DBSR_IA2 0x02000000 /* IAC2 debug event */
362#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */
363#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */
364#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */
365#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */
366#define DBSR_IDE 0x00100000 /* Imprecise debug event */
367#define DBSR_IA3 0x00080000 /* IAC3 debug event */
368#define DBSR_IA4 0x00040000 /* IAC4 debug event */
369#define DBSR_MRR 0x00000300 /* Most recent reset */
370#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */
371#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */
372#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */
373#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */
374#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */
375#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */
376#define SPR_PIR 0x3ff /* .6. Processor Identification Register */
377#elif defined(E500)
378#define SPR_DBSR 0x130 /* ..8 Debug Status Register */
379#define DBSR_IDE 0x80000000 /* Imprecise debug event. */
380#define DBSR_UDE 0x40000000 /* Unconditional debug event. */
381#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */
382#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */
383#define DBSR_BRT 0x04000000 /* Branch taken debug event. */
384#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */
385#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */
386#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */
387#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */
388#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */
389#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */
390#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */
391#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */
392#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */
393#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */
394#define DBSR_RET 0x00008000 /* Return debug event. */
395#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */
396#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */
397#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */
398#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */
399#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */
400#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */
401#endif
402
403#define DBCR0_EDM 0x80000000 /* External Debug Mode */
404#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
405#define DBCR0_RST_MASK 0x30000000 /* ReSeT */
406#define DBCR0_RST_NONE 0x00000000 /* No action */
407#define DBCR0_RST_CORE 0x10000000 /* Core reset */
408#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
409#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
410#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */
411#define DBCR0_BT 0x04000000 /* Branch Taken debug event */
412#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
413#define DBCR0_TDE 0x01000000 /* Trap Debug Event */
414#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */
415#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */
416#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */
417#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */
418#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */
419#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */
420#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
421#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */
422#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
423#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
424#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
425
426#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */
427#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */
428#define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */
429#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */
430#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
431#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
432#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
433#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */
434#define MSSCR0_MBO 0x00400000 /* 9: must be one */
435#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */
436#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */
437#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */
438#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */
439#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */
440#define L2CR_L2E 0x80000000 /* 0: L2 enable */
441#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
442#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
443#define L2SIZ_2M 0x00000000
444#define L2SIZ_256K 0x10000000
445#define L2SIZ_512K 0x20000000
446#define L2SIZ_1M 0x30000000
447#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
448#define L2CLK_DIS 0x00000000 /* disable L2 clock */
449#define L2CLK_10 0x02000000 /* core clock / 1 */
450#define L2CLK_15 0x04000000 /* / 1.5 */
451#define L2CLK_20 0x08000000 /* / 2 */
452#define L2CLK_25 0x0a000000 /* / 2.5 */
453#define L2CLK_30 0x0c000000 /* / 3 */
454#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
455#define L2RAM_FLOWTHRU_BURST 0x00000000
456#define L2RAM_PIPELINE_BURST 0x01000000
457#define L2RAM_PIPELINE_LATE 0x01800000
458#define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
459 Setting this bit disables instruction
460 caching. */
461#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */
462#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
463 Enables automatic operation of the
464 L2ZZ (low-power mode) signal. */
465#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
466#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */
467#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
468#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */
469#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */
470#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */
471#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */
472#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */
473#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */
474#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */
475#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */
476#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */
477 /* progress (read only). */
478
479#define SPR_L3CR 0x3fa /* .6. L3 Control Register */
480#define L3CR_L3E 0x80000000 /* 0: L3 enable */
481#define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */
482#define L3CR_L3APE 0x20000000
483#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
484#define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */
485#define L3CR_L3CLK 0x03800000
486#define L3CR_L3IO 0x00400000
487#define L3CR_L3CLKEXT 0x00200000
488#define L3CR_L3CKSPEXT 0x00100000
489#define L3CR_L3OH1 0x00080000
490#define L3CR_L3SPO 0x00040000
491#define L3CR_L3CKSP 0x00030000
492#define L3CR_L3PSP 0x0000e000
493#define L3CR_L3REP 0x00001000
494#define L3CR_L3HWF 0x00000800
495#define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */
496#define L3CR_L3RT 0x00000300
497#define L3CR_L3NIRCA 0x00000080
498#define L3CR_L3DO 0x00000040
499#define L3CR_PMEN 0x00000004
500#define L3CR_PMSIZ 0x00000003
501
502#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */
503#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */
504#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */
505#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */
506#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */
507#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */
508#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */
509#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */
510#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */
511#define SPR_THRM_VALID 0x00000001 /* Valid bit */
512#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */
513#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */
514#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */
515#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
516
517/* Time Base Register declarations */
518#define TBR_TBL 0x10c /* 468 Time Base Lower - read */
519#define TBR_TBU 0x10d /* 468 Time Base Upper - read */
520#define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */
521#define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */
522
523/* Performance counter declarations */
524#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */
525
526/* The first five countable [non-]events are common to all the PMC's */
527#define PMCN_NONE 0 /* Count nothing */
528#define PMCN_CYCLES 1 /* Processor cycles */
529#define PMCN_ICOMP 2 /* Instructions completed */
530#define PMCN_TBLTRANS 3 /* TBL bit transitions */
531#define PCMN_IDISPATCH 4 /* Instructions dispatched */
532
533#if defined(AIM)
534
535#define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */
536#define ESR_MCI 0x80000000 /* Machine check - instruction */
537#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
538#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
539#define ESR_PTR 0x02000000 /* Program interrupt - trap */
540#define ESR_ST 0x01000000 /* Store operation */
541#define ESR_DST 0x00800000 /* Data storage interrupt - store fault */
542#define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */
543#define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */
544
545#elif defined(E500)
546
547#define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */
548#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
549#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
550#define ESR_PTR 0x02000000 /* Program interrupt - trap */
551#define ESR_ST 0x00800000 /* Store operation */
552#define ESR_DLK 0x00200000 /* Data storage, D cache locking */
553#define ESR_ILK 0x00100000 /* Data storage, I cache locking */
554#define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */
555#define ESR_SPE 0x00000080 /* SPE exception bit */
556
557#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */
558#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */
559#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */
560#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */
561
562#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */
563#define SVR_MPC8533 0x803c
564#define SVR_MPC8533E 0x8034
565#define SVR_MPC8541 0x8072
566#define SVR_MPC8541E 0x807a
| 35 */
36#ifndef _POWERPC_SPR_H_
37#define _POWERPC_SPR_H_
38
39#ifndef _LOCORE
40#define mtspr(reg, val) \
41 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
42#define mfspr(reg) \
43 ( { register_t val; \
44 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
45 val; } )
46#endif /* _LOCORE */
47
48/*
49 * Special Purpose Register declarations.
50 *
51 * The first column in the comments indicates which PowerPC
52 * architectures the SPR is valid on - 4 for 4xx series,
53 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series.
54 */
55
56#define SPR_MQ 0x000 /* .6. 601 MQ register */
57#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */
58#define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */
59#define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */
60#define SPR_LR 0x008 /* 468 Link Register */
61#define SPR_CTR 0x009 /* 468 Count Register */
62#define SPR_DSISR 0x012 /* .68 DSI exception source */
63#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
64#define DSISR_NOTFOUND 0x40000000 /* Translation not found */
65#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */
66#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */
67#define DSISR_STORE 0x02000000 /* Store operation */
68#define DSISR_DABR 0x00400000 /* DABR match */
69#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */
70#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
71#define SPR_DAR 0x013 /* .68 Data Address Register */
72#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */
73#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */
74#define SPR_DEC 0x016 /* .68 DECrementer register */
75#define SPR_SDR1 0x019 /* .68 Page table base address register */
76#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
77#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
78#define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */
79#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */
80#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
81#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */
82#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
83#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
84#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
85#define SPR_SPRG1 0x111 /* 468 SPR General 1 */
86#define SPR_SPRG2 0x112 /* 468 SPR General 2 */
87#define SPR_SPRG3 0x113 /* 468 SPR General 3 */
88#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */
89#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */
90#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */
91#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */
92#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */
93#define SPR_EAR 0x11a /* .68 External Access Register */
94#define SPR_TBL 0x11c /* 468 Time Base Lower */
95#define SPR_TBU 0x11d /* 468 Time Base Upper */
96#define SPR_PVR 0x11f /* 468 Processor Version Register */
97#define MPC601 0x0001
98#define MPC603 0x0003
99#define MPC604 0x0004
100#define MPC602 0x0005
101#define MPC603e 0x0006
102#define MPC603ev 0x0007
103#define MPC750 0x0008
104#define MPC604ev 0x0009
105#define MPC7400 0x000c
106#define MPC620 0x0014
107#define IBM403 0x0020
108#define IBM401A1 0x0021
109#define IBM401B2 0x0022
110#define IBM401C2 0x0023
111#define IBM401D2 0x0024
112#define IBM401E2 0x0025
113#define IBM401F2 0x0026
114#define IBM401G2 0x0027
115#define IBMPOWER3 0x0041
116#define MPC860 0x0050
117#define MPC8240 0x0081
118#define IBM405GP 0x4011
119#define IBM405L 0x4161
120#define IBM750FX 0x7000
121#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000)
122#define MPC7450 0x8000
123#define MPC7455 0x8001
124#define MPC7457 0x8002
125#define MPC7447A 0x8003
126#define MPC7448 0x8004
127#define MPC7410 0x800c
128#define MPC8245 0x8081
129#define FSL_E500v1 0x8020
130#define FSL_E500v2 0x8021
131
132#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
133#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */
134#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */
135#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */
136#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */
137#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */
138#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */
139#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */
140#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */
141#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */
142#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */
143#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */
144#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */
145#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */
146#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */
147#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */
148#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */
149#define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */
150#define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */
151#define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */
152#define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */
153#define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */
154#define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */
155#define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */
156#define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */
157#define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */
158#define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */
159#define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */
160#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
161#define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */
162#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
163#define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */
164#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
165#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
166#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
167#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
168#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
169#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
170#define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */
171#define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */
172#define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */
173#define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */
174#define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */
175#define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */
176#define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */
177#define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */
178#define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */
179#define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */
180#define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */
181#define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */
182#define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */
183#define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */
184#define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */
185#define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */
186#define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */
187#define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */
188#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
189#define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */
190#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
191#define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */
192#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
193#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
194#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
195#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
196#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
197#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
198#define SPR_MI_CTR 0x310 /* ..8 IMMU control */
199#define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */
200#define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */
201#define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */
202#define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */
203#define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */
204#define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */
205#define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */
206#define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */
207#define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */
208#define SPR_MI_AP 0x312 /* ..8 IMMU access protection */
209#define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */
210#define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */
211#define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */
212#define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */
213#define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */
214#define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */
215#define Mx_EPN_EV 0x00000020 /* Entry Valid */
216#define Mx_EPN_ASID 0x0000000f /* Address Space ID */
217#define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */
218#define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */
219#define Mx_TWC_APG 0x000001e0 /* Access Protection Group */
220#define Mx_TWC_G 0x00000010 /* Guarded memory */
221#define Mx_TWC_PS 0x0000000c /* Page Size (L1) */
222#define MD_TWC_WT 0x00000002 /* Write-Through */
223#define Mx_TWC_V 0x00000001 /* Entry Valid */
224#define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */
225#define Mx_RPN_RPN 0xfffff000 /* Real Page Number */
226#define Mx_RPN_PP 0x00000ff0 /* Page Protection */
227#define Mx_RPN_SPS 0x00000008 /* Small Page Size */
228#define Mx_RPN_SH 0x00000004 /* SHared page */
229#define Mx_RPN_CI 0x00000002 /* Cache Inhibit */
230#define Mx_RPN_V 0x00000001 /* Valid */
231#define SPR_MD_CTR 0x318 /* ..8 DMMU control */
232#define SPR_M_CASID 0x319 /* ..8 CASID */
233#define M_CASID 0x0000000f /* Current AS Id */
234#define SPR_MD_AP 0x31a /* ..8 DMMU access protection */
235#define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */
236#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */
237#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */
238#define M_TWB_L1INDX 0x00000ffc /* level-1 index */
239#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */
240#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */
241#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */
242#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */
243#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */
244#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */
245#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */
246#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */
247#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */
248#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */
249#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */
250#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */
251#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */
252#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */
253#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */
254#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */
255#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */
256#define SPR_PID 0x3b1 /* 4.. Process ID */
257#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */
258#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */
259#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */
260#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */
261#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */
262#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */
263#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */
264#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */
265#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */
266#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */
267#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */
268#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */
269#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */
270#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */
271#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */
272#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */
273#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */
274#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */
275#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */
276#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */
277#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */
278#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */
279#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */
280#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */
281#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */
282#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */
283#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */
284#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */
285#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */
286#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */
287#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */
288#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */
289#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */
290#define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */
291#define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */
292#define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */
293#define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */
294
295#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */
296#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */
297#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */
298#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */
299#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */
300#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */
301#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */
302#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */
303#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */
304#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */
305#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */
306#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */
307#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */
308#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */
309#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */
310#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */
311
312#define SPR_TSR 0x150 /* ..8 Timer Status Register */
313#define SPR_TCR 0x154 /* ..8 Timer Control Register */
314
315#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
316#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */
317#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */
318#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */
319#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */
320#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */
321#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */
322#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
323#define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */
324#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
325
326#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */
327#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */
328#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */
329#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */
330#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */
331#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */
332#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */
333#define TCR_WRC_CORE 0x10000000 /* Core reset */
334#define TCR_WRC_CHIP 0x20000000 /* Chip reset */
335#define TCR_WRC_SYSTEM 0x30000000 /* System reset */
336#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
337#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
338#define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */
339#define TCR_FP_MASK 0x03000000 /* FIT Period */
340#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */
341#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */
342#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */
343#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */
344#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
345#define TCR_ARE 0x00400000 /* Auto Reload Enable */
346
347#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */
348#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */
349#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */
350#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */
351#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */
352
353#if defined(AIM)
354#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */
355#define DBSR_IC 0x80000000 /* Instruction completion debug event */
356#define DBSR_BT 0x40000000 /* Branch Taken debug event */
357#define DBSR_EDE 0x20000000 /* Exception debug event */
358#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */
359#define DBSR_UDE 0x08000000 /* Unconditional debug event */
360#define DBSR_IA1 0x04000000 /* IAC1 debug event */
361#define DBSR_IA2 0x02000000 /* IAC2 debug event */
362#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */
363#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */
364#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */
365#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */
366#define DBSR_IDE 0x00100000 /* Imprecise debug event */
367#define DBSR_IA3 0x00080000 /* IAC3 debug event */
368#define DBSR_IA4 0x00040000 /* IAC4 debug event */
369#define DBSR_MRR 0x00000300 /* Most recent reset */
370#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */
371#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */
372#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */
373#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */
374#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */
375#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */
376#define SPR_PIR 0x3ff /* .6. Processor Identification Register */
377#elif defined(E500)
378#define SPR_DBSR 0x130 /* ..8 Debug Status Register */
379#define DBSR_IDE 0x80000000 /* Imprecise debug event. */
380#define DBSR_UDE 0x40000000 /* Unconditional debug event. */
381#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */
382#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */
383#define DBSR_BRT 0x04000000 /* Branch taken debug event. */
384#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */
385#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */
386#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */
387#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */
388#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */
389#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */
390#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */
391#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */
392#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */
393#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */
394#define DBSR_RET 0x00008000 /* Return debug event. */
395#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */
396#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */
397#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */
398#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */
399#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */
400#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */
401#endif
402
403#define DBCR0_EDM 0x80000000 /* External Debug Mode */
404#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
405#define DBCR0_RST_MASK 0x30000000 /* ReSeT */
406#define DBCR0_RST_NONE 0x00000000 /* No action */
407#define DBCR0_RST_CORE 0x10000000 /* Core reset */
408#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
409#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
410#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */
411#define DBCR0_BT 0x04000000 /* Branch Taken debug event */
412#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
413#define DBCR0_TDE 0x01000000 /* Trap Debug Event */
414#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */
415#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */
416#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */
417#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */
418#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */
419#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */
420#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
421#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */
422#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
423#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
424#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
425
426#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */
427#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */
428#define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */
429#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */
430#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
431#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
432#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
433#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */
434#define MSSCR0_MBO 0x00400000 /* 9: must be one */
435#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */
436#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */
437#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */
438#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */
439#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */
440#define L2CR_L2E 0x80000000 /* 0: L2 enable */
441#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
442#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
443#define L2SIZ_2M 0x00000000
444#define L2SIZ_256K 0x10000000
445#define L2SIZ_512K 0x20000000
446#define L2SIZ_1M 0x30000000
447#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
448#define L2CLK_DIS 0x00000000 /* disable L2 clock */
449#define L2CLK_10 0x02000000 /* core clock / 1 */
450#define L2CLK_15 0x04000000 /* / 1.5 */
451#define L2CLK_20 0x08000000 /* / 2 */
452#define L2CLK_25 0x0a000000 /* / 2.5 */
453#define L2CLK_30 0x0c000000 /* / 3 */
454#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
455#define L2RAM_FLOWTHRU_BURST 0x00000000
456#define L2RAM_PIPELINE_BURST 0x01000000
457#define L2RAM_PIPELINE_LATE 0x01800000
458#define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
459 Setting this bit disables instruction
460 caching. */
461#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */
462#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
463 Enables automatic operation of the
464 L2ZZ (low-power mode) signal. */
465#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
466#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */
467#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
468#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */
469#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */
470#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */
471#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */
472#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */
473#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */
474#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */
475#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */
476#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */
477 /* progress (read only). */
478
479#define SPR_L3CR 0x3fa /* .6. L3 Control Register */
480#define L3CR_L3E 0x80000000 /* 0: L3 enable */
481#define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */
482#define L3CR_L3APE 0x20000000
483#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
484#define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */
485#define L3CR_L3CLK 0x03800000
486#define L3CR_L3IO 0x00400000
487#define L3CR_L3CLKEXT 0x00200000
488#define L3CR_L3CKSPEXT 0x00100000
489#define L3CR_L3OH1 0x00080000
490#define L3CR_L3SPO 0x00040000
491#define L3CR_L3CKSP 0x00030000
492#define L3CR_L3PSP 0x0000e000
493#define L3CR_L3REP 0x00001000
494#define L3CR_L3HWF 0x00000800
495#define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */
496#define L3CR_L3RT 0x00000300
497#define L3CR_L3NIRCA 0x00000080
498#define L3CR_L3DO 0x00000040
499#define L3CR_PMEN 0x00000004
500#define L3CR_PMSIZ 0x00000003
501
502#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */
503#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */
504#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */
505#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */
506#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */
507#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */
508#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */
509#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */
510#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */
511#define SPR_THRM_VALID 0x00000001 /* Valid bit */
512#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */
513#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */
514#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */
515#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
516
517/* Time Base Register declarations */
518#define TBR_TBL 0x10c /* 468 Time Base Lower - read */
519#define TBR_TBU 0x10d /* 468 Time Base Upper - read */
520#define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */
521#define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */
522
523/* Performance counter declarations */
524#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */
525
526/* The first five countable [non-]events are common to all the PMC's */
527#define PMCN_NONE 0 /* Count nothing */
528#define PMCN_CYCLES 1 /* Processor cycles */
529#define PMCN_ICOMP 2 /* Instructions completed */
530#define PMCN_TBLTRANS 3 /* TBL bit transitions */
531#define PCMN_IDISPATCH 4 /* Instructions dispatched */
532
533#if defined(AIM)
534
535#define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */
536#define ESR_MCI 0x80000000 /* Machine check - instruction */
537#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
538#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
539#define ESR_PTR 0x02000000 /* Program interrupt - trap */
540#define ESR_ST 0x01000000 /* Store operation */
541#define ESR_DST 0x00800000 /* Data storage interrupt - store fault */
542#define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */
543#define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */
544
545#elif defined(E500)
546
547#define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */
548#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
549#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
550#define ESR_PTR 0x02000000 /* Program interrupt - trap */
551#define ESR_ST 0x00800000 /* Store operation */
552#define ESR_DLK 0x00200000 /* Data storage, D cache locking */
553#define ESR_ILK 0x00100000 /* Data storage, I cache locking */
554#define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */
555#define ESR_SPE 0x00000080 /* SPE exception bit */
556
557#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */
558#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */
559#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */
560#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */
561
562#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */
563#define SVR_MPC8533 0x803c
564#define SVR_MPC8533E 0x8034
565#define SVR_MPC8541 0x8072
566#define SVR_MPC8541E 0x807a
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