| hid.h (125614) | hid.h (141224) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 10 unchanged lines hidden (view full) --- 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $ | 1/*- 2 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 10 unchanged lines hidden (view full) --- 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $ |
| 27 * $FreeBSD: head/sys/powerpc/include/hid.h 125614 2004-02-09 00:12:50Z grehan $ | 27 * $FreeBSD: head/sys/powerpc/include/hid.h 141224 2005-02-04 01:14:38Z grehan $ |
| 28 */ 29 30#ifndef _POWERPC_HID_H_ 31#define _POWERPC_HID_H_ 32 33/* Hardware Implementation Dependent registers for the PowerPC */ 34 35#define HID0_EMCP 0x80000000 /* Enable MCP */ 36#define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */ 37#define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */ 38#define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */ 39#define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */ 40#define HID0_EICE 0x04000000 /* Enable ICE output */ 41#define HID0_TBEN 0x04000000 /* Time base enable (7450) */ 42#define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */ 43#define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */ 44#define HID0_STEN 0x01000000 /* Software table search enable (7450) */ | 28 */ 29 30#ifndef _POWERPC_HID_H_ 31#define _POWERPC_HID_H_ 32 33/* Hardware Implementation Dependent registers for the PowerPC */ 34 35#define HID0_EMCP 0x80000000 /* Enable MCP */ 36#define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */ 37#define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */ 38#define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */ 39#define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */ 40#define HID0_EICE 0x04000000 /* Enable ICE output */ 41#define HID0_TBEN 0x04000000 /* Time base enable (7450) */ 42#define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */ 43#define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */ 44#define HID0_STEN 0x01000000 /* Software table search enable (7450) */ |
| 45#define HID0_HBATEN 0x00800000 /* High BAT enable (7457) */ | 45#define HID0_HBATEN 0x00800000 /* High BAT enable (74[45][578]) */ |
| 46#define HID0_DOZE 0x00800000 /* Enable doze mode */ 47#define HID0_NAP 0x00400000 /* Enable nap mode */ 48#define HID0_SLEEP 0x00200000 /* Enable sleep mode */ 49#define HID0_DPM 0x00100000 /* Enable Dynamic power management */ 50#define HID0_RISEG 0x00080000 /* Read I-SEG */ | 46#define HID0_DOZE 0x00800000 /* Enable doze mode */ 47#define HID0_NAP 0x00400000 /* Enable nap mode */ 48#define HID0_SLEEP 0x00200000 /* Enable sleep mode */ 49#define HID0_DPM 0x00100000 /* Enable Dynamic power management */ 50#define HID0_RISEG 0x00080000 /* Read I-SEG */ |
| 51#define HID0_BHTCLR 0x00080000 /* Clear branch history table (7450) */ | 51#define HID0_BHTCLR 0x00040000 /* Clear branch history table (7450) */ |
| 52#define HID0_EIEC 0x00040000 /* Enable internal error checking */ | 52#define HID0_EIEC 0x00040000 /* Enable internal error checking */ |
| 53#define HID0_XAEN 0x00040000 /* Enable eXtended Addressing (7450) */ | 53#define HID0_XAEN 0x00020000 /* Enable eXtended Addressing (7450) */ |
| 54#define HID0_NHR 0x00010000 /* Not hard reset */ 55#define HID0_ICE 0x00008000 /* Enable i-cache */ 56#define HID0_DCE 0x00004000 /* Enable d-cache */ 57#define HID0_ILOCK 0x00002000 /* i-cache lock */ 58#define HID0_DLOCK 0x00001000 /* d-cache lock */ 59#define HID0_ICFI 0x00000800 /* i-cache flush invalidate */ 60#define HID0_DCFI 0x00000400 /* d-cache flush invalidate */ 61#define HID0_SPD 0x00000200 /* Disable speculative cache access */ 62#define HID0_XBSEN 0x00000100 /* Extended BAT block-size enable (7457) */ 63#define HID0_IFEM 0x00000100 /* Enable M-bit for I-fetch */ | 54#define HID0_NHR 0x00010000 /* Not hard reset */ 55#define HID0_ICE 0x00008000 /* Enable i-cache */ 56#define HID0_DCE 0x00004000 /* Enable d-cache */ 57#define HID0_ILOCK 0x00002000 /* i-cache lock */ 58#define HID0_DLOCK 0x00001000 /* d-cache lock */ 59#define HID0_ICFI 0x00000800 /* i-cache flush invalidate */ 60#define HID0_DCFI 0x00000400 /* d-cache flush invalidate */ 61#define HID0_SPD 0x00000200 /* Disable speculative cache access */ 62#define HID0_XBSEN 0x00000100 /* Extended BAT block-size enable (7457) */ 63#define HID0_IFEM 0x00000100 /* Enable M-bit for I-fetch */ |
| 64#define HID0_XBSEN 0x00000100 /* Extended BAT block size enable (7455+)*/ |
|
| 64#define HID0_SGE 0x00000080 /* Enable store gathering */ 65#define HID0_DCFA 0x00000040 /* Data cache flush assist */ 66#define HID0_BTIC 0x00000020 /* Enable BTIC */ | 65#define HID0_SGE 0x00000080 /* Enable store gathering */ 66#define HID0_DCFA 0x00000040 /* Data cache flush assist */ 67#define HID0_BTIC 0x00000020 /* Enable BTIC */ |
| 68#define HID0_LRSTK 0x00000010 /* Link register stack enable (7450) */ |
|
| 67#define HID0_ABE 0x00000008 /* Enable address broadcast */ | 69#define HID0_ABE 0x00000008 /* Enable address broadcast */ |
| 70#define HID0_FOLD 0x00000008 /* Branch folding enable (7450) */ |
|
| 68#define HID0_BHT 0x00000004 /* Enable branch history table */ 69#define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */ 70 71#define HID0_BITMASK \ 72 "\20" \ 73 "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \ 74 "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \ 75 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \ --- 59 unchanged lines hidden --- | 71#define HID0_BHT 0x00000004 /* Enable branch history table */ 72#define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */ 73 74#define HID0_BITMASK \ 75 "\20" \ 76 "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \ 77 "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \ 78 "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \ --- 59 unchanged lines hidden --- |