| platform_bare.c (193492) | platform_bare.c (209908) |
|---|---|
| 1/*- 2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/powerpc/booke/platform_bare.c 193492 2009-06-05 09:46:00Z raj $"); | 28__FBSDID("$FreeBSD: head/sys/powerpc/booke/platform_bare.c 209908 2010-07-11 21:08:29Z raj $"); |
| 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/pcpu.h> 35#include <sys/proc.h> 36#include <sys/smp.h> 37 | 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/pcpu.h> 35#include <sys/proc.h> 36#include <sys/smp.h> 37 |
| 38#include <machine/bootinfo.h> | |
| 39#include <machine/bus.h> 40#include <machine/cpu.h> 41#include <machine/hid.h> 42#include <machine/platform.h> 43#include <machine/platformvar.h> 44#include <machine/smp.h> 45#include <machine/spr.h> 46#include <machine/vmparam.h> 47 | 38#include <machine/bus.h> 39#include <machine/cpu.h> 40#include <machine/hid.h> 41#include <machine/platform.h> 42#include <machine/platformvar.h> 43#include <machine/smp.h> 44#include <machine/spr.h> 45#include <machine/vmparam.h> 46 |
| 47#include <dev/fdt/fdt_common.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50#include <dev/ofw/openfirm.h> 51 |
|
| 48#include <powerpc/mpc85xx/mpc85xx.h> | 52#include <powerpc/mpc85xx/mpc85xx.h> |
| 49#include <powerpc/mpc85xx/ocpbus.h> | |
| 50 51#include "platform_if.h" 52 53#ifdef SMP 54extern void *ap_pcpu; 55extern uint8_t __boot_page[]; /* Boot page body */ 56extern uint32_t kernload; /* Kernel physical load address */ 57#endif --- 28 unchanged lines hidden (view full) --- 86 0 87}; 88 89PLATFORM_DEF(bare_platform); 90 91static int 92bare_probe(platform_t plat) 93{ | 53 54#include "platform_if.h" 55 56#ifdef SMP 57extern void *ap_pcpu; 58extern uint8_t __boot_page[]; /* Boot page body */ 59extern uint32_t kernload; /* Kernel physical load address */ 60#endif --- 28 unchanged lines hidden (view full) --- 89 0 90}; 91 92PLATFORM_DEF(bare_platform); 93 94static int 95bare_probe(platform_t plat) 96{ |
| 94 uint32_t ver; | 97 uint32_t ver, sr; 98 int i, law_max, tgt; |
| 95 96 ver = SVR_VER(mfspr(SPR_SVR)); 97 if (ver == SVR_MPC8572E || ver == SVR_MPC8572) 98 maxcpu = 2; 99 else 100 maxcpu = 1; 101 | 99 100 ver = SVR_VER(mfspr(SPR_SVR)); 101 if (ver == SVR_MPC8572E || ver == SVR_MPC8572) 102 maxcpu = 2; 103 else 104 maxcpu = 1; 105 |
| 106 /* 107 * Clear local access windows. Skip DRAM entries, so we don't shoot 108 * ourselves in the foot. 109 */ 110 law_max = law_getmax(); 111 for (i = 0; i < law_max; i++) { 112 sr = ccsr_read4(OCP85XX_LAWSR(i)); 113 if ((sr & 0x80000000) == 0) 114 continue; 115 tgt = (sr & 0x01f00000) >> 20; 116 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 117 tgt == OCP85XX_TGTIF_RAM_INTL) 118 continue; 119 120 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 121 } 122 |
|
| 102 return (BUS_PROBE_GENERIC); 103} 104 105#define MEM_REGIONS 8 106static struct mem_region avail_regions[MEM_REGIONS]; 107 108void 109bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 110 struct mem_region **avail, int *availsz) 111{ | 123 return (BUS_PROBE_GENERIC); 124} 125 126#define MEM_REGIONS 8 127static struct mem_region avail_regions[MEM_REGIONS]; 128 129void 130bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 131 struct mem_region **avail, int *availsz) 132{ |
| 112 struct bi_mem_region *mr; 113 int i; | 133 uint32_t memsize; 134 int i, rv; |
| 114 | 135 |
| 115 /* Initialize memory regions table */ 116 mr = bootinfo_mr(); 117 for (i = 0; i < bootinfo->bi_mem_reg_no; i++, mr++) { 118 if (i == MEM_REGIONS) 119 break; 120 if (mr->mem_base < 1048576) { | 136 rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 137 138 if (rv != 0) 139 return; 140 141 for (i = 0; i < *availsz; i++) { 142 if (avail_regions[i].mr_start < 1048576) { 143 avail_regions[i].mr_size = 144 avail_regions[i].mr_size - 145 (1048576 - avail_regions[i].mr_start); |
| 121 avail_regions[i].mr_start = 1048576; | 146 avail_regions[i].mr_start = 1048576; |
| 122 avail_regions[i].mr_size = mr->mem_size - 123 (1048576 - mr->mem_base); 124 } else { 125 avail_regions[i].mr_start = mr->mem_base; 126 avail_regions[i].mr_size = mr->mem_size; | |
| 127 } 128 } | 147 } 148 } |
| 129 *availsz = i; | |
| 130 *avail = avail_regions; 131 132 /* On the bare metal platform phys == avail memory */ 133 *physsz = *availsz; 134 *phys = *avail; 135} 136 137static u_long 138bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 139{ 140 u_long ticks = -1; | 149 *avail = avail_regions; 150 151 /* On the bare metal platform phys == avail memory */ 152 *physsz = *availsz; 153 *phys = *avail; 154} 155 156static u_long 157bare_timebase_freq(platform_t plat, struct cpuref *cpuref) 158{ 159 u_long ticks = -1; |
| 160 phandle_t cpus, child; 161 pcell_t freq; |
|
| 141 | 162 |
| 163 if ((cpus = OF_finddevice("/cpus")) == 0) 164 goto out; 165 166 if ((child = OF_child(cpus)) == 0) 167 goto out; 168 169 if (OF_getprop(child, "bus-frequency", (void *)&freq, 170 sizeof(freq)) <= 0) 171 goto out; |
|
| 142 /* 143 * Time Base and Decrementer are updated every 8 CCB bus clocks. 144 * HID0[SEL_TBCLK] = 0 145 */ | 172 /* 173 * Time Base and Decrementer are updated every 8 CCB bus clocks. 174 * HID0[SEL_TBCLK] = 0 175 */ |
| 146 ticks = bootinfo->bi_bus_clk / 8; | 176 ticks = freq / 8; 177out: |
| 147 if (ticks <= 0) 148 panic("Unable to determine timebase frequency!"); 149 150 return (ticks); 151} 152 153static int 154bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) --- 77 unchanged lines hidden --- | 178 if (ticks <= 0) 179 panic("Unable to determine timebase frequency!"); 180 181 return (ticks); 182} 183 184static int 185bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) --- 77 unchanged lines hidden --- |