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machdep_e500.c (257178) machdep_e500.c (292903)
1/*-
2 * Copyright (c) 2011-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2011-2012 Semihalf.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/powerpc/booke/machdep_e500.c 257178 2013-10-26 18:18:14Z nwhitehorn $");
28__FBSDID("$FreeBSD: head/sys/powerpc/booke/machdep_e500.c 292903 2015-12-30 03:43:25Z jhibbits $");
29
29
30#include <sys/cdefs.h>
30#include <sys/types.h>
31#include <sys/types.h>
32#include <sys/param.h>
33#include <sys/proc.h>
31#include <sys/reboot.h>
32
34#include <sys/reboot.h>
35
36#include <vm/vm.h>
37#include <vm/pmap.h>
38
33#include <machine/machdep.h>
34
35#include <dev/fdt/fdt_common.h>
36
37#include <powerpc/mpc85xx/mpc85xx.h>
38
39extern void dcache_enable(void);
40extern void dcache_inval(void);
41extern void icache_enable(void);
42extern void icache_inval(void);
43extern void l2cache_enable(void);
44extern void l2cache_inval(void);
39#include <machine/machdep.h>
40
41#include <dev/fdt/fdt_common.h>
42
43#include <powerpc/mpc85xx/mpc85xx.h>
44
45extern void dcache_enable(void);
46extern void dcache_inval(void);
47extern void icache_enable(void);
48extern void icache_inval(void);
49extern void l2cache_enable(void);
50extern void l2cache_inval(void);
51extern void bpred_enable(void);
45
46void
47booke_init_tlb(vm_paddr_t fdt_immr_pa)
48{
49
50}
51
52void

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74 }
75
76 csr = mfspr(SPR_L1CSR1);
77 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
78 printf("L1 I-cache %sabled\n",
79 (csr & L1CSR1_ICE) ? "en" : "dis");
80}
81
52
53void
54booke_init_tlb(vm_paddr_t fdt_immr_pa)
55{
56
57}
58
59void

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81 }
82
83 csr = mfspr(SPR_L1CSR1);
84 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
85 printf("L1 I-cache %sabled\n",
86 (csr & L1CSR1_ICE) ? "en" : "dis");
87}
88
82#if 0
83void
84booke_enable_l2_cache(void)
85{
86 uint32_t csr;
87
88 /* Enable L2 cache on E500mc */
89 if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
90 (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {

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97 csr = mfspr(SPR_L2CSR0);
98 if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
99 printf("L2 cache %sabled\n",
100 (csr & L2CSR0_L2E) ? "en" : "dis");
101 }
102}
103
104void
89void
90booke_enable_l2_cache(void)
91{
92 uint32_t csr;
93
94 /* Enable L2 cache on E500mc */
95 if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
96 (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {

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103 csr = mfspr(SPR_L2CSR0);
104 if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
105 printf("L2 cache %sabled\n",
106 (csr & L2CSR0_L2E) ? "en" : "dis");
107 }
108}
109
110void
105booke_enable_l3_cache(void)
111booke_enable_bpred(void)
106{
112{
107 uint32_t csr, size, ver;
113 uint32_t csr;
108
114
109 /* Enable L3 CoreNet Platform Cache (CPC) */
110 ver = SVR_VER(mfspr(SPR_SVR));
111 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 ||
112 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) {
113 csr = ccsr_read4(OCP85XX_CPC_CSR0);
114 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) {
115 l3cache_inval();
116 l3cache_enable();
117 }
118
119 csr = ccsr_read4(OCP85XX_CPC_CSR0);
120 if ((boothowto & RB_VERBOSE) != 0 ||
121 (csr & OCP85XX_CPC_CSR0_CE) == 0) {
122 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0));
123 printf("L3 Corenet Platform Cache: %d KB %sabled\n",
124 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ?
125 "dis" : "en");
126 }
127 }
115 bpred_enable();
116 csr = mfspr(SPR_BUCSR);
117 if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0)
118 printf("Branch Predictor %sabled\n",
119 (csr & BUCSR_BPEN) ? "en" : "dis");
128}
129
130void
131booke_disable_l2_cache(void)
132{
133}
120}
121
122void
123booke_disable_l2_cache(void)
124{
125}
134
135static void
136l3cache_inval(void)
137{
138
139 /* Flash invalidate the CPC and clear all the locks */
140 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI |
141 OCP85XX_CPC_CSR0_LFC);
142 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI |
143 OCP85XX_CPC_CSR0_LFC))
144 ;
145}
146
147static void
148l3cache_enable(void)
149{
150
151 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE |
152 OCP85XX_CPC_CSR0_PE);
153 /* Read back to sync write */
154 ccsr_read4(OCP85XX_CPC_CSR0);
155}
156#endif